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| Preliminary User's Manual VR4102TM 64/32-bit Microprocessor PPD30102 Document No. U12739EJ2V0UM00 (2nd edition) Date Published January 1998 N CP(K) (c) 1997 (c) MIPS Technologies, Inc. 1996 Printed in Japan [MEMO] 2 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. VR3000, VR4000, VR4100, VR4101, VR4102, VR4200, VR4400, and VR Series are trademarks of NEC Corporation. MIPS is a trademark of MIPS Technologies, Inc. iAPX is a trademark of Intel Corp. DEC VAX is a trademark of Digital Equipment Corp. UNIX is a registered trademark in the United States and other countries, licensed exclusively through X/Open Company, Ltd. 3 Exporting this product or equipment that include this product may require a governmental license from the U.S.A. for some countries because this product utilizes technologies limited by the export control regulations of the U.S.A. The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M7 96. 5 4 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829 J97. 8 5 [MEMO] 6 PREFACE Readers This manual targets users who intends to understand the functions of the VR4102 and to design application systems using this microprocessor. This manual introduces the architecture and hardware functions of the VR4102 to users, following the organization described below. This manual consists of the following contents: * * * * * * * * Introduction Pipeline operation Cache organization and memory management system Exception processing Initialization interface Interrupts Peripheral units Instruction set details Purpose Organization How to read this manual It is assumed that the reader of this manual has general knowledge in the fields of electric engineering, logic circuits, and microcomputers. The VR4000TM in this manual includes the VR4400TM. To learn in detail about the function of a specific instruction, o Read Chapter 3 CPU Instruction Set Summary and Chapter 27 CPU Instruction Set Details. To learn about the overall functions of the VR4102, o Read this manual in sequential order. To learn about electrical specifications, o Refer to Data Sheet which is separately available. Legend Higher on left and lower on right XXX# (trailing # after pin and signal names) binary/decimal ... XXXX hexadecimal ... 0xXXXX Prefixes representing an exponent of 2 (for address space or memory capacity): K (kilo) 210 = 1024 20 2 M (mega) 2 = 1024 30 3 G (giga) 2 = 1024 40 4 T (tera) 2 = 1024 50 5 P (peta) 2 = 1024 60 6 E (exa) 2 = 1024 Data significance: Active low: Numeric representation: 7 Related Documents The related documents indicated here may include preliminary version. However, preliminary versions are not marked as such. * User's manual VR4102 User's Manual TM VR4100 User's Manual * Data sheet VR4102 Data Sheet This manual U10050E U12543E * Application note VR4102 Application Note To be prepared Note VR SeriesTM Application Note programming guide U10710J Note This document number is that of the Japanese version. 8 CONTENTS CHAPTER 1 INTRODUCTION .............................................................................................................. 1.1 1.2 1.3 1.4 FEATURES.............................................................................................................................. ORDERING INFORMATION .................................................................................................. 64-BIT ARCHITECTURE........................................................................................................ VR4102 PROCESSOR ............................................................................................................ 1.4.1 Internal Block Structure............................................................................................................. 1.4.2 I/O Registers ............................................................................................................................... 29 29 30 30 30 31 33 1.5 VR4100 CPU CORE ............................................................................................................... 1.5.1 VR4100 CPU Core ....................................................................................................................... 1.5.2 CPU Registers ............................................................................................................................ 1.5.3 CPU Instruction Set Overview................................................................................................... 1.5.4 Data Formats and Addressing .................................................................................................. 1.5.5 Coprocessors (CP0-CP3)........................................................................................................... 1.5.6 Floating-Point Unit (FPU)........................................................................................................... 1.5.7 Cache .......................................................................................................................................... 43 43 45 46 47 49 51 51 1.6 CPU CORE MEMORY MANAGEMENT SYSTEM (MMU)................................................. 1.6.1 Translation Lookaside Buffer (TLB) ......................................................................................... 1.6.2 Operating Modes ........................................................................................................................ 52 52 52 1.7 1.8 INSTRUCTION PIPELINE ...................................................................................................... CLOCK INTERFACE.............................................................................................................. 53 53 57 57 62 63 65 65 66 67 68 68 69 69 69 70 71 71 72 CHAPTER 2 PIN FUNCTIONS............................................................................................................. 2.1 2.2 PIN CONFIGURATION........................................................................................................... PIN FUNCTION DESCRIPTION............................................................................................ 2.2.1 System Bus Interface Signals ................................................................................................... 2.2.2 Clock Interface Signals.............................................................................................................. 2.2.3 Battery Monitor Interface Signals ............................................................................................. 2.2.4 Initialization Interface Signals................................................................................................... 2.2.5 RS-232-C Interface Signals........................................................................................................ 2.2.6 IrDA Interface Signals ................................................................................................................ 2.2.7 Debug Serial Interface Signals.................................................................................................. 2.2.8 Keyboard Interface Signals ....................................................................................................... 2.2.9 Audio Interface Signals ............................................................................................................. 2.2.10 Touch Panel/General Purpose A/D Interface Signals ........................................................... 2.2.11 General-purpose I/O Signals ................................................................................................... 2.2.12 HSP MODEM Interface Signals ............................................................................................... 2.2.13 LED Interface Signal ................................................................................................................ 2.2.14 Dedicated VDD and GND Signals ............................................................................................. 2.3 PIN STATUS UPON SPECIFIC STATES ........................................................................... 2.3.1 Pin Status upon Reset ............................................................................................................... 2.3.2 Connection of Unused Pins and Pin I/O Circuits .................................................................... 2.3.3 Pin I/O Circuits ........................................................................................................................... 73 73 76 79 9 CHAPTER 3 CPU INSTRUCTION SET SUMMARY .......................................................................... 3.1 3.2 81 CPU INSTRUCTION FORMATS ........................................................................................... 81 INSTRUCTION CLASSES...................................................................................................... 82 3.2.1 Load and Store Instructions...................................................................................................... 3.2.2 Computational Instructions....................................................................................................... 3.2.3 Jump and Branch Instructions.................................................................................................. 3.2.4 Special Instructions ................................................................................................................... 3.2.5 System Control Coprocessor (CP0) Instructions .................................................................... 82 86 92 96 97 CHAPTER 4 VR4102 PIPELINE ........................................................................................................... 4.1 4.2 4.3 4.4 4.5 PIPELINE STAGES ................................................................................................................ BRANCH DELAY.................................................................................................................... LOAD DELAY ......................................................................................................................... PIPELINE OPERATION.......................................................................................................... INTERLOCK AND EXCEPTION HANDLING....................................................................... 99 99 102 102 102 109 4.1.1 Pipeline Activities....................................................................................................................... 100 4.5.1 Exception Conditions................................................................................................................. 112 4.5.2 Stall Conditions .......................................................................................................................... 113 4.5.3 Slip Conditions ........................................................................................................................... 114 4.5.4 Bypassing ................................................................................................................................... 115 4.6 CODE COMPATIBILITY ......................................................................................................... 115 CHAPTER 5 MEMORY MANAGEMENT SYSTEM............................................................................. 117 5.1 5.2 TRANSLATION LOOKASIDE BUFFER (TLB) .................................................................... 117 VIRTUAL ADDRESS SPACE................................................................................................ 117 5.2.1 Virtual-to-Physical Address Translation .................................................................................. 118 5.2.2 32-bit Mode Address Translation.............................................................................................. 119 5.2.3 64-bit Mode Address Translation.............................................................................................. 120 5.2.4 Operating Modes ........................................................................................................................ 121 5.2.5 User Mode Virtual Addressing .................................................................................................. 121 5.2.6 Supervisor-mode Virtual Addressing ....................................................................................... 124 5.2.7 Kernel-mode Virtual Addressing............................................................................................... 127 5.3 PHYSICAL ADDRESS SPACE ............................................................................................. 135 5.3.1 ROM Space.................................................................................................................................. 137 5.3.2 System Bus Space ..................................................................................................................... 138 5.3.3 Internal I/O Space ....................................................................................................................... 139 5.3.4 LCD Space .................................................................................................................................. 140 5.3.5 DRAM Space ............................................................................................................................... 140 5.4 5.5 SYSTEM CONTROL COPROCESSOR ................................................................................ 141 5.4.1 Format of a TLB Entry................................................................................................................ 142 CP0 REGISTERS.................................................................................................................... 146 5.5.1 Index Register (0) ....................................................................................................................... 146 5.5.2 Random Register (1) .................................................................................................................. 146 5.5.3 EntryHi (10), EntryLo0 (2), EntryLo1 (3), and PageMask (5) Registers.................................. 147 5.5.4 Wired Register (6)....................................................................................................................... 148 10 5.5.5 Processor Revision Identifier (PRId) Register (15) ................................................................. 149 5.5.6 Config Register (16) ................................................................................................................... 150 5.5.7 Load Linked Address (LLAddr) Register (17).......................................................................... 151 5.5.8 Cache Tag Registers (TagLo (28) and TagHi (29)) .................................................................. 152 5.5.9 Virtual-to-Physical Address Translation .................................................................................. 153 5.5.10 TLB Misses ............................................................................................................................... 155 5.5.11 TLB Instructions....................................................................................................................... 155 CHAPTER 6 EXCEPTION PROCESSING........................................................................................... 157 6.1 6.2 6.3 HOW EXCEPTION PROCESSING WORKS........................................................................ 157 PRECISION OF EXCEPTIONS ............................................................................................. 158 EXCEPTION PROCESSING REGISTERS ........................................................................... 159 6.3.1 Context Register (4) ................................................................................................................... 160 6.3.2 BadVAddr Register (8) ............................................................................................................... 161 6.3.3 Count Register (9) ...................................................................................................................... 161 6.3.4 Compare Register (11) ............................................................................................................... 162 6.3.5 Status Register (12) ................................................................................................................... 162 6.3.6 Cause Register (13).................................................................................................................... 165 6.3.7 Exception Program Counter (EPC) Register (14) .................................................................... 167 6.3.8 WatchLo (18) and WatchHi (19) Registers ............................................................................... 168 6.3.9 XContext Register (20)............................................................................................................... 169 6.3.10 Parity Error Register (26)......................................................................................................... 170 6.3.11 Cache Error Register (27) ........................................................................................................ 171 6.3.12 ErrorEPC Register (30) ............................................................................................................ 171 6.4 DETAILS OF EXCEPTIONS ................................................................................................. 173 6.4.1 Exception Types......................................................................................................................... 173 6.4.2 Exception Vector Locations ...................................................................................................... 173 6.4.3 Priority of Exceptions ................................................................................................................ 176 6.4.4 Cold Reset Exception ................................................................................................................ 177 6.4.5 Soft Reset Exception ................................................................................................................. 178 6.4.6 NMI Exception ............................................................................................................................ 179 6.4.7 Address Error Exception ........................................................................................................... 180 6.4.8 TLB Exceptions .......................................................................................................................... 181 6.4.9 Cache Error Exception............................................................................................................... 184 6.4.10 Bus Error Exception................................................................................................................. 185 6.4.11 System Call Exception............................................................................................................. 186 6.4.12 Breakpoint Exception .............................................................................................................. 186 6.4.13 Coprocessor Unusable Exception.......................................................................................... 187 6.4.14 Reserved Instruction Exception ............................................................................................. 188 6.4.15 Trap Exception ......................................................................................................................... 188 6.4.16 Integer Overflow Exception..................................................................................................... 189 6.4.17 Watch Exception ...................................................................................................................... 189 6.4.18 Interrupt Exception .................................................................................................................. 190 6.5 EXCEPTION PROCESSING AND SERVICING FLOWCHARTS ....................................... 191 11 CHAPTER 7 INITIALIZATION INTERFACE ........................................................................................ 199 7.1 RESET FUNCTION................................................................................................................. 199 7.1.1 RTC Reset ................................................................................................................................... 199 7.1.2 RSTSW ........................................................................................................................................ 201 7.1.3 Deadman's Switch...................................................................................................................... 202 7.1.4 Software Shutdown .................................................................................................................... 203 7.1.5 HALTimer Shutdown .................................................................................................................. 204 7.2 7.3 POWERON SEQUENCE ........................................................................................................ 205 RESET OF THE CPU CORE ............................................................................................... 207 7.3.1 Cold Reset................................................................................................................................... 207 7.3.2 Soft Reset.................................................................................................................................... 208 7.4 VR4102 PROCESSOR MODES ............................................................................................. 210 7.4.1 Power Modes .............................................................................................................................. 210 7.4.2 Privilege Mode ............................................................................................................................ 211 7.4.3 Reverse Endian .......................................................................................................................... 211 7.4.4 Bootstrap Exception Vector (BEV) ........................................................................................... 211 7.4.5 Cache Error Check ..................................................................................................................... 212 7.4.6 Parity Error Prohibit ................................................................................................................... 212 7.4.7 Interrupt Enable (IE) ................................................................................................................... 212 CHAPTER 8 CACHE MEMORY ........................................................................................................... 213 8.1 8.2 MEMORY ORGANIZATION ................................................................................................... 213 CACHE ORGANIZATION....................................................................................................... 214 8.2.1 Organization of the Instruction Cache (I-Cache) ..................................................................... 214 8.2.2 Organization of the Data Cache (D-Cache) .............................................................................. 215 8.2.3 Accessing the Caches ............................................................................................................... 216 8.3 8.4 8.5 CACHE OPERATIONS........................................................................................................... 217 8.3.1 Cache Write Policy ..................................................................................................................... 217 CACHE STATES .................................................................................................................... 218 CACHE STATE TRANSITION DIAGRAMS ......................................................................... 219 8.5.1 Data Cache State Transition...................................................................................................... 219 8.5.2 Instruction Cache State Transition ........................................................................................... 219 8.6 8.7 CACHE DATA INTEGRITY ................................................................................................... 220 MANIPULATION OF THE CACHES BY AN EXTERNAL AGENT .................................. 230 CHAPTER 9 CPU CORE INTERRUPTS............................................................................................. 231 9.1 9.2 9.3 9.4 9.5 NON-MASKABLE INTERRUPT (NMI) .................................................................................. ORDINARY INTERRUPTS ..................................................................................................... SOFTWARE INTERRUPTS GENERATED IN CPU CORE ............................................... TIMER INTERRUPT................................................................................................................ ASSERTING INTERRUPTS ................................................................................................... 231 231 232 232 232 9.5.1 Detecting Hardware Interrupts .................................................................................................. 232 9.5.2 Masking Interrupt Signals.......................................................................................................... 234 12 CHAPTER 10 BCU (BUS CONTROL UNIT) ..................................................................................... 235 10.1 GENERAL................................................................................................................................ 235 10.2 REGISTER SET...................................................................................................................... 235 10.2.1 BCUCNTREG 1 (0x0B00 0000) ................................................................................................ 236 10.2.2 BCUCNTREG 2 (0x0B00 0002) ................................................................................................ 238 10.2.3 BCUSPEEDREG (0x0B00 000A) .............................................................................................. 239 10.2.4 BCUERRSTREG (0x0B00 000C) .............................................................................................. 241 10.2.5 BCURFCNTREG (0x0B00 000E) .............................................................................................. 242 10.2.6 REVIDREG (0x0B00 0010)........................................................................................................ 243 10.2.7 BCURFCOUNTREG (0x0B00 0012) ......................................................................................... 244 10.2.8 CLKSPEEDREG (0x0B00 0014) ............................................................................................... 245 10.3 CONNECTION OF ADDRESS PINS.................................................................................... 246 10.4 NOTES ON USING BCU ...................................................................................................... 247 10.4.1 CPU Core Bus Modes .............................................................................................................. 247 10.4.2 Access Data Size...................................................................................................................... 247 10.4.3 ROM Interface ........................................................................................................................... 248 10.4.4 Flash Memory Interface ........................................................................................................... 249 10.4.5 LCD Control Interface .............................................................................................................. 250 10.4.6 Illegal Access Notification....................................................................................................... 251 10.5 BUS OPERATIONS................................................................................................................ 252 10.5.1 ROM Access ............................................................................................................................. 252 10.5.2 System Bus Access ................................................................................................................. 256 10.5.3 LCD Interface............................................................................................................................ 263 10.5.4 DRAM Access (EDO Type) ...................................................................................................... 264 10.5.5 Refresh...................................................................................................................................... 267 10.5.6 Bus Hold ................................................................................................................................... 268 CHAPTER 11 DMAAU (DMA ADDRESS UNIT)................................................................................ 271 11.1 GENERAL................................................................................................................................ 271 11.2 REGISTER SET...................................................................................................................... 272 11.2.1 AIU IN DMA Base Address Registers ..................................................................................... 273 11.2.2 AIU IN DMA Address Registers............................................................................................... 275 11.2.3 AIU OUT DMA Base Address Registers ................................................................................. 276 11.2.4 AIU OUT DMA Address Registers........................................................................................... 278 11.2.5 FIR DMA Base Address Registers .......................................................................................... 279 11.2.6 FIR DMA Address Registers.................................................................................................... 280 CHAPTER 12 DCU (DMA CONTROL UNIT) ..................................................................................... 281 12.1 GENERAL................................................................................................................................ 281 12.2 DMA PRIORITY CONTROL .................................................................................................. 281 12.3 REGISTER SET...................................................................................................................... 281 12.3.1 DMARSTREG (0x0B00 0040) ................................................................................................... 282 12.3.2 DMAIDLEREG (0x0B00 0042) .................................................................................................. 283 12.3.3 DMASENREG (0x0B00 0044) ................................................................................................... 284 12.3.4 DMAMSKREG (0x0B00 0046) .................................................................................................. 285 13 12.3.5 DMAREQREG (0x0B00 0048) ................................................................................................... 286 12.3.6 TDREG (0x0B00 004A) ............................................................................................................. 287 CHAPTER 13 CMU (CLOCK MASK UNIT) ....................................................................................... 289 13.1 GENERAL................................................................................................................................ 289 13.2 REGISTER SET ...................................................................................................................... 289 13.2.1 CMUCLKMSK (0x0B00 0060) ................................................................................................... 290 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) .......................................................................... 291 14.1 GENERAL................................................................................................................................ 291 14.2 REGISTER SET ...................................................................................................................... 294 14.2.1 SYSINT1REG (0x0B00 0080).................................................................................................... 295 14.2.2 PIUINTREG (0x0B00 0082) ....................................................................................................... 297 14.2.3 AIUINTREG (0x0B00 0084)....................................................................................................... 298 14.2.4 KIUINTREG (0x0B00 0086)....................................................................................................... 299 14.2.5 GIUINTLREG (0x0B00 0088) .................................................................................................... 300 14.2.6 DSIUINTREG (0x0B00 008A).................................................................................................... 301 14.2.7 MSYSINT1REG (0x0B00 008C) ................................................................................................ 302 14.2.8 MPIUINTREG (0x0B00 008E).................................................................................................... 304 14.2.9 MAIUINTREG (0x0B00 0090).................................................................................................... 305 14.2.10 MKIUINTREG (0x0B00 0092).................................................................................................. 306 14.2.11 MGIUINTLREG (0x0B00 0094) ............................................................................................... 307 14.2.12 MDSIUINTREG (0x0B00 0096) ............................................................................................... 308 14.2.13 NMIREG (0x0B00 0098) .......................................................................................................... 309 14.2.14 SOFTINTREG (0x0B00 009A)................................................................................................. 310 14.2.15 SYSINT2REG (0x0B00 0200).................................................................................................. 311 14.2.16 GIUINTHREG (0x0B00 0202) .................................................................................................. 312 14.2.17 FIRINTREG (0x0B00 0204) ..................................................................................................... 313 14.2.18 MSYSINT2REG (0x0B00 0206)............................................................................................... 314 14.2.19 MGIUINTHREG (0x0B00 0208) ............................................................................................... 315 14.2.20 MFIRINTREG (0x0B00 020A).................................................................................................. 316 14.3 NOTES FOR REGISTER SETTING ..................................................................................... 317 CHAPTER 15 PMU (POWER MANAGEMENT UNIT) ....................................................................... 319 15.1 GENERAL................................................................................................................................ 319 15.1.1 Reset Control ............................................................................................................................ 319 15.1.2 Shutdown Control .................................................................................................................... 320 15.1.3 Power-on Control ..................................................................................................................... 321 15.1.4 Power Mode .............................................................................................................................. 324 15.2 REGISTER SET ...................................................................................................................... 327 15.2.1 PMUINTREG (0x0B00 00A0) .................................................................................................... 328 15.2.2 PMUCNTREG (0x0B00 00A2) ................................................................................................... 330 15.2.3 PMUINT2REG (0x0B00 00A4) .................................................................................................. 332 15.2.4 PMUCNT2REG (0x0B00 00A6) ................................................................................................. 333 14 CHAPTER 16 RTC (REALTIME CLOCK UNIT) ................................................................................ 335 16.1 GENERAL................................................................................................................................ 335 16.2 REGISTER SET...................................................................................................................... 336 16.2.1 Elapsed Time Registers........................................................................................................... 337 16.2.2 Elapsed Time Compare Registers .......................................................................................... 339 16.2.3 RTC Long 1 Registers.............................................................................................................. 341 16.2.4 RTC Long 1 Count Registers .................................................................................................. 343 16.2.5 RTC Long 2 Registers.............................................................................................................. 345 16.2.6 RTC Long 2 Count Registers .................................................................................................. 347 16.2.7 TClock Counter Registers ....................................................................................................... 349 16.2.8 TClock Counter Count Registers............................................................................................ 351 16.2.9 RTC Interrupt Register............................................................................................................. 353 CHAPTER 17 DSU (DEADMAN'S SWITCH UNIT) ........................................................................... 355 17.1 GENERAL................................................................................................................................ 355 17.2 REGISTER SET...................................................................................................................... 355 17.2.1 DSUCNTREG (0x0B00 00E0) ................................................................................................... 356 17.2.2 DSUSETREG (0x0B00 00E2).................................................................................................... 357 17.2.3 DSUCLRREG (0x0B00 00E4) .................................................................................................. 358 17.2.4 DSUTIMREG (0x0B00 00E6) .................................................................................................... 359 17.3 REGISTER SETTING FLOW ................................................................................................ 360 CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) ...................................................................... 361 18.1 GENERAL................................................................................................................................ 361 18.2 REGISTER SET...................................................................................................................... 362 18.2.1 GIUIOSELL (0x0B00 0100) ....................................................................................................... 363 18.2.2 GIUIOSELH (0x0B00 0102)....................................................................................................... 364 18.2.3 GIUPIODL (0x0B00 0104) ......................................................................................................... 365 18.2.4 GIUPIODH (0x0B00 0106)......................................................................................................... 366 18.2.5 GIUINTSTATL (0x0B00 0108)................................................................................................... 367 18.2.6 GIUINTSTATH (0x0B00 010A).................................................................................................. 368 18.2.7 GIUINTENL (0x0B00 010C) ...................................................................................................... 369 18.2.8 GIUINTENH (0x0B00 010E) ...................................................................................................... 370 18.2.9 GIUINTTYPL (0x0B00 0110) ..................................................................................................... 371 18.2.10 GIUINTTYPH (0x0B00 0112)................................................................................................... 372 18.2.11 GIUINTALSELL (0x0B00 0114) .............................................................................................. 373 18.2.12 GIUINTALSELH (0x0B00 0116).............................................................................................. 374 18.2.13 GIUINTHTSELL (0x0B00 0118) .............................................................................................. 375 18.2.14 GIUINTHTSELH (0x0B00 011A) ............................................................................................. 376 18.2.15 GIUPODATL (0x0B00 011C)................................................................................................... 378 18.2.16 GIUPODATH (0x0B00 011E) .................................................................................................. 380 15 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) ................................................................. 381 19.1 GENERAL................................................................................................................................ 381 19.1.1 Block Diagrams ........................................................................................................................ 382 19.2 SCAN SEQUENCER STATE TRANSITION ........................................................................ 384 19.3 REGISTER SET ...................................................................................................................... 386 19.3.1 PIUCNTREG (0x0B00 0122) ..................................................................................................... 387 19.3.2 PIUINTREG (0x0B00 0124) ....................................................................................................... 390 19.3.3 PIUSIVLREG (0x0B00 0126)..................................................................................................... 391 19.3.4 PIUSTBLREG (0x0B00 0128) ................................................................................................... 392 19.3.5 PIUCMDREG (0x0B00 012A) .................................................................................................... 393 19.3.6 PIUASCNREG (0x0B00 0130)................................................................................................... 395 19.3.7 PIUAMSKREG (0x0B00 0132) .................................................................................................. 397 19.3.8 PIUCIVLREG (0x0B00 013E) .................................................................................................... 398 19.3.9 PIUPBnmREG (0x0B00 02A0 to 0x0B00 02AE, 0x0B00 02BC to 0x0B00 02BE) ................. 399 19.3.10 PIUABnREG (0x0B00 02B0 to 0x0B00 02B6) ....................................................................... 400 19.4 REGISTER SETTING FLOW................................................................................................. 401 19.5 RELATIONSHIPS AMONG TPX, TPY, AND ADIN PINS AND STATES ....................... 403 19.6 TIMING..................................................................................................................................... 404 19.6.1 Touch/Release Detection Timing ............................................................................................ 404 19.6.2 A/D Port Scan Timing............................................................................................................... 404 19.7 DATA LOSS INTERRUPT CONDITIONS ............................................................................ 405 TM 19.8 COMPARISON OF VR4102 AND VR4101 ....................................................................... 407 CHAPTER 20 AIU (AUDIO INTERFACE UNIT)................................................................................. 409 20.1 GENERAL................................................................................................................................ 409 20.2 REGISTER SET ...................................................................................................................... 409 20.2.1 MDMADATREG (0x0B00 0160) ................................................................................................ 410 20.2.2 SDMADATREG (0x0B00 0162) ................................................................................................. 411 20.2.3 SODATREG (0x0B00 0166) ...................................................................................................... 412 20.2.4 SCNTREG (0x0B00 0168) ......................................................................................................... 413 20.2.5 SCNVRREG (0x0B00 016A)...................................................................................................... 414 20.2.6 MIDATREG (0x0B00 0170) ....................................................................................................... 415 20.2.7 MCNTREG (0x0B00 0172) ........................................................................................................ 416 20.2.8 MCNVRREG (0x0B00 0174)...................................................................................................... 417 20.2.9 DVALIDREG (0x0B00 0178)...................................................................................................... 418 20.2.10 SEQREG (0x0B00 017A)......................................................................................................... 419 20.2.11 INTREG (0x0B00 017C) .......................................................................................................... 420 20.3 OPERATION SEQUENCE ...................................................................................................... 421 20.3.1 Output (Speaker) ...................................................................................................................... 421 20.3.2 Input (MIC)................................................................................................................................. 422 CHAPTER 21 KIU (KEYBOARD INTERFACE UNIT)........................................................................ 423 21.1 GENERAL................................................................................................................................ 423 21.2 REGISTER SET ...................................................................................................................... 423 21.2.1 KIUDATn (0x0B00 0180 to 0x0B00 018A) ............................................................................... 424 16 21.2.2 KIUSCANREP (0x0B00 0190)................................................................................................... 425 21.2.3 KIUSCANS (0x0B00 0192)........................................................................................................ 427 21.2.4 KIUWKS (0x0B00 0194)............................................................................................................ 429 21.2.5 KIUWKI (0x0B00 0196) ............................................................................................................. 430 21.2.6 KIUINT (0x0B00 0198) .............................................................................................................. 431 21.2.7 KIURST (0x0B00 019A) ............................................................................................................ 432 21.2.8 KIUGPEN (0x0B00 019C) ......................................................................................................... 433 21.2.9 SCANLINE (0x0B00 019E)........................................................................................................ 434 CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT) ............................................................. 435 22.1 GENERAL................................................................................................................................ 435 22.2 REGISTER SET...................................................................................................................... 435 22.2.1 PORTREG (0x0B00 01A0) ........................................................................................................ 436 22.2.2 MODEMREG (0x0B00 01A2) .................................................................................................... 437 22.2.3 ASIM00REG (0x0B00 01A4) ..................................................................................................... 438 22.2.4 ASIM01REG (0x0B00 01A6) ..................................................................................................... 439 22.2.5 RXB0RREG (0x0B00 01A8)...................................................................................................... 440 22.2.6 RXB0LREG (0x0B00 01AA)...................................................................................................... 441 22.2.7 TXS0RREG (0x0B00 01AC)...................................................................................................... 442 22.2.8 TXS0LREG (0x0B00 01AE) ...................................................................................................... 443 22.2.9 ASIS0REG (0x0B00 01B0)........................................................................................................ 444 22.2.10 INTR0REG (0x0B00 01B2)...................................................................................................... 445 22.2.11 BPRM0REG (0x0B00 01B6) ................................................................................................... 446 22.2.12 DSIURESETREG (0x0B00 01B8) ........................................................................................... 447 22.3 DESCRIPTION OF OPERATIONS........................................................................................ 448 22.3.1 Data Format .............................................................................................................................. 448 22.3.2 Transmission............................................................................................................................ 449 22.3.3 Reception.................................................................................................................................. 451 CHAPTER 23 LED (LED CONTROL UNIT) ...................................................................................... 453 23.1 GENERAL................................................................................................................................ 453 23.2 REGISTER SET...................................................................................................................... 453 23.2.1 LEDHTSREG (0x0B00 0240) .................................................................................................... 454 23.2.2 LEDLTSREG (0x0B00 0242)..................................................................................................... 455 23.2.3 LEDCNTREG (0x0B00 0248) .................................................................................................... 456 23.2.4 LEDASTCREG (0x0B00 024A) ................................................................................................. 457 23.2.5 LEDINTREG (0x0B00 024C) ..................................................................................................... 458 23.3 OPERATION FLOW ............................................................................................................... 459 CHAPTER 24 SIU (SERIAL INTERFACE UNIT) ............................................................................... 461 24.1 GENERAL................................................................................................................................ 461 24.2 REGISTER SET...................................................................................................................... 461 24.2.1 SIURB (0x0C00 0000: LCR[7] = 0, Read) ................................................................................ 462 24.2.2 SIUTH (0x0C00 0000: LCR[7] = 0, Write)................................................................................. 462 24.2.3 SIUDLL (0x0C00 0000: LCR[7] = 1) ......................................................................................... 463 17 24.2.4 SIUIE (0x0C00 0001: LCR[7] = 0) ............................................................................................. 464 24.2.5 SIUDLM (0x0C00 0001: LCR[7] = 1)......................................................................................... 465 24.2.6 SIUIID (0x0C00 0002: Read) ..................................................................................................... 467 24.2.7 SIUFC (0x0C00 0002: Write)..................................................................................................... 469 24.2.8 SIULC (0x0C00 0003)................................................................................................................ 472 24.2.9 SIUMC (0x0C00 0004) ............................................................................................................... 473 24.2.10 SIULS (0x0C00 0005) .............................................................................................................. 474 24.2.11 SIUMS (0x0C00 0006) ............................................................................................................. 476 24.2.12 SIUSC (0x0C00 0007).............................................................................................................. 477 24.2.13 SIUIRSEL (0x0C00 0008) ........................................................................................................ 478 CHAPTER 25 HSP (MODEM INTERFACE UNIT) ............................................................................. 481 25.1 GENERAL................................................................................................................................ 481 25.2 REGISTER SET ...................................................................................................................... 483 25.2.1 HSP Initialize Register.............................................................................................................. 484 25.2.2 HSP Data Register, HSP Index Register ................................................................................. 485 25.2.3 HSP ID Register, HSP I/O Address Program Confirmation Register ................................... 493 25.2.4 HSP Signature Checking Port ................................................................................................. 493 25.3 POWER CONTROL ................................................................................................................ 494 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT).......................................................................... 497 26.1 GENERAL................................................................................................................................ 497 26.2 REGISTER SET ...................................................................................................................... 498 26.2.1 FRSTR (0x0C00 0040)............................................................................................................... 499 26.2.2 DPINTR (0x0C00 0042) ............................................................................................................. 500 26.2.3 DPCNTR (0x0C00 0044)............................................................................................................ 501 26.2.4 TDR (0x0C00 0050) ................................................................................................................... 502 26.2.5 RDR (0x0C00 0052)................................................................................................................... 503 26.2.6 IMR (0x0C00 0054) .................................................................................................................... 504 26.2.7 FSR (0x0C00 0056) ................................................................................................................... 505 26.2.8 IRSR1 (0x0C00 0058) ................................................................................................................ 507 26.2.9 CRCSR (0x0C00 005C) ............................................................................................................. 508 26.2.10 FIRCR (0x0C00 005E) ............................................................................................................. 509 26.2.11 MIRCR (0x0C00 0060)............................................................................................................. 511 26.2.12 DMACR (0x0C00 0062) ........................................................................................................... 512 26.2.13 DMAER (0x0C00 0064) ........................................................................................................... 513 26.2.14 TXIR (0x0C00 0066) ................................................................................................................ 514 26.2.15 RXIR (0x0C00 0068) ................................................................................................................ 515 26.2.16 IFR (0x0C00 006A) .................................................................................................................. 517 26.2.17 RXSTS (0x0C00 006C) ............................................................................................................ 519 26.2.18 TXFL (0x0C00 006E) ............................................................................................................... 521 26.2.19 MRXF (0x0C00 0070) .............................................................................................................. 522 26.2.20 RXFL (0x0C00 0074) ............................................................................................................... 523 18 CHAPTER 27 CPU INSTRUCTION SET DETAILS ........................................................................... 525 27.1 27.2 27.3 27.4 27.5 27.6 INSTRUCTION NOTATION CONVENTIONS ....................................................................... LOAD AND STORE INSTRUCTIONS.................................................................................. JUMP AND BRANCH INSTRUCTIONS............................................................................... SYSTEM CONTROL COPROCESSOR (CP0) INSTRUCTIONS ....................................... CPU INSTRUCTION............................................................................................................... CPU INSTRUCTION OPCODE BIT ENCODING ................................................................ 525 527 528 528 529 674 CHAPTER 28 VR4102 COPROCESSOR 0 HAZARDS ..................................................................... 677 CHAPTER 29 PLL PASSIVE COMPONENTS ................................................................................... 683 APPENDIX A DIFFERENCES BETWEEN VR4102 AND VR4101 .................................................... 685 A.1 A.2 SUMMARY OF DIFFERENCES ............................................................................................ 685 DETAILS OF DIFFERENCES ............................................................................................... 686 A.2.1 CPU Core .................................................................................................................................... 686 A.2.2 Address Mapping....................................................................................................................... 686 A.2.3 BCU............................................................................................................................................. 687 A.2.4 DMA ............................................................................................................................................ 688 A.2.5 ICU .............................................................................................................................................. 688 A.2.6 PMU............................................................................................................................................. 688 A.2.7 RTC ............................................................................................................................................. 688 A.2.8 GIU .............................................................................................................................................. 689 A.2.9 PIU............................................................................................................................................... 690 A.2.10 AIU ............................................................................................................................................ 691 A.2.11 KIU ............................................................................................................................................ 691 A.2.12 DSIU .......................................................................................................................................... 692 A.2.13 SIU............................................................................................................................................. 692 A.2.14 Newly Added Units .................................................................................................................. 693 APPENDIX B INDEX ............................................................................................................................. 695 19 LIST OF FIGURES (1/4) Fig. No. 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 2-1 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 Title VR4102 Internal Block Diagram and Example of Connection to External Blocks................................... VR4100 CPU Core Internal Block Diagram ............................................................................................ VR4102 CPU Registers .......................................................................................................................... CPU Instruction Formats........................................................................................................................ Little-Endian Byte Ordering in Word Data.............................................................................................. Little-Endian Byte Ordering in Double Word Data ................................................................................. Misaligned Word Accessing (Little-Endian) ........................................................................................... CP0 Registers........................................................................................................................................ External Circuit of Clock Oscillator......................................................................................................... Examples of Oscillator with Bad Connection ......................................................................................... VR4102 Signal Classification.................................................................................................................. CPU Instruction Formats........................................................................................................................ Byte Specification Related to Load and Store Instructions .................................................................... Pipeline Stages ...................................................................................................................................... Instruction Execution in the Pipeline...................................................................................................... Pipeline Activities ................................................................................................................................... Branch Delay ......................................................................................................................................... Add Instruction Pipeline Activities .......................................................................................................... JALR Instruction Pipeline Activities ....................................................................................................... BEQ Instruction Pipeline Activities......................................................................................................... TLT Instruction Pipeline Activities .......................................................................................................... LW Instruction Pipeline Activities ........................................................................................................... SW Instruction Pipeline Activities .......................................................................................................... Interlocks, Exceptions, and Faults ......................................................................................................... Exception Detection ............................................................................................................................... Data Cache Miss Stall............................................................................................................................ CACHE Instruction Stall......................................................................................................................... Load Data Interlock................................................................................................................................ MD Busy Interlock.................................................................................................................................. Virtual-to-Physical Address Translation ................................................................................................. 32-bit Mode Virtual Address Translation................................................................................................ 64-bit Mode Virtual Address Translation................................................................................................ User Mode Address Space .................................................................................................................... Supervisor Mode Address Space .......................................................................................................... Kernel Mode Address Space ................................................................................................................. xkphys Area Address Space.................................................................................................................. VR4102 Physical Address Space ........................................................................................................... CP0 Registers and the TLB ................................................................................................................... Format of a TLB Entry............................................................................................................................ Format of a TLB Entry............................................................................................................................ Page 30 43 45 46 47 48 48 49 54 55 62 81 83 99 100 100 102 103 104 105 106 107 108 109 112 113 113 114 114 118 119 120 122 125 128 129 135 141 142 143 20 LIST OF FIGURES (2/4) Fig. No. 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 8-1 8-2 8-3 8-4 8-5 8-6 Title Index Register ........................................................................................................................................ Random Register.................................................................................................................................... Positions Indicated by the Wired Register.............................................................................................. Wired Register ........................................................................................................................................ PRId Register ......................................................................................................................................... Config Register Format........................................................................................................................... LLAddr Register...................................................................................................................................... TagLo and TagHi Registers.................................................................................................................... TLB Address Translation ........................................................................................................................ Context Register Format......................................................................................................................... BadVAddr Register Format..................................................................................................................... Count Register Format ........................................................................................................................... Compare Register Format ...................................................................................................................... Status Register Format........................................................................................................................... Status Register Diagnostic Status Field ................................................................................................. Cause Register Format........................................................................................................................... EPC Register Format.............................................................................................................................. WatchLo and WatchHi Register Format ................................................................................................. XContext Register Format ...................................................................................................................... Parity Error Register Format................................................................................................................... CacheErr Register Format...................................................................................................................... The ErrorEPC Register Format .............................................................................................................. Common Exception Handler................................................................................................................... TLB/XTLB Refill Exception Handler........................................................................................................ Cache Error Exception Handler .............................................................................................................. Cold Reset, Soft Reset, and NMI Exception Handler ............................................................................. RTC Reset .............................................................................................................................................. RSTSW................................................................................................................................................... Deadman's Switch .................................................................................................................................. Software Shutdown................................................................................................................................. HALTimer Shutdown............................................................................................................................... VR4102 Activation Sequence (when Battery Check Is OK) .................................................................... VR4102 Activation Sequence (when Battery Check Is NG) .................................................................... Cold Reset .............................................................................................................................................. Soft Reset ............................................................................................................................................... Logical Hierarchy of Memory .................................................................................................................. Cache Support........................................................................................................................................ Cache Line Format ................................................................................................................................. Data Cache Line Format......................................................................................................................... Cache Data and Tag Organization ......................................................................................................... Data Cache State Diagram..................................................................................................................... Page 146 146 148 148 149 150 151 152 154 160 161 161 162 162 163 165 167 168 169 170 171 172 192 194 196 197 200 201 202 203 204 206 206 209 209 213 214 215 215 216 219 21 LIST OF FIGURES (3/4) Fig. No. 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 8-20 8-21 8-22 9-1 9-2 9-3 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-23 Title Instruction Cache State Diagram ........................................................................................................... Data flow on Instruction Fetch ............................................................................................................... Data Integrity on Load Operations ......................................................................................................... Data Integrity on Store Operations ........................................................................................................ Data Integrity on Index_Invalidate Operations....................................................................................... Data Integrity on Index_Writeback_Invalidate Operations..................................................................... Data Integrity on Index_Load_Tag Operations ...................................................................................... Data Integrity on Index_Store_Tag Operations ..................................................................................... Data Integrity on Create_Dirty Operations............................................................................................. Data Integrity on Hit_Invalidate Operations ........................................................................................... Data Integrity on Hit_Writeback_Invalidate Operations ......................................................................... Data Integrity on Fill Operations ............................................................................................................ Data Integrity on Hit_Writeback Operations........................................................................................... Data Integrity on Writeback Flow ........................................................................................................... Data Integrity on Refill Flow ................................................................................................................... Data Integrity on Writeback & Refill Flow............................................................................................... Non-maskable Interrupt Signal .............................................................................................................. Hardware Interrupt Signals .................................................................................................................... Masking of the CPU Core Interrupts ...................................................................................................... ROM 4-byte Read, 16-bit Mode (WROMA[2:0] = 110)........................................................................... ROM 4-byte Read, 32-bit Mode (WROMA[2:0] = 110)........................................................................... PageROM 4-word Read, 16-bit Mode (WROMA[2:0] = 111, WPROM[1:0] = 10) .................................. PageROM 4-word Read, 32-bit Mode (WROMA[2:0] = 111, WPROM[1:0] = 10) .................................. Flash Memory Mode, 2-byte Access...................................................................................................... 1-byte Access to Even Address Using 16-bit Bus (WISAA[2:0] = 101).................................................. 2-byte Access when Sampling IOCHRDY at High Level Using 16-bit Bus (WISAA[2:0] = 101) ............ 1-byte Access to Odd Address Using 16-bit Bus (WISAA[2:0] = 101) ................................................... 1-byte Access to Odd Address Using 8-bit Bus (WISAA[2:0] = 101) ..................................................... 2-byte Access when Sampling ZWS# at Low Level on 16-bit Bus (WISAA[2:0] = 101) ........................ 2-byte Access when Sampling ZWS# at Low Level on 8-bit Bus (WISAA[2:0] = 101) .......................... 2-byte Access on 16-bit Bus (WLCD/M[2:0] = 101) ............................................................................... 1-byte Access on 8-bit Bus (WLCD/M[2:0] = 101) ................................................................................. 2-byte Access When Sampling ZWS# at Low Level on 16-bit Bus (WLCD/M[2:0] = 101)..................... 1-byte Access When Sampling ZWS# at Low Level on 8-bit Bus (WLCD/M[2:0] = 101)....................... 2-byte Access to LCD Controller (WLCD/M[2:0] = 010)......................................................................... 2-byte Access to LCD Controller (WLCD/M[2:0] = 011)......................................................................... 4-byte Access to DRAM (16-bit Mode) .................................................................................................. 8-byte Access to DRAM (32-bit Mode) .................................................................................................. Byte Read of Odd Address in DRAM (16-bit Mode)............................................................................... Byte Read of Even Address in DRAM (16-bit Mode) ............................................................................. Byte Write to Odd Address in DRAM (16-bit Mode)............................................................................... Byte Write to Even Address in DRAM (16-bit Mode) ............................................................................. Page 219 220 221 222 223 223 224 224 225 225 226 226 227 228 228 229 231 233 234 253 253 254 255 255 256 257 258 258 259 260 261 261 262 262 263 263 264 264 265 265 266 266 22 LIST OF FIGURES (4/4) Fig. No. 10-24 10-25 10-26 10-27 11-1 13-1 14-1 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 19-1 19-2 19-3 19-4 19-5 19-6 19-7 22-1 22-2 22-3 22-4 24-1 25-1 25-2 25-3 27-1 29-1 Title CBR Refresh (16-bit Mode) .................................................................................................................... Self Refresh (16-bit Mode)...................................................................................................................... Bus Hold in Fullspeed Mode................................................................................................................... Bus Hold in Suspend Mode .................................................................................................................... DMA Space Used in DMA Transfers ...................................................................................................... Block Diagram of CMU and Peripheral Blocks ....................................................................................... Interrupt Control Outline ......................................................................................................................... Activation via Power Switch Interrupt (BATTINH/BATTINT# = 1)........................................................... Activation via Power Switch Interrupt (BATTINH/BATTINT# = 0)........................................................... Activation via GPIO Activation Interrupt (BATTINH/BATTINT# = 1)....................................................... Activation via GPIO Activation Interrupt (BATTINH/BATTINT# = 0)....................................................... Activation via DCD Interrupt (BATTINH/BATTINT# = 1)......................................................................... Activation via DCD Interrupt (BATTINH/BATTINT# = 0)......................................................................... Activation via Alarm Interrupt (BATTINH/BATTINT# = 1) ....................................................................... Activation via Alarm Interrupt (BATTINH/BATTINT# = 0) ....................................................................... Power Mode State Transition ................................................................................................................. PIU Peripheral Block Diagram ................................................................................................................ Equivalent Circuit of Coordinate Detection ............................................................................................. Internal Block Diagram of PIU ................................................................................................................ Scan Sequencer State Transition Diagram ............................................................................................ Interval Times and States ....................................................................................................................... Touch/Release Detection Timing............................................................................................................ A/D Port Scan Timing ............................................................................................................................. Data Format for Transmission and Reception ........................................................................................ Transmit Complete Interrupt Timing ....................................................................................................... Receive Complete Interrupt Timing ........................................................................................................ Receive Error Timing .............................................................................................................................. Connection Example Between The VR4102 and IrDA Module ............................................................... HSP Unit Block Diagram......................................................................................................................... Circuit Configuration Block Diagram Examples ...................................................................................... Block Diagram of HSP Interface Power Control ..................................................................................... VR4102 Opcode Bit Encoding................................................................................................................. Example of Connection of PLL Passive Components ............................................................................ Page 267 267 268 269 271 289 293 321 321 322 322 323 323 324 324 325 382 382 383 384 391 404 404 448 450 451 452 479 482 482 494 674 683 23 LIST OF TABLES (1/4) Table. No. 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 1-12 1-13 1-14 1-15 1-16 1-17 1-18 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 Title Page 33 33 34 34 35 35 36 37 37 38 39 40 40 41 41 41 42 50 63 65 65 66 67 68 68 69 69 69 70 71 71 72 73 76 82 84 85 86 87 87 88 88 BCU Registers ....................................................................................................................................... DMAAU Registers .................................................................................................................................. DCU Registers ....................................................................................................................................... CMU Register ........................................................................................................................................ ICU Registers......................................................................................................................................... PMU Registers....................................................................................................................................... RTC Registers ....................................................................................................................................... DSU Registers ....................................................................................................................................... GIU Registers ........................................................................................................................................ PIU Registers......................................................................................................................................... AIU Registers......................................................................................................................................... KIU Registers......................................................................................................................................... DSIU Registers ...................................................................................................................................... LED Registers........................................................................................................................................ SIU Registers......................................................................................................................................... HSP Registers ....................................................................................................................................... FIR Registers ......................................................................................................................................... System Control Coprocessor (CP0) Register Definitions ...................................................................... System Bus Interface Signals ................................................................................................................ Clock Interface Signals .......................................................................................................................... Battery Monitor Interface Signals........................................................................................................... Initialization Interface Signals ................................................................................................................ RS-232-C Interface Signals ................................................................................................................... IrDA Interface Signals ............................................................................................................................ Debug Serial Interface Signals .............................................................................................................. Keyboard Interface Signals.................................................................................................................... Audio Interface Signals .......................................................................................................................... Touch Panel/General Purpose A/D Interface Signals............................................................................ General-purpose I/O Signals ................................................................................................................. HSP MODEM Interface Signals ............................................................................................................. LED Interface Signal .............................................................................................................................. Dedicated VDD and GND Signals ........................................................................................................... Status of Pins upon Reset ..................................................................................................................... Connection of Unused Pins and Pin I/O Circuit Type ............................................................................ Number of Delay Slot Cycles Necessary for Load and Store Instructions............................................. Load/store Instruction ............................................................................................................................ Load/store Instruction (Extended ISA) ................................................................................................... ALU Immediate Instruction..................................................................................................................... ALU Immediate Instruction (Extended ISA) ........................................................................................... Three Operand Type Instruction ............................................................................................................ Three Operand Type Instruction (Extended ISA)................................................................................... Shift Instruction ...................................................................................................................................... 24 LIST OF TABLES (2/4) Table. No. 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 4-1 4-2 4-3 4-4 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 6-1 6-2 6-3 6-4 6-5 10-1 10-2 10-3 10-4 10-5 10-6 Title Page 89 90 90 91 92 93 94 95 96 96 97 101 110 111 111 122 126 130 132 133 136 137 137 139 139 140 140 145 147 159 166 174 174 176 235 246 246 247 248 250 Shift Instruction (Extended ISA).............................................................................................................. Multiply/Divide Instructions ..................................................................................................................... Multiply/Divide Instructions (Extended ISA)............................................................................................ Number of Stall Cycles in Multiply and Divide Instructions..................................................................... Number of Delay Slot Cycles in Jump and Branch Instructions ............................................................. Jump Instructions ................................................................................................................................... Branch Instructions ................................................................................................................................. Branch Instructions (Extended ISA)........................................................................................................ Special Instructions ................................................................................................................................ Special Instructions (Extended ISA) ....................................................................................................... System Control Coprocessor (CP0) Instructions .................................................................................... Description of Pipeline Activities during Each Stage .............................................................................. Correspondence of Pipeline Stage to Interlock and Exception Condition .............................................. Description of Pipeline Exception ........................................................................................................... Pipeline Interlock .................................................................................................................................... Comparison of useg and xuseg .............................................................................................................. 32-bit and 64-bit Supervisor Mode Segments ........................................................................................ 32-bit Kernel Mode Segments ................................................................................................................ 64-bit Kernel Mode Segments ................................................................................................................ Cacheability and the xkphys Address Space ......................................................................................... VR4102 Physical Address Space............................................................................................................ ROM Addresses (when using 16-bit data bus) ....................................................................................... ROM Addresses (when using 32-bit data bus) ....................................................................................... Internal I/O Space 1................................................................................................................................ Internal I/O Space 2................................................................................................................................ DRAM Addresses (when using 16-bit data bus)..................................................................................... DRAM Addresses (when using 32-bit data bus)..................................................................................... Cache Algorithm ..................................................................................................................................... Mask Values and Page Sizes ................................................................................................................. CP0 Exception Processing Registers ..................................................................................................... Cause Register Exception Code Field.................................................................................................... 64-Bit Mode Exception Vector Base Addresses ..................................................................................... 32-Bit Mode Exception Vector Base Addresses ..................................................................................... Exception Priority Order.......................................................................................................................... BCU Registers ........................................................................................................................................ Address Bit Correspondence between ADD Bus and External Devices ................................................ Address Connection Table with External Devices .................................................................................. Access Size Restrictions for Address Spaces ........................................................................................ Summary of ROM Modes ....................................................................................................................... Example of Bit Inversion in Data in VR4102 and at DATA [15:0] Pins .................................................... 25 LIST OF TABLES (3/4) Table. No. 10-7 10-8 10-9 10-10 10-11 10-12 11-1 12-1 12-2 13-1 14-1 15-1 15-2 15-3 15-4 16-1 17-1 18-1 18-2 18-3 18-4 19-1 19-2 19-3 19-4 19-5 19-6 20-1 21-1 22-1 22-2 Title Page 251 252 254 256 260 263 272 281 281 289 294 319 320 326 327 336 355 361 362 379 380 386 389 396 399 400 407 409 423 435 452 Illegal Access Notification Methods ....................................................................................................... Access Times during Ordinary ROM Read Mode .................................................................................. PageROM Read Mode Access Time ..................................................................................................... System Bus Access Times .................................................................................................................... High-Speed System Bus Access Times ................................................................................................ Access Times for LCD Interface ............................................................................................................ DMAAU Registers .................................................................................................................................. DMA Priority Levels ............................................................................................................................... DCU Registers ....................................................................................................................................... CMU Register ........................................................................................................................................ ICU Registers......................................................................................................................................... Bit Operations during Reset................................................................................................................... Bit Operations during Shutdown ............................................................................................................ Power Mode........................................................................................................................................... PMU Registers....................................................................................................................................... RTC Registers ....................................................................................................................................... DSU Registers ....................................................................................................................................... GPIO Pin Functions ............................................................................................................................... GIU Registers ........................................................................................................................................ Table of Correspondences between GPIO[47..32] and Function Pins .................................................. Table of Correspondence between GPIO[48] and Function Pin............................................................ PIU Registers......................................................................................................................................... PIUCNTREG Bit Manipulation and States ............................................................................................. PIUASCNREG Bit Manipulation and States........................................................................................... Detected Coordinates and Page Buffers ............................................................................................... A/D Ports and Data Buffers.................................................................................................................... Comparison of PIUs of VR4102 and VR4101.......................................................................................... AIU Registers......................................................................................................................................... KIU Registers......................................................................................................................................... DSIU Registers ...................................................................................................................................... Receive Error Causes............................................................................................................................ 26 LIST OF TABLES (4/4) Table. No. 23-1 24-1 24-2 24-3 25-1 25-2 26-1 27-1 27-2 27-3 28-1 28-2 Title Page 453 461 466 468 483 485 498 526 527 528 678 681 LED Registers......................................................................................................................................... SIU Registers.......................................................................................................................................... Correspondence between Baud Rates and Divisors .............................................................................. Interrupt Function ................................................................................................................................... HSP Registers ........................................................................................................................................ Control Register Definitions .................................................................................................................... FIR Registers.......................................................................................................................................... CPU Instruction Operation Notations...................................................................................................... Load and Store Common Functions ....................................................................................................... Access Type Specifications for Loads/Stores ........................................................................................ VR4102 Coprocessor 0 Hazards............................................................................................................. Calculation Example of CP0 Hazard and the Number of Instructions Inserted ...................................... 27 [MEMO] 28 CHAPTER 1 INTRODUCTION This chapter describes the outline of the VR4102 (PD30102), which is a 64-/32-bit RISC microprocessor. 1.1 FEATURES The VR4102, which is a high-performance 64-/32-bit microprocessor employing the RISC (reduced instruction set computer) architecture developed by MIPS, is one of the RISC microprocessor VR-SeriesTM products manufactured by NEC. The VR4102 is ideally suited for battery-driven high-performance portable information equipment. It mainly consists of the high-performance ultra-low-power consumption VR4102 CPU core, and has various peripheral functions including a DMA controller, software modem interface, serial interface, keyboard interface, IrDA interface, touch panel interface, real-time clock, A/D converter, and D/A converter. The external bus width of this device can be selected between 32 bits and 16 bits. This function enables the VR4102 to process voluminous data at high speed. The features of the VR4102 are described below. a Employs 64-bit RISC CPU Core (VR4100 equivalent) a Internal 64-bit processing a Optimized 5-stage pipeline a Conforms to MIPS I, II, III instruction sets (with the FPU, LL, and SC instructions left out) a Supports high-speed product-sum operation instructions to execute applications in high speed a On-chip 4-Kbyte instruction cache and 1-Kbyte data cache a 32-double-entry translation lookaside buffer (TLB) for virtual address management a 32-bit physical address space and 40-bit virtual address space (in 64-bit mode) a On-chip peripheral units suited for portable equipment * Memory controller (supports ROM, EDO-type DRAM, and flash memory) * ISA-bus interface * Keyboard interface * Touch panel interface (on-chip 4-channel A/D converter) * Controller complying with IrDA 1.1 (FIR) * Software modem interface * DMA controller * Serial interface * Debug serial interfaces * Interrupt controller * Audio interface (on-chip digital I/O, A/D and D/A converters) * General-purpose A/D converter: 3 channels * General-purpose ports a Effective power management features, which include the following four operating modes: * Fullspeed mode: normal operating mode in which all clocks operate * Standby mode: all internal clocks stop except for interrupt-related clocks * Suspend mode: bus clock and all internal clocks stop except for interrupt-related clocks * Hibernate mode: all clocks generated by the CPU core stop 29 CHAPTER 1 INTRODUCTION a External input clock: 32.768 kHz, 18.432 MHz (for internal CPU core and peripheral unit operation), 48 MHz a Supports ISA bus subset a Clock supply management function for each on-chip peripheral unit to implement low-power consumption a Operation supply voltage: VDD = 3.0 to 3.6 V 1.2 ORDERING INFORMATION Part Number Package 216-pin plastic LQFP (fine pitch) (24 x 24 mm) 216-pin plastic LQFP (fine pitch) (24 x 24 mm) 224-pin plastic FBGA (16 x 16 mm) 224-pin plastic FBGA (16 x 16 mm) Maximum Operation Frequency 54 MHz 66 MHz 54 MHz 66 MHz (dedicated for FIR IrDA interface) PD30102GM-54-8EV PD30102GM-66-8EV PD30102S1-54-3C PD30102S1-66-3C 1.3 64-BIT ARCHITECTURE The VR4102 microprocessor has a 64-bit architecture. However, it can also run 32-bit applications. 1.4 VR4102 PROCESSOR The VR4102 consists of the VR4100 CPU core and seventeen peripheral units. It can connect external controllers directly. Figure 1-1 is an internal block diagram of the VR4102 processor. Figure 1-1. VR4102 Internal Block Diagram and Example of Connection to External Blocks 32.768kHz 18.432MHz CODEC AFE OSB LCD Module OSB PLL HSP GIU KIU PD16666 PD16661 LCD Panel RTC LED DSU AIU VR4100 CPU core PCMCIA /Buffer PCcard ICU PMU CMU DCU D/A PIU A/D SIU Touch Panel RS-232-C Driver FIR IR Driver ROM/ Flash memory EDO DRAM BCU DMAAU VR4102 48MHz 30 CHAPTER 1 INTRODUCTION 1.4.1 Internal Block Structure The following provides an outline of the peripheral units. For the CPU core, refer to 1.5 VR4100 CPU CORE. (1) Bus Control Unit (BCU) In the VR4102, the bus control unit (BCU) transfers data between the VR4100 CPU core and SysAD bus. It also controls external circuits, such as the LCD controller connected to the system bus, DRAM, ROM (flash memory or masked ROM), and PCMCIA controller, and transfers data between the VR4102 and these external devices, using the address and data buses. (2) Real-time Clock Unit (RTC) The real-time clock (RTC) is provided with an accurate counter that operates on a 32.768-kHz clock pulse supplied from the clock generator. controlling various interrupts. It is also provided with several counters and Compare registers for (3) Deadman's Switch Unit (DSU) The Deadman's switch unit (DSU) is used to check whether the processor is running normally. If the register of this unit is not cleared by software within a specified period, the system is shut down. (4) Interrupt Control Unit (ICU) The interrupt control unit (ICU) controls interrupt requests that are caused by factors either internal or external to the VR4102, and informs the VR4100 CPU core when an interrupt request occurs. (5) Power Management Unit (PMU) The power management unit (PMU) outputs signals necessary to control the power of the entire system including the VR4102. The signals are used to control the PLL of the VR4100 CPU core and the internal clocks (pipeline clock, TClock, and MasterOut) in low-power modes. (6) Direct Memory Access Address Unit (DMAAU) The direct memory access address unit (DMAAU) controls the address of three different DMA transfers. (7) Direct Memory Access Control Unit (DCU) The direct memory access control unit (DCU) controls the arbitration of three different DMA transfers. (8) Clock Mask Unit (CMU) The clock mask unit (CMU) controls the way the clocks TClock and MasterOut are supplied from the VR4100 CPU core to internal peripheral units. (9) General Purpose I/O Unit (GIU) The general purpose I/O unit (GIU) controls 49 GPIO pins. (10) Audio Interface Unit (AIU) The audio interface unit (AIU) executes mic-input sampling and audio signal output by controlling the internal A/D converter and D/A converter. 31 CHAPTER 1 INTRODUCTION (11) Keyboard Interface Unit (KIU) The keyboard interface unit (KIU) has 12 scan lines and 8 detection lines. It can detect when any of 64/80/96 keys are pressed. It supports key rollover for two to three continuous strokes. (12) Touch Panel Interface Unit (PIU) The touch panel interface unit (PIU) detects when the touch panel is touched, by controlling the internal A/D converter. (13) Debug Serial Interface Unit (DSIU) The debug serial interface unit (DSIU) is a serial interface for debugging. It supports a maximum transfer rate of 115 kbps. (14) Serial Interface Unit (SIU) The serial interface unit (SIU) conforms to the RS-232-C specification and is compatible with 16550. It supports a maximum transfer rate of 1.15 Mbps. Also available is an IrDA serial interface supporting a maximum transfer rate of 115 kbps, but this interface and the RS-232-C interface are mutually exclusive. (15) Fast IrDA Interface Unit (FIR) The FIR unit is a unit for performing 0.5- to 4-Mbps IrDA communication. This unit operates based on a dedicated 48-MHz clock input. (16) Host Signal Processing Unit (HSP) The HSP unit is used to realize a software modem. It interfaces the CPU core with an external codec device, and controls them. (17) Light Emitting Diode Unit (LED) The LED unit is used to control the lighting of external LED. 32 CHAPTER 1 INTRODUCTION 1.4.2 I/O Registers The I/O registers are used for peripheral unit control. Table 1-1. BCU Registers Register symbols BCUCNTREG 1 BCUCNTREG 2 BCUSPEEDREG BCUERRSTREG BCURFCNTREG REVIDREG BCURFCOUNTREG CLKSPEEDREG BCU Control Register 1 BCU Control Register 2 BCU Access Cycle Change Register BCU BUS ERROR Status Register BCU Refresh Control Register Peripheral Unit Revision ID Register BCU Refresh Cycle Count Register Clock Setting Register Function Address 0x0B00 0000 0x0B00 0002 0x0B00 000A 0x0B00 000C 0x0B00 000E 0x0B00 0010 0x0B00 0012 0x0B00 0014 Table 1-2. DMAAU Registers Register symbols AIUIBALREG AIUIBAHREG AIUIALREG AIUIAHREG AIUOBALREG AIUOBAHREG AIUOALREG AIUOAHREG FIRBALREG FIRBAHREG FIRALREG FIRAHREG Function AIU IN DMA Base Address Register Low AIU IN DMA Base Address Register High AIU IN DMA Address Register Low AIU IN DMA Address Register High AIU OUT DMA Base Address Register Low AIU OUT DMA Base Address Register High AIU OUT DMA Address Register Low AIU OUT DMA Address Register High FIR DMA Base Address Register Low FIR DMA Base Address Register High FIR DMA Address Register Low FIR DMA Address Register High Address 0x0B00 0020 0x0B00 0022 0x0B00 0024 0x0B00 0026 0x0B00 0028 0x0B00 002A 0x0B00 002C 0x0B00 002E 0x0B00 0030 0x0B00 0032 0x0B00 0034 0x0B00 0036 33 CHAPTER 1 INTRODUCTION Table 1-3. DCU Registers Register symbols DMARSTREG DMAIDLEREG DMASENREG DMAMSKREG DMAREQREG TDREG DMA Reset Register DMA Sequencer Status Register DMA Sequencer Enable Register DMA Mask Register DMA Request Register Transfer Direction Setting Register Function Address 0x0B00 0040 0x0B00 0042 0x0B00 0044 0x0B00 0046 0x0B00 0048 0x0B00 004A Table 1-4. CMU Register Register symbol CMUCLKMSK CMU Clock Mask Register Function Address 0x0B00 0060 34 CHAPTER 1 INTRODUCTION Table 1-5. ICU Registers Register symbols SYSINT1REG PIUINTREG AIUINTREG KIUINTREG GIUINTLREG DSIUINTREG MSYSINT1REG MPIUINTREG MAIUINTREG MKIUINTREG MGIUINTLREG MDSIUINTREG NMIREG SOFTINTREG SYSINT2REG GIUINTHREG FIRINTREG MSYSINT2REG MGIUINTHREG MFIRINTREG Function Level 1 System Interrupt Register 1 Level 2 PIU Interrupt Register Level 2 AIU Interrupt Register Level 2 KIU Interrupt Register Level 2 GIU Interrupt Register Low Level 2 DSIU Interrupt Register Level 1 Mask System Interrupt Register 1 Level 2 Mask PIU Interrupt Register Level 2 Mask AIU Interrupt Register Level 2 Mask KIU Interrupt Register Level 2 Mask GIU Interrupt Register Low Level 2 Mask DSIU Interrupt Register Battery Interrupt Select Register Software Interrupt Register Level 1 System Interrupt Register 2 Level 2 GIU Interrupt Register High Level 2 FIR Interrupt Register Level 1 Mask System Interrupt Register 2 Level 2 Mask GIU Interrupt Register High Level 2 Mask FIR Interrupt Register Address 0x0B00 0080 0x0B00 0082 0x0B00 0084 0x0B00 0086 0x0B00 0088 0x0B00 008A 0x0B00 008C 0x0B00 008E 0x0B00 0090 0x0B00 0092 0x0B00 0094 0x0B00 0096 0x0B00 0098 0x0B00 009A 0x0B00 0200 0x0B00 0202 0x0B00 0204 0x0B00 0206 0x0B00 0208 0x0B00 020A Table 1-6. PMU Registers Register symbols PMUINTREG PMUCNTREG PMUINT2REG PMUCNT2REG Function PMU Interrupt/Status Register PMU Control Register PMU Interrupt Register 2 PMU Control Register 2 Address 0x0B00 00A0 0x0B00 00A2 0x0B00 00A4 0x0B00 00A6 35 CHAPTER 1 INTRODUCTION Table 1-7. RTC Registers Register symbols ETIMELREG ETIMEMREG ETIMEHREG ECMPLREG ECMPMREG ECMPHREG RTCL1LREG RTCL1HREG RTCL1CNTLREG RTCL1CNTHREG RTCL2LREG RTCL2HREG RTCL2CNTLREG RTCL2CNTHREG TCLKLREG TCLKHREG TCLKCNTLREG TCLKCNTHREG RTCINTREG Elapsed Time L Register Elapsed Time M Register Elapsed Time H Register Elapsed Compare L Register Elapsed Compare M Register Elapsed Compare H Register RTC Long 1 L Register RTC Long 1 H Register RTC Long 1 Count L Register RTC Long 1 Count H Register RTC Long 2 L Register RTC Long 2 H Register RTC Long 2 Count L Register RTC Long 2 Count H Register TClock L Register TClock H Register TClock Count L Register TClock Count H Register RTC Interrupt Register Function Address 0x0B00 00C0 0x0B00 00C2 0x0B00 00C4 0x0B00 00C8 0x0B00 00CA 0X0B00 00CC 0x0B00 00D0 0x0B00 00D2 0x0B00 00D4 0x0B00 00D6 0x0B00 00D8 0x0B00 00DA 0x0B00 00DC 0x0B00 00DE 0x0B00 01C0 0x0B00 01C2 0x0B00 01C4 0x0B00 01C6 0x0B00 01DE 36 CHAPTER 1 INTRODUCTION Table 1-8. DSU Registers Register symbols DSUCNTREG DSUSETREG DSUCLRREG DSUTIMREG DSU Control Register DSU Cycle (Dead Time) Set Register DSU Clear Register DSU Elapsed Time Register Function Address 0x0B00 00E0 0x0B00 00E2 0x0B00 00E4 0x0B00 00E6 Table 1-9. GIU Registers Register symbols GIUIOSELL GIUIOSELH GIUPIODL GIUPIODH GIUINTSTATL GIUINTSTATH GIUINTENL GIUINTENH GIUINTTYPL GIUINTTYPH GIUINTALSELL GIUINTALSELH GIUINTHTSELL GIUINTHTSELH GIUPODATL GIUPODATH Function GPIO Input/Output Select Register L GPIO Input/Output Select Register H GPIO Port Input/Output Data Register L GPIO Port Input/Output Data Register H GPIO Interrupt Status Register L GPIO Interrupt Status Register H GPIO Interrupt Enable Register L GPIO Interrupt Enable Register H GPIO Interrupt Type (Edge or Level) Select Register L GPIO Interrupt Type (Edge or Level) Select Register H GPIO Interrupt Active Level Select Register L GPIO Interrupt Active Level Select Register H GPIO Interrupt Hold/Through Select Register L GPIO Interrupt Hold/Through Select Register H GPIO Port Output Data Register L GPIO Port Output Data Register H Address 0x0B00 0100 0x0B00 0102 0x0B00 0104 0x0B00 0106 0x0B00 0108 0x0B00 010A 0x0B00 010C 0x0B00 010E 0x0B00 0110 0x0B00 0112 0x0B00 0114 0x0B00 0116 0x0B00 0118 0x0B00 011A 0x0B00 011C 0x0B00 011E 37 CHAPTER 1 INTRODUCTION Table 1-10. PIU Registers Register symbols PIUCNTREG PIUINTREG PIUSIVLREG PIUSTBLREG PIUCMDREG PIUASCNREG PIUAMSKREG PIUCIVLREG PIUPB00REG PIUPB01REG PIUPB02REG PIUPB03REG PIUPB10REG PIUPB11REG PIUPB12REG PIUPB13REG PIUAB0REG PIUAB1REG PIUAB2REG PIUAB3REG PIUPB04REG PIUPB14REG PIU Control Register PIU Interrupt Cause Register PIU Data Sampling Interval Register PIU A/D Converter Start Delay Register PIU A/D Command Register PIU A/D Port Scan Register PIU A/D Scan Mask Register PIU Check Interval Register PIU Page 0 Buffer 0 Register PIU Page 0 Buffer 1 Register PIU Page 0 Buffer 2 Register PIU Page 0 Buffer 3 Register PIU Page 1 Buffer 0 Register PIU Page 1 Buffer 1 Register PIU Page 1 Buffer 2 Register PIU Page 1 Buffer 3 Register PIU AD Scan Buffer 0 Register PIU AD Scan Buffer 1 Register PIU AD Scan Buffer 2 Register PIU AD Scan Buffer 3 Register PIU Page 0 Buffer 4 Register PIU Page 1 Buffer 4 Register Function Address 0x0B00 0122 0x0B00 0124 0x0B00 0126 0x0B00 0128 0x0B00 012A 0x0B00 0130 0x0B00 0132 0x0B00 013E 0x0B00 02A0 0x0B00 02A2 0x0B00 02A4 0x0B00 02A6 0x0B00 02A8 0x0B00 02AA 0x0B00 02AC 0x0B00 02AE 0x0B00 02B0 0x0B00 02B2 0x0B00 02B4 0x0B00 02B6 0x0B00 02BC 0x0B00 02BE 38 CHAPTER 1 INTRODUCTION Table 1-11. AIU Registers Register symbols MDMADATREG SDMADATREG SODATREG SCNTREG SCNVRREG MIDATREG MCNTREG MCNVRREG DVALIDREG SEQREG INTREG Mike DMA Data Register Speaker DMA Data Register Speaker Output Data Register Speaker Output Control Register Speaker Conversion Rate Register Mike Input Data Register Mike Input Control Register Mike Conversion Rate Register Data Valid Register Sequential Operation Enable Register AIU Interrupt Register Function Address 0x0B00 0160 0x0B00 0162 0x0B00 0166 0x0B00 0168 0x0B00 016A 0x0B00 0170 0x0B00 0172 0x0B00 0174 0x0B00 0178 0x0B00 017A 0x0B00 017C 39 CHAPTER 1 INTRODUCTION Table 1-12. KIU Registers Register symbols KIUDAT0 KIUDAT1 KIUDAT2 KIUDAT3 KIUDAT4 KIUDAT5 KIUSCANREP KIUSCANS KIUWKS KIUWKI KIUINT KIURST KIUGPEN SCANLINE KIU Data0 Register KIU Data1 Register KIU Data2 Register KIU Data3 Register KIU Data4 Register KIU Data5 Register KIU Scan/Repeat Register KIU Scan Status Register KIU Wait Keyscan Stable Register KIU Wait Keyscan Interval Register KIU Interrupt Register KIU Reset Register KIU General Purpose Output Enable Register KIU Scan Line Register Function Address 0x0B00 0180 0x0B00 0182 0x0B00 0184 0x0B00 0186 0x0B00 0188 0x0B00 018A 0x0B00 0190 0x0B00 0192 0x0B00 0194 0x0B00 0196 0x0B00 0198 0x0B00 019A 0x0B00 019C 0x0B00 019E Table 1-13. DSIU Registers Register symbols PORTREG MODEMREG ASIM00REG ASIM01REG RXB0RREG RXB0LREG TXS0RREG TXS0LREG ASIS0REG INTR0REG BPRM0REG DSIURESETREG Port Change Register Modem Control Register Asynchronous Mode 0 Register Asynchronous Mode 1 Register Receive Buffer Register (Extended) Receive Buffer Register Transmit Data Register (Extended) Transmit Data Register Status Register Debug SIU Interrupt Register Baud-rate Generator Prescaler Mode Register Debug SIU Reset Register Function Address 0x0B00 01A0 0x0B00 01A2 0x0B00 01A4 0x0B00 01A6 0x0B00 01A8 0x0B00 01AA 0x0B00 01AC 0x0B00 01AE 0x0B00 01B0 0x0B00 01B2 0x0B00 01B6 0x0B00 01B8 40 CHAPTER 1 INTRODUCTION Table 1-14. LED Registers Register symbols LEDHTSREG LEDLTSREG LEDCNTREG LEDASTCREG LEDINTREG LED H Time Set Register LED L Time Set Register LED Control Register LED Auto Stop Time Count Register LED Interrupt Register Function Address 0x0B00 0240 0x0B00 0242 0x0B00 0248 0x0B00 024A 0x0B00 024C Table 1-15. SIU Registers Register symbols SIURB SIUTH SIUDLL SIUIE SIUDLM SIUIID SIUFC SIULC SIUMC SIULS SIUMS SIUSC SIUIRSEL Function Receiver Buffer Register (Read) Transmitter Holding Register (Write) Divisor Latch (Least Significant Byte) Register Interrupt Enable Register Divisor Latch (Most Significant Byte) Register Interrupt Identification Register (Read) FIFO Control Register (Write) Line Control Register MODEM Control Register Line Status Register MODEM Status Register Scratch Register SIU/FIR IrDA Selector 0x0C00 0003 0x0C00 0004 0x0C00 0005 0x0C00 0006 0x0C00 0007 0x0C00 0008 1 0 1 0x0C00 0002 0x0C00 0001 LCR[7] 0 Address 0x0C00 0000 Remark LCR[7] is bit 7 of the SIULC register. Table 1-16. HSP Registers Register symbols HSPINIT HSPDATA[7:0] HSPDATA[15:8] HSPINDEX HSPID[7:0] HSPPCS[7:0] HSPPCTEL[7:0] HSP Initialize Register HSP Data Register [7:0] HSP Data Register [15:8] HSP Index Register HSP ID Register Function Address 0x0C00 0020 0x0C00 0022 0x0C00 0023 0x0C00 0024 0x0C00 0028 0x0C00 0029 0x0C00 0029 HSP I/O Address Program Confirmation Register HSP Signature Checking Port 41 CHAPTER 1 INTRODUCTION Table 1-17. FIR Registers Register symbols FRSTR DPINTR DPCNTR TDR RDR IMR FSR IRSR1 CRCSR FIRCR MIRCR DMACR DMAER TXIR RXIR IFR RXSTS TXFL MRXF RXFL FIR Reset Register DMA Page Interrupt Register DMA Page Control Register Transmit Data Register Receive Data Register Interrupt Mask Register FIFO Setup Register IR Setup Register 1 CRC Setup Register FIR Control Register MIR Control Register DMA Control Register DMA Enable Register Transmission Indicate Register Reception Indicate Register Interrupt Flag Register Reception Status Register Transmit Frame Length Register Maximum Receive Frame Length Register Receive Frame Length Register Function Address 0x0C00 0040 0x0C00 0042 0x0C00 0044 0x0C00 0050 0x0C00 0052 0x0C00 0054 0x0C00 0056 0x0C00 0058 0x0C00 005C 0x0C00 005E 0x0C00 0060 0x0C00 0062 0x0C00 0064 0x0C00 0066 0x0C00 0068 0x0C00 006A 0x0C00 006C 0x0C00 006E 0x0C00 0070 0x0C00 0074 42 CHAPTER 1 INTRODUCTION 1.5 VR4100 CPU CORE Figure 1-2. VR4100 CPU Core Internal Block Diagram VA bus ID bus VR4100 CPU core Control(o) Control(i) Address/Data(o) Address/Data(i) Bus Interface Data Cache (1K bytes) Instruction Cache (4K bytes) CP0 CPU TLB Clock Generator Internal Clock 1.5.1 VR4100 CPU Core (1) CPU bus interface The CPU bus interface controls data transmission/reception between the VR4100 CPU core and the BCU, which is one of peripheral units. The VR4100 CPU interface consists of two 32-bit multiplexed address/data buses (one is for input, and another is for output), clock signals, and control signals such as interrupts. (2) Clock generator The following clock inputs are oscillated and supplied to internal units. x 32.768-kHz clock for RTC unit: oscillating a 32.768-kHz crystal resonator input via an internal oscillator to supply to the RTC unit. x 8.432-MHz clock for serial interface and the VR4102's reference operating clock: oscillating an 18.432-MHz crystal resonator input via an internal oscillator, and then multiplying it by phaselocked loop (PLL) to generate a pipeline clock (PClock). The internal bus clock (TClock) is generated from PClock and supplied to peripheral units. (3) Instruction cache The instruction cache employs direct mapping, virtual index, and physical tag. Its capacity is 4K bytes. (4) CPU CPU has hardware resources to process an integer instruction. They are the 64-bit register file, 64-bit integer data bus, and multiply-and-accumulate operation unit. 43 CHAPTER 1 INTRODUCTION (5) Coprocessor 0 (CP0) CP0 incorporates a memory management unit (MMU) and exception handling function. MMU checks whether there is an access between different memory segments (user, supervisor, and kernel) by executing address conversion. The translation lookaside buffer (TLB) converts virtual addresses to physical addresses. (6) Data cache The data cache employs direct mapping, virtual index, physical tag, and write back. Its capacity is 1K bytes. 44 CHAPTER 1 INTRODUCTION 1.5.2 CPU Registers The VR4100 CPU core has thirty two 64-bit general-purpose registers (GPRs). In addition, the processor provides the following special, registers: -- 64-bit Program Counter (PC) -- 64-bit HI register, containing the integer multiply and divide upper doubleword result -- 64-bit LO register, containing the integer multiply and divide lower doubleword result Two of the general-purpose registers have assigned the following functions: -- r0 is hardwired to a value of zero, and can be used as the target register for any instruction whose result is to be discarded. r0 can also be used as a source when a zero value is needed. -- r31 is the link register used by link instruction, such as JAL/JALR instructions. This register can be used for other instructions. However, be careful that use of the register by a link instruction will not coincide with use of the register for other operations. The register group is provided within the CP0, to process exceptions and to manage addresses. CPU registers can operate as either 32-bit or 64-bit registers, depending on the VR4102 processor mode of operation. Figure 1-3 shows the CPU registers. Figure 1-3. VR4102 CPU Registers General-purpose register 63 32 31 r0 = 0 r1 r2 r29 r30 r31 = LinkAddress 63 63 0 63 Multiply/divide register 32 31 HI 32 31 LO 0 0 Program Counter 32 31 PC 0 The VR4102 has no Program Status Word (PSW) register as such; this is covered by the Status and Cause registers incorporated within the System Control Coprocessor (CP0). The CP0 registers are used for exception handling or address management. The overview of these registers is described in 1.5.5 Coprocessors (CP0-CP3). 45 CHAPTER 1 INTRODUCTION 1.5.3 CPU Instruction Set Overview Each CPU instruction is 32 bits long. As shown in Figure 1-4, there are three instruction formats: -- immediate (I-type) -- jump (J-type) -- register (R-type) Figure 1-4. CPU Instruction Formats 31 I-type (immediate) 31 J-type (jump) 31 R-type (register) op op op 26 25 rs 26 25 21 20 rt 16 15 immediate 0 0 target 26 25 rs 21 20 rt 16 15 rd 11 10 sa 65 funct 0 The instruction set can be further divided into the following five groupings: (1) Load and store instructions move data between memory and general-purpose registers. signed immediate offset. (2) Computational instructions perform arithmetic, logical, shift, multiply, and divide operations on values in registers. They include R-type (in which both the operands and the result are stored in registers) and I-type (in which one operand is a 16-bit signed immediate value) formats. (3) Jump and branch instructions change the control flow of a program. Jumps are always made to an absolute address formed by combining a 26-bit target address with the high-order bits of the Program Counter (J-type format) or register address (R-type format). The format of the branch instructions is I type. Branches have 16-bit offsets relative to the Program Counter. JAL instructions save their return address in register 31. (4) Coprocessor 0 (System Control Coprocessor, CP0) instructions perform operations on CP0 registers to control the memory-management and exception-handling facilities of the processor. (5) Special instructions perform system calls and breakpoint operations, or cause a branch to the general exception-handling vector based upon the result of a comparison. These instructions occur in both R-type (both the operands and the result are stored in registers) and I-type (one operand is a 16-bit signed immediate value) formats. Chapter 3 provides a more detailed summary (Refer to Chapter 27 for detailed descriptions of the operation of each instruction) . They are all immediate (I-type) instructions, since the only addressing mode supported is base register plus 16-bit, 46 CHAPTER 1 INTRODUCTION 1.5.4 Data Formats and Addressing The VR4102 uses following four data formats: Doubleword (64 bits) Word (32 bits) Halfword (16 bits) Byte (8 bits) For the VR4100 CPU core, byte ordering within all of the larger data formats - halfword, word, doubleword - can be configured in either big-endian or little-endian order. However, the VR4102 supports the little-endian order only. Endianness refers to the location of byte 0 within the multi-byte data structure. Figure 1-5 shows the ordering of bytes within words and the ordering of words within doubleword structures for the little-endian conventions. When configured as a little-endian system, byte 0 is always the least-significant (rightmost) byte, which is compatible with iAPXTM and DEC VAXTM conventions. Figure 1-5 shows this configuration. Figure 1-5. Little-Endian Byte Ordering in Word Data Higher address Word address 12 8 4 Bit No. 31 15 11 7 3 24 23 14 10 6 2 16 15 13 9 5 1 87 12 8 4 0 0 Lower address 0 Remarks 1. The lowest byte is the lowest address. 2. The address of word data is specified by the lowest byte's address. In this manual, bit 0 is always the least-significant (rightmost) bit; thus, bit designations are always little-endian. Figure 1-6 shows little-endian byte ordering in doublewords. 47 CHAPTER 1 INTRODUCTION Figure 1-6. Little-Endian Byte Ordering in Double Word Data Higher address Double word address 63 16 8 23 15 7 Word Half word 32 31 16 15 18 10 2 17 9 1 Byte 87 16 8 0 0 22 14 6 21 13 5 20 12 4 19 11 3 Lower address 0 Remarks 1. The lowest byte is the lowest address. 2. The address of word data is specified by the lowest byte's address. The CPU uses following byte boundaries for halfword, word, and doubleword accesses: -- Halfword: An even byte boundary (0, 2, 4...) -- Word: A byte boundary divisible by four (0, 4, 8...) -- Doubleword: A byte boundary divisible by eight (0, 8, 16...) The following special instructions to load and store data that are not aligned on 4-byte (word) or 8-byte (doubleword) boundaries: LWL LDL LWR LDR SWL SDL SWR SDR These instructions are used in pairs to provide an access to misaligned data. Accessing misaligned data incurs one additional instruction cycle over that required for accessing aligned data. Figure 1-7 shows the access of a misaligned word that has byte address 3 for the little-endian conventions. Figure 1-7. Misaligned Word Accessing (Little-Endian) Higher address 31 24 23 6 3 Lower address Bit No. 16 15 5 87 4 0 48 CHAPTER 1 INTRODUCTION 1.5.5 Coprocessors (CP0-CP3) MIPS ISA defines 4 types of coprocessors (CP0 to CP3). CP1 is reserved to execute a floating-point instruction. CP2 and CP3 are reserved for future use. CP0 is an onchip system control coprocessor, which supports the virtual memory system and exception handling. The virtual memory system is implemented using an on-chip TLB and the CP0 registers in the CPU. CP0 translates virtual addresses to physical addresses, switches the operating mode, (kernel, supervisor, or user mode), and management exceptions. It also controls the cache subsystem to analyze a cause and to return from the error state. Figure 1-8 shows the definitions of the CP0 register, and Table 1-18 shows simple descriptions of each register. For the detailed descriptions of the registers related to the virtual system memory, refer to Chapter 5. For the detailed descriptions of the registers related to exception handling, refer to Chapter 6. Figure 1-8. CP0 Registers Register No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Register name Index* Random* EntryLo0* EntryLo1* Context** PageMask* Wired* - BadVAddr** Count** EntryHi* Compare** Status** Cause** EPC** PRId* Register No. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Register name Config* LLAddr* WatchLo** WatchHi** XContext** - - - - - PErr** CacheErr** TagLo* TagHi* ErrorEPC** - * for Memory management ** for Exception handling - Reserved 49 CHAPTER 1 INTRODUCTION Table 1-18. System Control Coprocessor (CP0) Register Definitions Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 to 25 26 27 28 29 30 31 Register Index Random EntryLo0 EntryLo1 Context PageMask Wired BadVAddr Count EntryHi Compare Status Cause EPC PRId Config LLAddr WatchLo WatchHi XContext PErr CacheErr TagLo TagHi ErrorEPC Description Programmable pointer to TLB array Pseudo-random pointer to TLB array (read only) Low half of TLB entry for even VPN Low half of TLB entry for odd VPN Pointer to kernel virtual PTE in 32-bit mode TLB page mask Number of wired TLB entries Reserved for future use Virtual address where the most recent error occurred Timer count High half of TLB entry (including ASID) Timer compare Status register Cause of last exception Exception Program Counter Processor revision identifier Configuration register (specifying memory mode system) Reserved Memory reference trap address low bits Memory reference trap address high bits Pointer to kernel virtual PTE in 64-bit mode Reserved for future use Cache parity bits Index and status of cache error Cache Tag register (low) Cache Tag register (high) Error Exception Program Counter Reserved for future use 50 CHAPTER 1 INTRODUCTION 1.5.6 Floating-Point Unit (FPU) The VR4102 does not support the floating-point unit (FPU). Coprocessor Unusable exception will occur if any FPU instructions are executed. If necessary, FPU instructions should be emulated by software in an exception handler. 1.5.7 Cache The VR4102 chip incorporates instruction and data caches, which are independent of each other. This configuration enables high-performance pipeline operations. Both caches have a 64-bit data bus, enabling a oneclock access. These buses can be accessed in parallel. The instruction cache of the VR4102 has a storage capacity of 4 KB, while the data cache has a capacity of 1 KB. A detailed description of caches is given in CHAPETE 8 CACHE ORGANIZATION AND OPERATION. 51 CHAPTER 1 INTRODUCTION 1.6 CPU CORE MEMORY MANAGEMENT SYSTEM (MMU) The VR4102 has a 32-bit physical addressing range of 4 Gbytes. However, since it is rare for systems to implement a physical memory space as large as that memory space, the CPU provides a logical expansion of memory space by translating addresses composed in the large virtual address space into available physical memory addresses. The VR4102 supports the following two addressing modes: 32-bit mode, in which the virtual address space is divided into 2 Gbytes for user process and 2 Gbytes for the kernel. 64-bit mode, in which the virtual address is expanded to1 Tbyte (2 bytes) of user virtual address space. 40 A detailed description of these address spaces is given in Chapter 4. 1.6.1 Translation Lookaside Buffer (TLB) The TLB converts virtual addresses to physical addresses. It runs by a full-associative method. It has 32 entries, each mapping a pair of pages having a variable size (1 KB to 256 KB). (1) Joint TLB (JTLB) For fast virtual-to-physical address decoding, the VR4102 uses a large, fully associative TLB (joint TLB) that translates 64 virtual pages to their corresponding physical addresses. The TLB is organized as 32 pairs of even-odd entries, and maps a virtual address and address space identifier (ASID) into the 4-Gbyte physical address space. The page size can be configured, on a per-entry basis, to map a page size of 1 KB to 256 KB. A CP0 register stores the size of the page to be mapped, and that size is entered into the TLB when a new entry is written. Thus, operating systems can provide special purpose maps; for example, a typical frame buffer can be memory-mapped using only one TLB entry. Translating a virtual address to a physical address begins by comparing the virtual address from the processor with the physical addresses in the TLB; there is a match when the virtual page number (VPN) of the address is the same as the VPN field of the entry, and either the Global (G) bit of the TLB entry is set, or the ASID field of the virtual address is the same as the ASID field of the TLB entry. This match is referred to as a TLB hit. If there is no match, a TLB Miss exception is taken by the processor and software is allowed to refill the TLB from a page table of virtual/physical addresses in memory. 1.6.2 Operating Modes The VR4102 has three operating modes: -- User mode -- Supervisor mode -- Kernel mode The manner in which memory addresses are translated or mapped depends on these operating modes. Refer to CHAPTER 5 MEMORY MANAGEMENT SYSTEM for details. 52 CHAPTER 1 INTRODUCTION 1.7 INSTRUCTION PIPELINE The VR4102 has a 5-stage instruction pipeline. Under normal circumstances, one instruction is issued each cycle. A detailed description of pipeline is provided in Chapter 4. 1.8 CLOCK INTERFACE The VR4102 has the following nine clocks. -- CLKX1, CLKX2 (input) These are oscillation inputs of 18.432 MHz, and used to generate operation clocks for the CPU core and serial interface. -- RTCX1, RTCX2 (input) These are oscillation inputs of 32.768 kHz, and used for PMU and RTC. -- FIRCLK (input) This is a 48-MHz clock input, and used for FIR. -- PClock (internal) This clock is used to control the pipeline used in the VR4100 CPU core, and for units relating to the pipeline. This clock is generated from the clock input of CLKX1 and CLKX2 pins. Its frequency is determined by CLKSEL[2..0] pins. -- MasterOut (internal) This is a bus clock of the VR4100 CPU core, and used for interrupt control. Its frequency is 1/4 of PClock frequency. -- TClock (internal) This is an operation clock for VR4100 CPU core bus, internal bus of the VR4102, and on-chip peripheral unit. In the current VR4102, its frequency is 1/2 of PClock frequency. -- BUSCLK (output) This clock is supplied to the controller on the system bus. Its frequency in determined by CLKSEL[2..0] pins. -- HSPMCLK (output) This clock is supplied to the external CODEC. Its frequency is determined by the HSPMCLKD register. -- HSPSCLK (input) This is an operation clock for the external CODEC and the modem interface. Figure 1-9 shows an external circuit of the clock oscillator. 53 CHAPTER 1 INTRODUCTION Figure 1-9. External Circuit of Clock Oscillator (a) Crystal oscillation VR4102 GND Note1 External clock (b) External clock VR4102 Note1 Open Note2 Note2 Notes 1. CLKX1, RTCX1 2. CLKX2, RTCX2 Cautions 1. When using a clock oscillator, run wires in the area of this figure shown by broken lines, according to the following rules, to avoid effects such as stray capacitance: * Minimize the wire. * Never cause the wires to cross other signal lines or run near a line carrying a large varying current. * Cause the grounding point of the capacitor of the oscillator circuit to have the same potential as GND. Never connect the capacitor to a ground pattern carrying a large current. * Never extract a signal from the oscillator. 2. Take it into consideration that no load such as wiring capacity is applied to the CLKX2 or RTCX2 pin when inputting an external clock. Figure 1-10 shows examples of oscillator having bad connection. 54 CHAPTER 1 INTRODUCTION Figure 1-10. Examples of Oscillator with Bad Connection (a) Connection circuit wiring is too long. (b) There is another signal line crossing. Note1 Note2 GND Note1 Note2 GND (c) A high varying current flows near a signal line. (d) A current flows over the ground line of the generator circuit (The potentials of points A, B, and C change). VDD Note1 Large current Note2 GND Note1 Note2 GND A B C (e) A signal is extracted. Notes 1. CLKX2, RTCX2 2. CLKX1, RTCX1 Note2 Note1 GND 55 [MEMO] 56 CHAPTER 2 PIN FUNCTIONS 2.1 PIN CONFIGURATION x 216-pin plastic LQFP (fine-pitch) (24 u 24 mm) (Top View) PPD30102GM-54-8EV GND IOW# IOR# SHB# BUSCLK LEDOUT# FIRCLK GND HLDACK# HLDRQ IOCHRDY IOCS16# MEMCS16# ZWS# MEMW# MEMR# ADD25 ADD24 ADD23 ADD22 VDD GND ADD21 ADD20 ADD19 ADD18 ADD17 ADD16 ADD15 ADD14 ADD13 ADD12 ADD8 VDD GND ADD7 ADD6 ADD5 ADD4 VDD GND RxD CTS# DCD#/GPIO15 DSR# DTR#/CLKSEL0 RTS#/CLKSEL1 TxD/CLKSEL2 IRDIN FIRDIN#/SEL IRDOUT# IRING BATTINH/BATTINT# VDD VDD DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 GND VDD GND VDD DATA16/GPIO16 DATA17/GPIO17 DATA18/GPIO18 DATA19/GPIO19 DATA20/GPIO20 DATA21/GPIO21 DATA22/GPIO22 DATA23/GPIO23 DATA24/GPIO24 DATA25/GPIO25 DATA26/GPIO26 DATA27/GPIO27 DATA28/GPIO28 DATA29/GPIO29 DATA30/GPIO30 DATA31/GPIO31 GND VDD GND VDD ADD11 ADD10 ADD9 ADD3 ADD2 ADD1 ADD0 POWER POWERON MPOWER RTCRST# RSTSW# GND VDD AGND PIUGND TPX0 TPX1 TPY0 TPY1 PIUVDD ADIN0 ADIN1 ADIN2 AUDIOIN AVDD DGND AUDIOOUT DVDD LCAS# UCAS# MRAS3#/UUCAS# MRAS2#/ULCAS# MRAS1# MRAS0# ROMCS3# ROMCS2# ROMCS1# ROMCS0# RSTOUT RD# GND VDD WR# LCDRDY LCDCS# GPIO49 DBUS32/GPIO48 DCTS#/GPIO47 DRTS#/GPIO46 DDIN/GPIO45 DDOUT/GPIO44 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GND 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 GND ILCSENSE OFFHOOK MUTE AFERST# SDI FS SDO HSPSCLK TELCON HC0 HSPMCLK OPD# KPORT0 KPORT1 KPORT2 KPORT3 KPORT4 KPORT5 KPORT6 KPORT7 VDD GND VDD GND KSCAN11/GPIO43 KSCAN10/GPIO42 KSCAN9/GPIO41 KSCAN8/GPIO40 KSCAN7/GPIO39 KSCAN6/GPIO38 KSCAN5/GPIO37 KSCAN4/GPIO36 KSCAN3/GPIO35 KSCAN2/GPIO34 KSCAN1/GPIO33 KSCAN0/GPIO32 IC (Open) GND GND GND VDD VDD GND VDDP GNDP CVDD CLKX1 CLKX2 RTCX2 RTCX1 CGND GPIO0 VDD Remark # indicates actrive low. 57 CHAPTER 2 PIN FUNCTIONS x 224-pin plastic FGBA (16 u 16 mm) PPD30102S1-54-3C Bottom View Top View 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 V U T R P N ML K J H G F E D C B A A B C D E F G H J KL M N P R T U V Index mark 58 CHAPTER 2 PIN FUNCTIONS Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 Pin Name VDD SHB# BUSCLK HLDACK# IOCHRDY MEMW# ADD23 VDD ADD18 ADD15 ADD8 ADD7 VDD DCD#/GPIO15 TxD/CLKSEL2 IRDOUT# IRING VDD DATA1 IOR# IOW# LEDOUT# FIRCLK HLDRQ# ZWS# ADD24 ADD21 ADD12 ADD6 GND DSR# IRDIN FIRDIN#/SEL BATTINH/BATTINT# OFFHOOK MUTE DATA2 DATA0 GND GND GND IOCS16# MEMR# ADD22 ADD20 ADD17 ADD13 ADD5 RxD DTR#/CLKSEL0 Pin No. C15 C16 C17 C18 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 E1 E2 E3 E4 E15 E16 E17 E18 F1 F2 F3 F4 F15 F16 F17 F18 G1 G2 G3 G4 G15 G16 G17 G18 H1 H2 H3 H4 Pin Name RTS#/CLKSEL1 GND ILCSENSE AFERST# DATA5 DATA3 DATA6 GND MEMCS16# ADD25 GND ADD19 ADD16 ADD14 VDD GND ADD4 CTS# GND GND SDI SDO DATA9 DATA4 DATA7 DATA10 OPD# HSPSCLK FS HC0 DATA13 DATA8 DATA11 DATA14 KPORT3 HSPMCLK TELCON KPORT1 VDD DATA12 DATA15 GND KPORT7 KPORT2 KPORT0 KPORT5 DATA16/GPIO16 GND DATA18/GPIO18 VDD Pin No. H15 H16 H17 H18 J1 J2 J3 J4 J15 J16 J17 J18 K1 K2 K3 K4 K15 K16 K17 K18 L1 L2 L3 L4 L15 L16 L17 L18 M1 M2 M3 M4 M15 M16 M17 M18 N1 N2 N3 N4 N15 N16 N17 N18 P1 P2 P3 P4 P15 P16 Pin Name GND KPORT6 KPORT4 VDD DATA20/GPIO20 DATA17/GPIO17 DATA22/GPIO22 DATA19/GPIO19 KSCAN9/GPIO41 VDD GND KSCAN11/GPIO43 DATA23/GPIO23 DATA26/GPIO26 DATA25/GPIO25 DATA21/GPIO21 KSCAN7/GPIO39 KSCAN10/GPIO42 KSCAN5/GPIO37 KSCAN8/GPIO40 DATA27/GPIO27 DATA31/GPIO31 DATA29/GPIO29 DATA24/GPIO24 KSCAN3/GPIO35 KSCAN6/GPIO38 KSCAN0/GPIO32 KSCAN4/GPIO36 DATA30/GPIO30 VDD GND DATA28/GPIO28 KSCAN2/GPIO34 IC (Open) GND KSCAN1/GPIO33 VDD ADD3 ADD10 GND GND VDD VDDP GND ADD9 ADD0 ADD2 ADD11 VDD GNDP 59 CHAPTER 2 PIN FUNCTIONS Pin No. P17 P18 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 T1 T2 T3 T4 T5 Pin Name CLKX2 GND ADD1 POWER GND GND AUDIOIN DVDD MRAS2#/ULCAS# MRAS1# ROMCS1# RSTOUT GND GPIO49 DDIN/GPIO45 GPIO12 GND CVDD RTCX2 CLKX1 POWERON RSTSW# GND PIUVDD ADIN0 Pin No. T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 Pin Name AVDD LCAS# ROMCS2# RD# WR# DBUS32/GPIO48 DDOUT#/GPIO44 GPIO11 GPIO8 GND GND GPIO0 RTCX1 MPOWER RTCRST# AGND TPX1 TPY0 ADIN1 DGND UCAS# ROMCS3# LDCRDY DRTS#/GPIO46 GPIO13 Pin No. U13 U14 U15 U16 U17 U18 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 Pin Name GPIO9 GPIO6 GPIO5 GPIO1 GPIO2 CGND VDD PIUGND TPX0 TPY1 ADIN2 AUDIOOUT MRAS3#/UUCAS# MRAS0# ROMCS0# VDD LCDCS# DCTS#/GPIO47 GPIO14 GPIO10 GPIO7 GPIO4 GPIO3 VDD 60 CHAPTER 2 PIN FUNCTIONS PIN IDENTIFICATION ADD [0:25] ADIN [0:2] AFERST# AGND AUDIOIN AUDIOOUT AVDD BATTINH BATTINT# BUSCLK CGND CLKSEL [0:2] CLKX1 CLKX2 CTS# CVDD DATA [0:31] DBUS32 DCD# DCTS# DDIN DDOUT DGND DRTS# DSR# DTR# DVDD FIRCLK FIRDIN# FS GND GNDP GPIO [0:49] HC0 HLDACK# HLDRQ# HSPMCLK HSPSCLK IC ILCSENSE IOCHRDY IOCS16# IOR# IOW# IRDIN : Address Bus : General Purpose Input for A/D : AFE Reset : GND for A/D : Audio Input : Audio Output : VDD for A/D : Battery Inhibit : Battery Interrupt Request : System Bus Clock : GND for Oscillator : Clock Select : Clock X1 : Clock X2 : Clear to Send : VDD for Oscillator : Data Bus : Data Bus 32 : Data Carrier Detect : Debug Serial Clear to Send : Debug Serial Data Input : Debug Serial Data Output : GND for D/A : Debug Serial Request to Send : Data Set Ready : Data Terminal Ready : VDD for D/A : FIR Clock : FIR Data Input : Frame Synchronization : Ground : Ground for PLL : General Purpose I/O : Hardware Control 0 : Hold Acknowledge : Hold Request : HSP Codec Master Clock : HSP Codec Serial Clock : Internally Connected : Input Loop Current Sensing : I/O Channel Ready : I/O Chip Select 16 : I/O Read : I/O Write : IrDA Data Input VDD VDDP WR# ZWS# UUCAS# IRDOUT# IRING KPORT [0:7] KSCAN [0:11] LCAS# LCDCS# LCDRDY LEDOUT# MEMCS16# MEMR# MEMW# MPOWER MRAS [0:3]# MUTE OFFHOOK OPD# PIUGND PIUVDD POWER POWERON RD# ROMCS [0:3]# RSTOUT RSTSW# RTCRST# RTCX1 RTCX2 RTS# RxD SDI SDO SEL SHB# TELCON TPX [0:1] TPY [0:1] TxD UCAS# ULCAS# : IrDA Data Output : Input Ring : Key Code Data Input : Key Scan Line : Lower Column Address Strobe : LCD Chip Select : LCD Ready : LED Output : Memory Chip Select 16 : Memory Read : Memory Write : Main Power : DRAM Row Address Strobe : Mute : Off Hook : Output Power Down : GND for Touch Panel Interface : VDD for Touch Panel Interface : Power Switch : Power On State : Read : ROM Chip Select : System Bus Reset Output : Reset Switch : Real-time Clock Reset : Real-time Clock X1 : Real-time Clock X2 : Request to Send : Receive Data : HSP Serial Data Input : HSP Serial Data Output : IrDA Module Select : System Hi-Byte Enable : Telephone Control : Touch Panel X I/O : Touch Panel Y I/O : Transmit Data : Upper Column Address Strobe : Lower Byte of Upper Column Address Strobe : Upper Byte of Upper Column Address Strobe : Power Supply Voltage : VDD for PLL : Write : Zero Wait State Remark # indicates active low. 61 CHAPTER 2 PIN FUNCTIONS 2.2 PIN FUNCTION DESCRIPTION The functional classification of the VR4102 pins is listed below. Remark # indicates active low. Figure 2-1. VR4102 Signal Classification RxD TxD/CLKSEL2 RTS#/CLKSEL1 DTR#/CLKSEL0 CTS# DCD#/GPIO15 DSR# FIRDIN#/SEL IRDIN IRDOUT# DDOUT/GPIO44 DDIN/GPIO45 DRTS#/GPIO46 DCTS#/GPIO47 POWER RSTSW# RTCRST# MPOWER POWERON BATTINH/ BATTINT# KPORT (0:7) KSCAN (0:11)/ GPIO (32:43) AUDIOOUT AUDIOIN CLKX1 CLKX2 RTCX1 RTCX2 FIRCLK LEDOUT# VDDP GNDP CVDD CGND DVDD DGND AVDD AGND PIUVDD PIUGND 8 12 2 2 3 50 26 16 16 ADD (0:25) DATA (0:15) DATA (16:31)/ GPIO (16:31) LCDRDY LCDCS# RD# WR# ROMCS (0:3)# UUCAS#/MRAS3# ULCAS#/MRAS2# MRAS (0:1)# UCAS# LCAS# BUSCLK SHB# IOR# IOW# MEMR# MEMW# ZWS# RSTOUT MEMCS16# IOCS16# IOCHRDY HLDRQ# HLDACK# DBUS32/GPIO48 TPX (0:1) TPY (0:1) ADIN (0:2) GPIO (0:49) IRING ILCSENSE OFFHOOK MUTE AFERST# SDI FS SDO HSPSCLK TELCON HC0 HSPMCLK OPD# RS-232C interface LCD interface 4 IrDA interface 2 Memory interface Debug serial interface System bus interface Initialization interface ISA bus interface Battery monitor interface Keyboard interface Audio interface Clock interface VR4102 Touch panel/ general-purpose A/D interface General-purpose I/O (including alternate-function pins and DCD# inputs) LED interface HSP modem interface Dedicated VDD, GND 62 CHAPTER 2 PIN FUNCTIONS 2.2.1 System Bus Interface Signals These signals are used when the VR4102 is connected to a DRAM, ROM, or LCD, or other devices in the system through the system bus. Table 2-1. System Bus Interface Signals (1/2) Signal ADD[25..0] I/O O Description of function This is a 26-bit address bus. The VR4102 uses this to specify addresses for the DRAM, ROM, LCD, or system bus (ISA). This is a 16-bit data bus. The VR4102 uses this to transmit and receive data with a DRAM, ROM, LCD, or system bus. This function differs depending on how the DBUS32 pin is set. DATA[15..0] I/O DATA[31..16]/ GPIO[31..16] I/O RD# WR# LCDRDY O O I ROMCS[3..0]# O UUCAS#/ MRAS[3]# O LCAS# O 63 CHAPTER 2 PIN FUNCTIONS Table 2-1. System Bus Interface Signals (2/2) Signal BUSCLK I/O O Description of function This is the system bus clock. It is used to output the clock that is supplied to the controller on the system bus. Its frequency is determined by the state of the CLKSEL2/TXD, CLKSEL1/RTS#, and CLKSEL0/DTR pins. (See 2.2.5 RS-232-C Interface Signals.) This is the system bus high-byte enable signal. During system bus access, this signal is active when the high-order byte is valid on the data bus. This is the system bus I/O read signal. It is active when the VR4102 accesses the system bus to read data from an I/O port. This is the system bus I/O write signal. It is active when the VR4102 accesses the system bus to write data to an I/O port. This is the system bus memory read signal. It is active when the VR4102 accesses the system bus to read data from memory. This is the system bus memory write signal. It is active when the VR4102 accesses the system bus to write data to memory. This is the system bus zero wait state signal. Set this signal as active to enable the controller on the system bus to be accessed by the VR4102 without a wait interval. This is the system bus reset signal. It is active when the VR4102 resets the system bus controller. This is a dynamic bus sizing request signal. Set this signal as active when system bus memory accesses data in 16-bit width. (However, the DRAM bus memory space that is controlled by the DBUS 32 pin is excepted.) This is a dynamic bus sizing request signal. Set this signal as active when system bus I/O accesses data in 16-bit width. This is the system bus ready signal. Set this signal as active when the system bus controller is ready to be accessed by the VR4102. This is a hold request signal for the system bus and DRAM bus that is sent from an external bus master. This is a hold acknowledge signal for the system bus and DRAM bus that is sent to an external bus master. This function differs depending on the operating status. * In normal operation (output) It can be used as a general-purpose output port. After RTC reset (input) It is a data bus width switching signal. Sampling occurs when the RTCRST signal changes from low to high. 1 : Use 32-bit width for data bus 0 : Use 16-bit width for data bus SHB# O IOR# O IOW# O MEMR# O MEMW# O ZWS# I RSTOUT MEMCS16# O I IOCS16# I IOCHRDY I HLDRQ# HLDACK# I O DBUS32/ GPIO[48] I/O * 64 CHAPTER 2 PIN FUNCTIONS 2.2.2 Clock Interface Signals These signals are used to supply clocks. Table 2-2 lists functions of these signals. Table 2-2. Clock Interface Signals Signal RTCX1 RTCX2 CLKX1 CLKX2 FIRCLK I/O I O I O I Description of function This is the 32.768-kHz oscillator's input pin. It is connected to one side of a crystal resonator. This is the 32.768-kHz oscillator's output pin. It is connected to one side of a crystal resonator. This is the 18.432-MHz oscillator's input pin. It is connected to one side of a crystal resonator. This is the 18.432-MHz oscillator's output pin. It is connected to one side of a crystal resonator. This the 48-MHz clock input pin. Fix this at high level when FIR is not used. 2.2.3 Battery Monitor Interface Signals These signals indicate when an external agent is able to provide enough power for system operations. Table 2-3 describes the functions of these signals. Table 2-3. Battery Monitor Interface Signals Signal BATTINH/ BATTINT# I/O I Description of function This function differs depending on how the MPOWER pin is set. 65 CHAPTER 2 PIN FUNCTIONS 2.2.4 Initialization Interface Signals These signals are used when an external agent initializes the processor operation parameters. describes the functions of these signals. Table 2-4 Initialization Interface Signals Signal MPOWER I/O O Description of function This signal is used to turn on the main power source. The VR4102 asserts the signal at this pin to turn on the power source for the external DC/DC converter. This signal indicates when the VR4102 is ready to operate. It becomes active when a power-on factor is detected and becomes inactive when the BATTINH/BATTINT# signal check operation is completed. This signal indicates that the POWER ON switch has been pressed. When the POWER ON switch has been pressed, an external agent must assert the signal at this pin. This signal indicates that the RESET switch has been pressed. When the RESET switch has been pressed, an external agent must assert the signal at this pin. This signal resets the RTC. When power is first supplied to a device, the external agent must assert the signal at this pin for about 600 ms. Table 2-4 POWERON O POWER I RSTSW# I RTCRST# I 66 CHAPTER 2 PIN FUNCTIONS 2.2.5 RS-232-C Interface Signals These signals control data transmission and reception between the VR4102 and an RS-232-C controller. Table 25 describes the functions of these signals. Table 2-5. RS-232-C Interface Signals Signal RxD CTS# I/O I I Description of function This is a receive data signal. It is used when the RS-232-C controller sends serial data to the VR4102. This is the transmit enable ("clear-to-send") signal. This signal is asserted when the RS-232-C controller is ready to receive transmission of serial data. This is a carrier detection signal. This signal is asserted when valid serial data is being received. It is also used when detecting a power-on factor for the VR4102. When this pin is not used for DCD# signal, this pin can be used as an interrupt detection function for the GIU unit. This is the data set ready signal. Assert this signal to set up transmission and reception of serial data between the RS-232C controller and the VR4102. This function differs depending on the operating status. * In normal operation (output) TxD signal (output): This is a transmit data signal. It is used when the VR4102 sends serial data to the RS-232C controller. RTS# signal (output): This is a transmit request signal. This signal is asserted when the VR4102 is ready to receive serial data from the RS-232C controller. DTR# signal (output): This is a terminal equipment ready signal. This signal is asserted when the VR4102 is ready to transmit or receive serial data. * After RTC reset (input) These signals are used to set the CPU core operation and BUSCLK frequency (CLKSEL[2..0]: input). Sampling occurs when the RTCRST signal changes from low to high. CLKSEL[2..0] 111 110 101 100 011 010 001 000 CPU Core frequency RFU RFU 53.6 MHz 49.2 MHz 45.4 MHz 42.1 MHz 36.9 MHz 32.8 MHz BUSCLK frequency RFU RFU 6.700 MHz 6.075 MHz 5.675 MHz 5.275 MHz 9.200 MHz 8.200 MHz DCD#/ GPIO[15] I DSR# I TxD/ CLKSEL[2], RTS#/ CLKSEL[1], DTR#/ CLKSEL[0] I/O Caution Some of these settings of frequency may not be able to select in the future. 67 CHAPTER 2 PIN FUNCTIONS 2.2.6 IrDA Interface Signals These signals are used to control data transmission and reception between the VR4102 and an IrDA controller. Table 2-6 describes the functions of these signals. Table 2-6. IrDA Interface Signals Signal IRDIN I/O I Description of function This is the IrDA serial data input signal. It is used when the VR4102 sends serial data to the IrDA controller, for both FIR and SIR. If the IrDA controller used is an HP product, however, this signal should be used for only SIR. This function differs according to the IrDA controller used (for how to switch a controller, refer to 24.2.13). x HP's controller FIRDIN#: It is a FIR receive data input signal. x TEMIC's controller SEL: It is an output port for external FIR/SIR switching. x SHARP's controller Use is prohibited. IRDOUT# O This is the IrDA serial data output signal for both SIR and FIR. It is used when the IrDA controller sends serial data to the VR4102. FIRDIN#/SEL I/O 2.2.7 Debug Serial Interface Signals These signals are used to control data transmission and reception between the VR4102 and a external debug serial controller. Table 2-7 describes the functions of these signals. Table 2-7. Debug Serial Interface Signals Signal DDOUT/ GPIO[44] I/O O Description of function This is the debug serial data output signal. It is used when an external debug serial data controller sends serial data to the VR4102. When this pin is not used for the DDOUT signal, it can be used as a general-purpose output port. This is the debug serial data input signal. It is used when the VR4102 sends serial data to an external debug serial controller. When this pin is not used for the DDIN signal, it can be used as a general-purpose output port. This is a transmission request signal. The VR4102 asserts this signal before sending serial data. When this pin is not used for the DRTS# signal, it can be used as a general-purpose output port. This is a transmit acknowledge signal. The VR4102 asserts this signal when it is ready to receive transmitted serial data. When this pin is not used for the DCTS# signal, it can be used as a general-purpose output port. DDIN/ GPIO[45] I/O DRTS#/ GPIO[46] DCTS#/ GPIO[47] O I/O 68 CHAPTER 2 PIN FUNCTIONS 2.2.8 Keyboard Interface Signals These signals are used to control a keyboard circuit to the VR4102. Table 2-8 describes the functions of these signals. Table 2-8. Keyboard Interface Signals Signal KPORT[7..0] KSCAN[11..0]/ GPIO[43..32] I/O I O Description of function This is a keyboard scan data input signal. It is used to scan for pressed keys on the keyboard. These signal are used as keyboard scan data output signals and a general-purpose output port. The scan line is set as active when scanning for pressed keys on the keyboard. Pins that are not used for the key scan operation can be used as a general-purpose output port. 2.2.9 Audio Interface Signals This signal is used to input/output audio signals. Table 2-9 describes the functions of this signal. Table 2-9. Audio Interface Signals Signal AUDIOOUT I/O O Description of function This is an audio output signal. Analog signals that have been converted via the on-chip 10-bit D/A converter are output. This pin is the audio input pin. AUDIOIN I 2.2.10 Touch Panel/General Purpose A/D Interface Signals These are the signals to the on-chip A/D converter of the VR4102. Four of these signals are used for a touch panel, one is used for audio input, and the remaining three are used as general-purpose pins. Table 2-10 describes the functions of these signals. Table 2-10. Touch Panel/General Purpose A/D Interface Signals Signal TPX[1..0] I/O I/O Description of function This is an I/O signal that is used for the touch panel. It uses the voltage applied to the X coordinate and the voltage input to the Y coordinate to detect which coordinates on the touch panel are being pressed. This is an I/O signal that is used for the touch panel. It uses the voltage applied to the Y coordinate and the voltage input to the X coordinate to detect which coordinates on the touch panel are being pressed. This is a general-purpose A/D input signal. TPY[1..0] I/O ADIN[2..0] I 69 CHAPTER 2 PIN FUNCTIONS 2.2.11 General-purpose I/O Signals These are general-purpose I/O pins of the VR4102. Ordinary, 33 of the 49 GPIO pins are used as alternatefunction pins. Table 2-11 describes the functions of these signals. Table 2-11. General-purpose I/O Signals Signal GPIO[3..0] GPIO[8..4] GPIO[12..9] GPIO[14..13] DATA[31..16]/ GPIO[31..16] KSCAN[11..0]/ GPIO[43..32] DDOUT/ GPIO[44] DDIN/GPIO[45] DRTS#/ GPIO[46] DCTS#/ GPIO[47] DBUS32/ GPIO[48] GPIO[49] I/O I/O I/O I/O I/O I/O Description of function These are maskable power-on factors. After start-up, they are used as ordinary GPIO pins. These are ordinary GPIO pins. These are maskable power-on factors. After start-up, they are used as ordinary GPIO pins. These are ordinary GPIO pins. See 2.2.1 System Bus Interface Signals. O See 2.2.8 Keyboard Interface Signals. O See 2.2.7 Debug Serial Interface Signals. I/O O See 2.2.7 Debug Serial Interface Signals. See 2.2.7 Debug Serial Interface Signals. I/O See 2.2.7 Debug Serial Interface Signals. I/O See 2.2.1 System Bus Interface Signals. I/O This function differs depending on the operating status. * In normal operation It can be used as a general-purpose output port. After RTC reset Input state. Input low level. Sampling occurs when the RTCRST signal changes from low to high. * 70 CHAPTER 2 PIN FUNCTIONS 2.2.12 HSP MODEM Interface Signals Table 2-12. HSP MODEM Interface Signals Signal IRING ILCSENSE OFFHOOK MUTE AFERST# SDI FS SDO HSPSCLK TELCON HC0 HSPMCLK OPD# I/O I I O O O I I O I O O O O Function RING signal detect signal. This pin becomes active when the RING signal is detected. Handset detect signal. On-hook relay control signal. Modem speaker mute control signal. CODEC reset signal. Serial input signal from CODEC. Frame synchronization signal from CODEC. Serial output signal to CODEC. Operation clock input of modem interface block for CODEC. Handset relay control signal. CODEC control signal. Clock output to CODEC. Use this pin for controlling power of CODEC and DAA. This signal is set as active when to set power supply to them ON. 2.2.13 LED Interface Signal Table 2-13. LED Interface Signal Signal LEDOUT# I/O O This is an output signal for lighting LEDs. Description of function 71 CHAPTER 2 PIN FUNCTIONS 2.2.14 Dedicated VDD and GND Signals Table 2-14. Dedicated VDD and GND Signals Signal VDDP GNDP CVDD CGND DVDD This is the dedicated VDD for the PLL. This is the dedicated GND for the PLL. This is the dedicated VDD for the internal oscillator. This is the dedicated GND for the internal oscillator. This is the dedicated VDD for the D/A converter. The voltage applied to this pin becomes the maximum value for AUDIOOUT's analog output. This is the dedicated GND for the D/A converter. The voltage applied to this pin becomes the minimum value for AUDIOOUT's analog output. This is the dedicated VDD for the A/D converter. The voltage applied to this pin becomes the maximum voltage value for the A/D interface signals. This is the dedicated GND for the A/D converter. The voltage applied to this pin becomes the minimum voltage value detectable by the A/D interface signals. This is the dedicated VDD for the touch panel interface. This is the dedicated GND for the touch panel interface. Description of function DGND AVDD AGND PIUVDD PIUGND 72 CHAPTER 2 PIN FUNCTIONS 2.3 PIN STATUS UPON SPECIFIC STATES 2.3.1 Pin Status upon Reset Table 2-15. Status of Pins upon Reset (1/3) Signal When reset by RTCRST 0 0 0/ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1 1 1 1 1 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z When reset by Deadman's Switch or RSTSW 0 0 0/ Hi-Z 1 1 1 1 Note 3 Note 3 Note 3 Note 3 Note 3 0 1 1 1 1 1 1 During Suspend mode Note 1 Note 1 Note 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 0 During Hibernate mode or when shut down by HAL timer 0 0 0/ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 0 0 0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z During bus hold Hi-Z Hi-Z Hi-Z/ Note 1 1 Hi-Z Hi-Z 1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note 2 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note 4 ADD[25..0] DATA[15..0] DATA[31..16]/ GPIO[31..16] LCDCS# RD# WR# LCDRDY ROMCS[3..0]# UUCAS#/MRAS[3] # ULCAS#/MRAS[2]# MRAS[1..0]# UCAS# LCAS# BUSCLK SHB# IOR# IOW# MEMR# MEMW# ZWS# RSTOUT IOCS16# MEMCS16# IOCHRDY Notes 1. 2. 3. 4. Remark The state at the previous Fullspeed mode is retained. Bus hold from Suspend mode: Outputs the low-level signal Bus hold from Fullspeed mode or standby mode: Outputs clocks. Reset by RSTSW# signal: This pin outputs the low-level signal (self refresh) Reset by Deadman's Switch: This pin outputs the high-level signal Normal operations are performed. 0: outputs low level, 1: outputs high level, Hi-Z: high-impedance 73 CHAPTER 2 PIN FUNCTIONS Table 2-15. Status of Pins upon Reset (2/3) Signal When reset by RTCRST Hi-Z 0 0 Hi-Z Hi-Z Hi-Z 0 Hi-Z Hi-Z/ Hi-Z 1 When reset by Deadman's Switch or RSTSW 1 1 0 1 1 1 0 Hi-Z Hi-Z/ Hi-Z 1 During Suspend mode Note 1 1 0 1 1 1 0 Note 2 Hi-Z/ Note 2 1 During Hibernate mode or when shut down by HAL timer Hi-Z 0 0 1 1 1 0 Hi-Z Hi-Z/ Hi-Z 1 During bus hold Note 1 1 0 Note 1 Note 1 Note 1 Note 1 Note 2 Hi-Z/ Note 2 1 HLDRQ# HLDACK# RTCX1 RTCX2 CLKX1 CLKX2 FIRCLK BATTINH/ BATTINT# MPOWER POWERON POWER RSTSW# RTCRST# RxD TxD/CLKSEL[2] RTS#/CLKSEL[1] CTS# DCD#/GPIO[15] DTR#/CLKSEL[0] DSR# IRDIN IRDOUT# FIRDIN#/SEL DDIN/ Note3 GPIO[45] DDOUT/ Note3 GPIO[44] DRTS#/ Note3 GPIO[46] DCTS#/ Note3 GPIO[47] 1 1 1 1 1 Hi-Z/ Hi-Z Hi-Z/ Hi-Z Hi-Z/ Note 2 Hi-Z/ Hi-Z Hi-Z/ Note 2 Notes 1. 2. 3. Remark Normal operations are performed. The state at the previous Fullspeed mode is retained. This pin can be switched by software between function-pin and output-port uses. 0: outputs low level, 1: outputs high level, Hi-Z: high-impedance 74 CHAPTER 2 PIN FUNCTIONS Table 2-15. Status of Pins upon Reset (3/3) Signal When reset by RTCRST Hi-Z 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 0 Hi-Z 0 0 0 1 Hi-Z Hi-Z When reset by Deadman's Switch or RSTSW Hi-Z 0 1 Hi-Z Hi-Z Hi-Z Hi-Z 0 0 Hi-Z 0 0 0 Note 3 Hi-Z Hi-Z During Suspend mode Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 3 Note 2 Note 2 During Hibernate mode or when shut down by HAL timer Hi-Z 0 1 Hi-Z Hi-Z Hi-Z Hi-Z 0 0 Hi-Z 0 0 0 Note 3 Hi-Z Hi-Z During bus hold Note 3 Note 3 Note 3 Note 3 Note 3 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 3 Note 2 Note 2 KPORT[7..0] KSCAN[11..0]/ Note 1 GPIO[43..32] AUDIOOUT TPX[1..0] TPY[1..0] ADIN[2..0] AUDIOIN GPIO[14..0] IRING ILCSENSE OFFHOOKNote 4 MUTENote 4 AFERST#Note 4 SDI FS SDO HSPSCLK TELCONNote 4 HC0Note 4 HSPMCLKNote 4 OPD# LEDOUT# DBUS32/ Note 5 GPIO[48] GPIO[49] Note 5 Notes 1. 2. 3. 4. 5. Remark This pin can be switched by software between function-pin and output-port uses. The state at the previous Fullspeed mode is retained. Normal operations are performed. Be sure to set the BSC bit (DI) of the HSPINT register (0x0C00 0020) to 1 during initialization. After RTC reset is canceled, this signal functions as an output port. 0: outputs low level, 1: outputs high level, Hi-Z: high-impedance 75 CHAPTER 2 PIN FUNCTIONS 2.3.2 Connection of Unused Pins and Pin I/O Circuits Table 2-16. Connection of Unused Pins and Pin I/O Circuit Type (1/3) Signal ADD[25..0] DATA[15..0] DATA[31..16]/ GPIO[31..16] LCDCS# RD# WR# LCDRDY ROMCS[3..0]# UUCAS#/MRAS[3]# ULCAS#/MRAS[2]# MRAS[1..0]# UCAS# LCAS# BUSCLK SHB# IOR# IOW# MEMR# MEMW# ZWS# RSTOUT IOCS16# MEMCS16# IOCHRDY Internal processing External processing / Pull up Pull down Note 1 Note 1 Pull up Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Pull up Pull up Pull up Pull up Pull up Drive capability 120 pF 40 pF 40 pF I/O circuit type A A A Note 2 Note 2 Note 2 Note 2 40 pF 120 pF 120 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF A A A A A A A A A A A A A A A A A A A A A Notes 1. Pull up when the bus hold function is used. 2. Intermediate-level input is enabled when the MPOWER pin is set for low-level output. 76 CHAPTER 2 PIN FUNCTIONS Table 2-16. Connection of Unused Pins and Pin I/O Circuit Type (2/3) Signal HLDRQ# HLDACK# RTCX1 RTCX2 CLKX1 CLKX2 FIRCLK BATTINH/ BATTINT# MPOWER POWERON POWER RSTSW# RTCRST# RxD TxD/CLKSEL[2] RTS#/CLKSEL[1] CTS# DCD#/GPIO[15] DTR#/CLKSEL[0] DSR# IRDIN IRDOUT# FIRDIN#/SEL DDIN/ Note 4 GPIO[45] DDOUT/ Note 4 GPIO[44] DRTS#/ Note 4 GPIO[46] DCTS#/ Note 4 GPIO[47] Internal processing Note 1 Schmitt Schmitt Schmitt Schmitt External processing Note 2 Resonator Resonator Resonator Resonator Note 3 Pull up Pull down Pull up Pull down Pull up Pull up Pull down Pull up Pull up Pull down Drive capability 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF I/O circuit type A A A B A A B B B A A A A A A A A A A A 40 pF A 40 pF A 40 pF A Notes 1. Intermediate-level input is enabled when the MPOWER pin is set for low-level output. 2. When the bus hold function is used : Pull up. When the bus hold function is not used : Connect to VDD. 3. When FIR unit is used : Attach an oscillator. When FIR unit is not used : Connect to VDD. 4. This pin can be switched by software between function-pin and output-port uses. 77 CHAPTER 2 PIN FUNCTIONS Table 2-16. Connection of Unused Pins and Pin I/O Circuit Type (3/3) Signal KPORT[7..0] KSCAN[11..0]/ Note 1 GPIO[43..32] AUDIOOUT TPX[1..0] TPY[1] TPY[0] ADIN[2..0] AUDIOIN GPIO[14..13] GPIO[12..9] GPIO[8..5] GPIO[4..0] IRING ILCSENSE OFFHOOKNote 3 MUTENote 3 AFERST#Note 3 SDI FS SDO HSPSCLK TELCONNote 3 HC0Note 3 HSPMCLKNote 3 OPD# LEDOUT# DBUS32/ Note 4 GPIO[48] GPIO[49] Note 4 Internal processing Schmitt, Pull down Schmitt Schmitt Schmitt External processing Note 2 Pull up Pull down Pull up Pull down Pull up Pull down Pull up Pull down Pull down Pull down Pull up Pull down Pull up Pull down Pull up Pull down Pull down Drive capability 40 pF 120 pF or more 120 pF or more 120 pF or more I/O circuit type F A G C D C 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF E E A B A B B A A A A A A A A A A A A A A A Notes 1. 2. 3. 4. This pin can be switched by software between function-pin and output-port uses. Connect an operation amplifier which has high-impedance input characteristics, since the output level of AUDIOOUT pin varies according to the external impedance. Be sure to set BSC bit (DI) of the HSPINT register (0x0C00 0020) to 1 during initialization. After RTC reset is canceled, this signal functions as an output port. 78 CHAPTER 2 PIN FUNCTIONS 2.3.3 Pin I/O Circuits Type A VDD data P-ch IN/OUT data Type D VDD P-ch IN/OUT output disable N-ch output disable P-ch N-ch input enable Type B VDD data P-ch IN/OUT input enable Vref N-ch N-ch output disable N-ch Type E IN P-ch N-ch Vref Type F VDD input enable Type C VDD data P-ch IN/OUT open drain output disable data P-ch IN/OUT N-ch output disable P-ch N-ch Vref N-ch input enable pulldown enable N-ch Type G analog output voltage OUT 79 [MEMO] 80 CHAPTER 3 CPU INSTRUCTION SET SUMMARY This chapter is an overview of the central processing unit (CPU) instruction set; refer to the Chapter 27 for detailed descriptions of individual CPU instructions. 3.1 CPU INSTRUCTION FORMATS Each CPU instruction consists of a single 32-bit word, aligned on a word boundary. There are three instruction formats - immediate (I-type), jump (J-type), and register (R-type) - as shown in Figure 3-1. The use of a small number of instruction formats simplifies instruction decoding, allowing the compiler to synthesize more complicated and less frequently used instruction and addressing modes from these three formats as needed. Figure 3-1. CPU Instruction Formats 31 I-type (immediate) 31 J-type (jump) 31 R-type (register) op: rs: rt: op op 26 25 rs 21 20 rt 16 15 rd op 26 25 target 11 10 sa 65 func 0 26 25 rs 21 20 rt 16 15 immediate 0 0 6-bit operation code 5-bit source register specifier 5-bit target (source/destination) register or branch condition immediate: 16-bit immediate value, branch displacement or address displacement target: rd: sa: func: 26-bit unconditional branch target address 5-bit destination register specifier 5-bit shift amount 6-bit function field (1) Support of the MIPS ISA The VR4102 does not support a multiprocessor operating environment. reserved instruction exception. The load/link (LL) bit is eliminated. Note that the SYNC instruction is handled as a NOP instruction since all load/store instructions in this processor are executed in program order. Thus the synchronization support instructions defined in the MIPS II and MIPS III ISA - the load linked and store conditional instructions - cause 81 CHAPTER 3 CPU INSTRUCTION SET SUMMARY 3.2 INSTRUCTION CLASSES 3.2.1 Load and Store Instructions Load and store are immediate (I-type) instructions that move data between memory and the general-purpose registers. The only addressing mode that load and store instructions directly support is base register plus 16-bit signed immediate offset. (1) Scheduling a Load Delay Slot A load instruction that does not allow its result to be used by the instruction immediately following is called a delayed load instruction. The instruction slot immediately following this delayed load instruction is referred to as the load delay slot. In the VR4000 Series, a load instruction can be followed directly by an instruction that accesses a register that is loaded by the load instruction. In this case, however, an interlock occurs for a necessary number of cycles. Any instruction can follow a load instruction, but the load delay slot should be scheduled appropriately for both performance and compatibility with the VR3000 PIPELINE. (2) Store Delay Slot When a store instruction is writing data to a cache, the data cache is kept busy at the DC and WB stages. If an instruction (such as load) that follows directly the store instruction accesses the data cache in the DC stage, a hardware-driven interlock occurs. To overcome this problem, the store delay slot should be scheduled. Table 3-1. Number of Delay Slot Cycles Necessary for Load and Store Instructions Instruction Load Store Necessary number of PCycles 1 1 TM Series microprocessors. For detail, see CHAPTER 4 VR4102 (3) Defining Access Types Access type indicates the size of a VR4102 processor data item to be loaded or stored, set by the load or store instruction opcode. Access types and accessed byte are shown in Table 3-2. Regardless of access type or byte ordering (endianness), the address given specifies the low-order byte in the addressed field. For a little-endian configuration, the low-order byte is the least-significant byte. The access type, together with the three low-order bits of the address, define the bytes accessed within the addressed doubleword (shown in Table 3-2). Only the combinations shown in Table 3-2 are permissible; other combinations cause address error exceptions. Tables 3-3 and 3-4 list the ISA-defined load/store instructions and expand-ISA instructions, respectively. 82 CHAPTER 3 CPU INSTRUCTION SET SUMMARY Figure 3-2. Byte Specification Related to Load and Store Instructions Access type (value) Low-order address bit 2 Doubleword (7) 7-byte (6) 0 0 0 6-byte (5) 0 0 5-byte (4) 0 0 Word (3) 0 1 Triple byte (2) 0 0 1 1 Halfword (1) 0 0 1 1 Byte (0) 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 7 6 5 4 3 2 1 7 6 0 5 4 3 2 7 6 6 5 5 1 0 4 3 7 6 5 4 2 2 1 1 0 7 6 5 7 6 7 63 7 6 6 6 5 5 5 5 5 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 2 1 0 2 2 2 2 2 2 1 0 1 1 1 1 0 Accessed byte (Little endian) 0 0 0 83 CHAPTER 3 CPU INSTRUCTION SET SUMMARY Table 3-2. Load/store Instruction Instruction Load Byte Format and Description op base rt offset LB rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. The bytes of the memory location specified by the address are sign extended and loaded into register rt. LBU rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. The bytes of the memory location specified by the address are zero extended and loaded into register rt. LH rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. The halfword of the memory location specified by the address is sign extended and loaded to register rt. LHU rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. The halfword of the memory location specified by the address is zero extended and loaded to register rt. LW rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. The word of the memory location specified by the address is sign extended and loaded to register rt. In the 64-bit mode, it is further sign extended to 64 bits. LWL rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. Shifts to the left the word whose address is specified so that the address-specified byte is at the leftmost position of the word. The result of the shift operation is merged with the contents of register rt and loaded to register rt. In the 64-bit mode, it is further sign extended to 64 bits. LWR rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. Shifts to the right the word whose address is specified so that the address-specified byte is at the rightmost position of the word. The result of the shift operation is merged with the contents of register rt and loaded to register rt. In the 64-bit mode, it is further sign extended to 64 bits. SB rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. The least significant byte of register rt is stored to the memory location specified by the address. SH rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. The least significant halfword of register rt is stored to the memory location specified by the address. SW rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. The lower word of register rt is stored to the memory location specified by the address. SWL rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. Shifts to the right the contents of register rt so that the left-most byte of the word is in the position of the address-specified byte. The result is stored to the lower word in memory. SWR rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. Shifts to the left the contents of register rt so that the right-most byte of the word is in the position of the address-specified byte. The result is stored to the upper word in memory. Load Byte Unsigned Load Halfword Load Halfword Unsigned Load Word Load Word Left Load Word Right Store Byte Store Halfword Store Word Store Word Left Store Word Right 84 CHAPTER 3 CPU INSTRUCTION SET SUMMARY Table 3-3. Load/store Instruction (Extended ISA) Instruction Load Doubleword Format and Description op base rt offset LD rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. The doubleword of the memory location specified by the address are loaded into register rt. LDL rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. Shifts to the left the double word whose address is specified so that the address-specified byte is at the left-most position of the double word. The result of the shift operation is merged with the contents of register rt and loaded to register rt. LDR rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. Shifts to the right the double word whose address is specified so that the address-specified byte is at the right-most position of the double word. The result of the shift operation is merged with the contents of register rt and loaded to register rt. LWU rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. The word of the memory location specified by the address are zero extended and loaded into register rt SD rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. The contents of register rt are stored to the memory location specified by the address. SDL rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. Shifts to the right the contents of register rt so that the left-most byte of the double word is in the position of the address-specified byte. The result is stored to the lower doubleword in memory. SDR rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. Shifts to the left the contents of register rt so that the right-most byte of the double word is in the position of the address-specified byte. The result is stored to the upper doubleword in memory. Load Doubleword Left Load Doubleword Right Load Word Unsigned Store Doubleword Store Doubleword Left Store Doubleword Right 85 CHAPTER 3 CPU INSTRUCTION SET SUMMARY 3.2.2 Computational Instructions Computational instructions perform arithmetic, logical, and shift operations on values in registers. Computational instructions can be either in register (R-type) format, in which both operands are registers, or in immediate (I-type) format, in which one operand is a 16-bit immediate. Computational instructions are classified as: (1) ALU immediate instructions (Tables 3-4 and 3-5) (2) Three-operand type instructions (Tables 3-6 and 3-7) (3) Shift instructions (Tables 3-8 and 3-9) (4) Multiply/divide instructions (Table 3-10 and 3-11) To maintain data compatibility between the 64- and 32-bit modes, it is necessary to sign-extend 32-bit operands correctly. If the sign extension is not correct, the 32-bit operation result is meaningless. Table 3-4. ALU Immediate Instruction Instruction Add Immediate Format and Description op rs rt immediate ADDI rt, rs, immediate The 16-bit immediate is sign extended and then added to the contents of register rs to form a 32-bit result. The result is stored into register rt. In the 64-bit mode, the operand must be sign extended. An exception occurs on the generation of 2's complement overflow. ADDIU rt, rs, immediate The 16-bit immediate is sign extended and then added to the contents of register rs to form a 32-bit result. The result is stored into register rt. In the 64-bit mode, the operand must be sign extended. No exception occurs on the generation of integer overflow. SLTI rt, rs, immediate The 16-bit immediate is sign extended and then compared to the contents of register rt treating both operands as signed integers. If rs is less than the immediate, the result is set to 1; otherwise, the result is set to 0. The result is stored to register rt. SLTIU rt, rs, immediate The 16-bit immediate is sign extended and then compared to the contents of register rt treating both operands as unsigned integers. If rs is less than the immediate, the result is set to 1; otherwise, the result is set to 0. The result is stored to register rt. ANDI rt, rs, immediate The 16-bit immediate is zero extended and then ANDed with the contents of the register. The result is stored into register rt. ORI rt, rs, immediate The 16-bit immediate is zero extended and then ORed with the contents of the register. The result is stored into register rt. XORI rt, rs, immediate The 16-bit immediate is zero extended and then Ex-ORed with the contents of the register. The result is stored into register rt. LUI rt, immediate The 16-bit immediate is shifted left by 16 bits to set the lower 16 bits of word to 0. The result is stored into register rt. In the 64-bit mode, the operand must be sign extended. Add Immediate Unsigned Set On Less Than Immediate Set On Less Than Immediate Unsigned And Immediate Or Immediate Exclusive Or Immediate Load Upper Immediate 86 CHAPTER 3 CPU INSTRUCTION SET SUMMARY Table 3-5. ALU Immediate Instruction (Extended ISA) Instruction Doubleword Add Immediate Format and Description op rs rt immediate DADDI rt, rs, immediate The 16-bit immediate is sign extended to 64 bits and then added to the contents of register rs to form a 64-bit result. The result is stored into register rt. An exception occurs on the generation of integer overflow. DADDIU rt, rs, immediate The 16-bit immediate is sign extended to 64 bits and then added to the contents of register rs to form a 64-bit result. The result is stored into register rt. No exception occurs on the generation of overflow. Doubleword Add Immediate Unsigned Table 3-6. Three Operand Type Instruction Instruction Add Format and Description op rs rt rd sa funct ADD rd, rs, rt The contents of registers rs and rt are added together to form a 32-bit result. The result is stored into register rd. In the 64-bit mode, the operand must be sign extended. An exception occurs on the generation of integer overflow. ADDU rd, rs, rt The contents of registers rs and rt are added together to form a 32-bit result. The result is stored into register rd. In the 64-bit mode, the operand must be sign extended. No exception occurs on the generation of integer overflow. SUB rd, rs, rt The contents of register rt are subtracted from the contents of register rs. The 32-bit result is stored into register rd. In the 64-bit mode, the operand must be sign extended. An exception occurs on the generation of integer overflow. SUBU rd, rs, rt The contents of register rt are subtracted from the contents of register rs. The 32-bit result is stored into register rd. In the 64-bit mode, the operand must be sign extended. No exception occurs on the generation of integer overflow. SLT rd, rs, rt The contents of registers rs and rt are compared, treating both operands as signed integers. If the contents of register rs is less than that of register rt, the result is set to 1; otherwise, the result is set to 0. The result is stored to register rd. SLTU rd, rs, rt The contents of registers rs and rt are compared treating both operands as unsigned integers. If the contents of register rs is less than that of register rt, the result is set to 1; otherwise, the result is set to 0. The result is stored to register rd. AND rd, rt, rs The contents of register rs are logical ANDed with that of general register rt bit-wise. The result is stored to register rd. OR rd, rt, rs The contents of register rs are logical ORed with that of general register rt bit-wise. The result is stored to register rd. XOR rd, rt, rs The contents of register rs are logical Ex-ORed with that of general register rt bit-wise. The result is stored to register rd. NOR rd, rt, rs The contents of register rs are logical NORed with that of general register rt bit-wise. The result is stored to register rd. Add Unsigned Subtract Subtract Unsigned Set On Less Than Set On Less Than Unsigned And Or Exclusive Or Nor 87 CHAPTER 3 CPU INSTRUCTION SET SUMMARY Table 3-7. Three Operand Type Instruction (Extended ISA) Instruction Doubleword Add Format and Description op rs rt rd sa funct DADD rd, rt, rs The contents of register rs are added to that of register rt. The 64-bit result is stored into register rd. An exception occurs on the generation of integer overflow. DADDU rd, rt, rs The contents of register rs are added to that of register rt. The 64-bit result is stored into register rd. No exception occurs on the generation of integer overflow. DSUB rd, rt, rs The contents of register rt are subtracted from that of register rs. The 64-bit result is stored into register rd. An exception occurs on the generation of integer overflow. DSUBU rd, rt, rs The contents of register rt are subtracted from that of register rs. The 64-bit result is stored into register rd. No exception occurs on the generation of integer overflow. Doubleword Add Unsigned Doubleword Subtract Doubleword Subtract Unsigned Table 3-8. Shift Instruction Instruction Shift Left Logical Format and Description op rs rt rd sa funct SLL rd, rs, sa The contents of register rt are shifted left by sa bits and zeros are inserted into the emptied lower bits. The 32-bit result is stored into register rd. In the 64-bit mode, the operand must be sign extended. SRL rd, rs, sa The contents of register rt are shifted right by sa bits and zeros are inserted into the emptied higher bits. The 32-bit result is stored into register rd. In the 64-bit mode, the operand must be sign extended. SRA rd, rt, sa The contents of register rt are shifted right by sa bits and the emptied higher bits are sign extended. The 32-bit result is stored into register rd. In the 64-bit mode, the operand must be sign extended. SLLV rd, rt, rs The contents of register rt are shifted left and zeros are inserted into the emptied lower bits. The lower five bits of register rs specify the shift count. The 32-bit result is stored into register rd. In the 64-bit mode, the operand must be sign extended. SRLV rd, rt, rs The contents of register rt are shifted right and zeros are inserted into the emptied higher bits. The lower five bits of register rs specify the shift count. The 32-bit result is stored into register rd. In the 64bit mode, the operand must be sign extended. SRAV rd, rt, rs The contents of register rt are shifted right and the emptied higher bits are sign extended. The lower five bits of register rs specify the shift count. The 32-bit result is stored into register rd. In the 64-bit mode, the operand must be sign extended. Shift Right Logical Shift Right Arithmetic Shift Left Logical Variable Shift Right Logical Variable Shift Right Arithmetic Variable 88 CHAPTER 3 CPU INSTRUCTION SET SUMMARY Table 3-9. Shift Instruction (Extended ISA) Instruction Doubleword Shift Left Logical Format and Description op rs rt rd sa funct DSLL rd, rs, sa The contents of register rt are shifted left by sa bits and zeros are inserted into the emptied lower bits. The 64-bit result is stored into register rd. DSRL rd, rs, sa The contents of register rt are shifted right by sa bits and zeros are inserted into the emptied higher bits. The 64-bit result is stored into register rd. DSRA rd, rt, sa The contents of register rt are shifted right by sa bits and the emptied higher bits are sign extended. The 64-bit result is stored into register rd. DSLLV rd, rt, rs The contents of register rt are shifted left and zeros are inserted into the emptied lower bits. The lower six bits of register rs specify the shift count. The 64-bit result is stored into register rd. DSRLV rd, rt, rs The contents of register rt are shifted right and zeros are inserted into the emptied higher bits. The lower six bits of register rs specify the shift count. The 64-bit result is stored into register rd. DSRAV rd, rt, rs The contents of register rt are shifted right and the emptied higher bits are sign extended. The lower six bits of register rs specify the shift count. The 64-bit result is stored into register rd. DSLL32 rd, rt, sa The contents of register rt are shifted left by 32 + sa bits and zeros are inserted into the emptied lower bits. The 64-bit result is stored into register rd. DSRL32 rd, rt, sa The contents of register rt are shifted right by 32 + sa bits and zeros are inserted into the emptied higher bits. The 64-bit result is stored into register rd. DSRA32 rd, rt, sa The contents of register rt are shifted right by 32 + sa bits and the emptied higher bits are sign extended. The 64-bit result is stored into register rd. Doubleword Shift Right Logical Doubleword Shift Right Arithmetic Doubleword Shift Left Logical Variable Doubleword Shift Right Logical Variable Doubleword Shift Right Arithmetic Variable Doubleword Shift Left Logical + 32 Doubleword Shift Right Logical + 32 Doubleword Shift Right Arithmetic + 32 89 CHAPTER 3 CPU INSTRUCTION SET SUMMARY Table 3-10. Multiply/Divide Instructions Instruction Multiply Format and Description op rs rt rd sa funct MULT rs, rt The contents of registers rt and rs are multiplied, treating both operands as 32-bit signed integers. The 64-bit result is stored into special registers HI and LO. In the 64-bit mode, the operand must be sign extended. MULTU rs, rt The contents of registers rt and rs are multiplied, treating both operands as 32-bit unsigned integers. The 64-bit result is stored into special registers HI and LO. In the 64-bit mode, the operand must be sign extended. DIV rs, rt The contents of register rs are divided by that of register rt, treating both operands as 32-bit signed integers. The 32-bit quotient is stored into special register LO, and the 32-bit remainder is stored into special register HI. In the 64-bit mode, the operand must be sign extended. DIVU rs, rt The contents of register rs are divided by that of register rt, treating both operands as 32-bit unsigned integers. The 32-bit quotient is stored into special register LO, and the 32-bit remainder is stored into special register HI. In the 64-bit mode, the operand must be sign extended. Multiply Unsigned Divide Divide Unsigned Move From HI MFHI rd The contents of special register HI are loaded into register rd. MFLO rd The contents of special register LO are loaded into register rd. MTHI rs The contents of register rs are loaded into special register HI. MTLO rs The contents of register rs are loaded into special register LO. Move From LO Move To HI Move To LO Table 3-11. Multiply/Divide Instructions (Extended ISA) (1/2) Instruction Doubleword Multiply Format and Description op rs rt rd sa funct DMULT rs, rt The contents of registers rt and rs are multiplied, treating both operands as signed integers. The 128bit result is stored into special registers HI and LO. DMULTU rs, rt The contents of registers rt and rs are multiplied, treating both operands as unsigned integers. The 128-bit result is stored into special registers HI and LO. DDIV rs, rt The contents of register rs are divided by that of register rt, treating both operands as signed integers. The 64-bit quotient is stored into special register LO, and the 64-bit remainder is stored into special register HI. DDIVU rs, rt The contents of register rs are divided by that of register rt, treating both operands as unsigned integers. The 64-bit quotient is stored into special register LO, and the 64-bit remainder is stored into special register HI. Doubleword Multiply Unsigned Doubleword Divide Doubleword Divide Unsigned 90 CHAPTER 3 CPU INSTRUCTION SET SUMMARY Table 3-11. Multiply/Divide Instructions (Extended ISA) (2/2) Instruction Multiply and Add 16bit Integer Format and Description op rs rt rd sa funct MADD16 rs, rt The contents of registers rt and rs are multiplied, treating both operands as 16-bit signed integers (by sign extending to 64 bits). The result is added to the combined value of special registers HI and LO. The 64-bit result is stored into special registers HI and LO. DMADD16 rs, rt The contents of registers rt and rs are multiplied, treating both operands as 16-bit signed integers (by sign extending to 64 bits). The result is added to value of special register LO. The 64-bit result is stored into special register LO. Doubleword Multiply and Add 16-bit Integer MFHI and MFLO instructions after a multiply or divide instruction generate interlocks to delay execution of the next instruction, inhibiting the result from being read until the multiply or divide instruction completes. Table 3-12 gives the number of processor cycles (PCycles) required to resolve interlock or stall between various multiply or divide instructions and a subsequent MFHI or MFLO instruction. Table 3-12. Number of Stall Cycles in Multiply and Divide Instructions Instruction MULT MULTU DIV DIVU DMULT DMULTU DDIV DDIVU MADD16 DMADD16 Number of instruction cycles 1 1 35 35 4 4 67 67 1 1 91 CHAPTER 3 CPU INSTRUCTION SET SUMMARY 3.2.3 Jump and Branch Instructions Jump and branch instructions change the control flow of a program. All jump and branch instructions occur with a delay of one instruction: that is, the instruction immediately following the jump or branch instruction (this is known as the instruction in the delay slot) always executes while the target instruction is being fetched from memory. For instructions involving a link (such as JAL and BLTZAL), the return address is saved in register r31. Table 3-13. Number of Delay Slot Cycles in Jump and Branch Instructions Instruction Branch instruction Jump instruction Necessary number of cycles 1 1 (1) Overview of jump instructions Subroutine calls in high-level languages are usually implemented with J or JAL instructions, both of which are Jtype instructions. In J-type format, the 26-bit target address shifts left 2 bits and combines with the high-order 4 bits of the current program counter to form a 32-bit or 64-bit absolute address. Returns, dispatches, and cross-page jumps are usually implemented with the JR or JALR instructions. Both are R-type instructions that take the 32-bit or 64-bit byte address contained in one of the general-purpose registers. For more information, refer to Chapter 27. (2) Overview of branch instructions A branch instruction has a PC-related signed 16-bit offset. Tables 3-14 through 3-16 show the lists of Jump, Branch, and Extended ISA instructions, respectively. 92 CHAPTER 3 CPU INSTRUCTION SET SUMMARY Table 3-14. Jump Instruction Instruction Jump Format and Description op target J target The contents of 26-bit target address is shifted left by two bits and combined with the high-order four bits of the PC. The program jumps to this calculated address with a delay of one instruction. JAL target The contents of 26-bit target address is shifted left by two bits and combined with the high-order four bits of the PC. The program jumps to this calculated address with a delay of one instruction. The address of the instruction following the delay slot is stored into r31 (link register). Jump And Link Instruction Jump Register Format and Description op rs rt rd sa funct JR rs The program jumps to the address specified in register rs with a delay of one instruction. JALR rs, rd The program jumps to the address specified in register rs with a delay of one instruction. The address of the instruction following the delay slot is stored into rd. Jump And Link Register There are the following common restrictions for Tables 3-15 and 3-16. (1) Branch address All branch instruction target addresses are computed by adding the address of the instruction in the delay slot to the 16-bit offset (shifted left by 2 bits and sign-extended to 64 bits). All branches occur with a delay of one instruction. (2) Operation when unbranched If the branch condition does not meet in executing a Likely instruction, the instruction in its delay slot is nullified. For all other branch instructions, the instruction in its delay slot is unconditionally executed. Remark The target instruction of the branch is fetched at the EX stage of the branch instruction. Comparison of the operands of the branch instruction and calculation of the target address is performed at phase 2 of the RF stage and phase 1 of the EX stage of the instruction. Branch instructions require one cycle of the branch delay slot defined by the architecture. Jump instructions also require one cycle of delay slot. If the branch condition is not satisfied in a branch likely instruction, the instruction in its delay slot is nullified. 93 CHAPTER 3 CPU INSTRUCTION SET SUMMARY There are special symbols used in the instruction formats of Tables 3-15 through 3-19. REGIMM : Opcode Sub CO BC br op : Sub-operation code : Sub-operation identifier : BC sub-operation code : Branch condition identifier : Operation code Table 3-15. Branch Instructions Instruction Branch On Equal Format and Description op rs rt offset BEQ rs, rt, offset If the contents of register rs are equal to that of register rt, the program branches to the target address. BNE rs, rt, offset If the contents of register rs are not equal to that of register rt, the program branches to the target address. BLEZ rs, offset If the contents of register rs are less than or equal to zero, the program branches to the target address. BGTZ rs, offset If the contents of register rs are greater than zero, the program branches to the target address. Branch On Not Equal Branch On Less Than Or Equal To Zero Branch On Greater Than Zero Instruction Branch On Less Than Zero Branch On Greater Than Or Equal To Zero Branch On Less Than Zero And Link Format and Description REGIMM rs sub offset BLTZ rs, offset If the contents of register rs are less than zero, the program branches to the target address. BGEZ rs, offset If the contents of register rs are greater than or equal to zero, the program branches to the target address. BLTZAL rs, offset The address of the instruction that follows delay slot is stored to register r31 (link register). If the contents of register rs are less than zero, the program branches to the target address. BGEZAL rs, offset The address of the instruction that follows delay slot is stored to register r31 (link register). If the contents of register rs are greater than or equal to zero, the program branches to the target address. Branch On Greater Than Or Equal To Zero And Link Instruction Branch On Coprocessor 0 True Format and Description COP0 BC br offset BC0T offset Adds the 16-bit offset (shifted left by two bits and sign extended to 32 bits) to the address of the instruction in the delay slot to calculate out the branch target address. If the conditional signal of the coprocessor 0 is true, the program branches to the target address with one-instruction delay. BC0F offset Adds the 16-bit offset (shifted left by two bits and sign extended to 32 bits) to the address of the instruction in the delay slot to calculate out the branch target address. If the conditional signal of the coprocessor 0 is false, the program branches to the target address with one-instruction delay. Branch On Coprocessor 0 False 94 CHAPTER 3 CPU INSTRUCTION SET SUMMARY Table 3-16. Branch Instructions (Extended ISA) Instruction Branch On Equal Likely Format and Description op rs rt offset BEQL rs, rt, offset If the contents of register rs are equal to that of register rt, the program branches to the target address. If the branch condition is not met, the instruction in the delay slot is discarded. BNEL rs, rt, offset If the contents of register rs are not equal to that of register rt, the program branches to the target address. If the branch condition is not met, the instruction in the delay slot is discarded. BLEZL rs, offset If the contents of register rs are less than or equal to zero, the program branches to the target address. If the branch condition is not met, the instruction in the delay slot is discarded. BGTZ rs, offset If the contents of register rs are greater than zero, the program branches to the target address. If the branch condition is not met, the instruction in the delay slot is discarded. Branch On Not Equal Likely Branch On Less Than Or Equal To Zero Likely Branch On Greater Than Zero Instruction Branch On Less Than Zero Likely Format and Description REGIMM rs sub offset BLTZL rs, offset If the contents of register rs are less than zero, the program branches to the target address. If the branch condition is not met, the instruction in the delay slot is discarded. BGEZL rs, offset If the contents of register rs are greater than or equal to zero, the program branches to the target address. If the branch condition is not met, the instruction in the delay slot is discarded. BLTZALL rs, offset The address of the instruction that follows delay slot is stored to register r31 (link register). If the contents of register rs are less than zero, the program branches to the target address. If the branch condition is not met, the instruction in the delay slot is discarded. BGEZALL rs, offset The address of the instruction that follows delay slot is stored to register r31 (link register). If the contents of register rs are greater than or equal to zero, the program branches to the target address. If the branch condition is not met, the instruction in the delay slot is discarded. Branch On Greater Than Or Equal To Zero Likely Branch On Less Than Zero And Link Likely Branch On Greater Than Or Equal To Zero And Link Likely Instruction Branch On Coprocessor 0 True Likely Format and Description COP0 BC br offset BC0TL offset Adds the 16-bit offset (shifted left by two bits and sign extended to 32 bits) to the address of the instruction in the delay slot to calculate out the branch target address. If the conditional signal of the coprocessor 0 is true, the program branches to the target address with one-instruction delay. If the branch condition is not met, the instruction in the delay slot is discarded. BC0FL offset Adds the 16-bit offset (shifted left by two bits and sign extended to 32 bits) to the address of the instruction in the delay slot to calculate out the branch target address. If the conditional signal of the coprocessor 0 is false, the program branches to the target address with one-instruction delay. If the branch condition is not met, the instruction in the delay slot is discarded. Branch On Coprocessor 0 False Likely 95 CHAPTER 3 CPU INSTRUCTION SET SUMMARY 3.2.4 Special Instructions Special instructions generate software exceptions. Their formats are R-type (Syscall, Break). The Trap instruction is available only for the VR4000 Series. All the other instructions are available for all VR Series. Table 3-17. Special Instructions Instruction Synchronize Format and Description SPECIAL rs rt rd sa funct SYNC Completes the load/store instruction executing in the current pipeline before the next load/store instruction starts execution. SYSCALL Generates a system call exception, and then transits control to the exception handling program. BREAK Generates a break point exception, and then transits control to the exception handling program. System Call Breakpoint Table 3-18. Special Instructions (Extended ISA) (1/2) Instruction Trap If Greater Than Or Equal Format and Description SPECIAL rs rt rd sa funct TGE rs, rt The contents of register rs are compared with that of register rt, treating both operands as signed integers. If the contents of register rs are greater than or equal to that of register rt, an exception occurs. TGEU rs, rt The contents of register rs are compared with that of register rt, treating both operands as unsigned integers. If the contents of register rs are greater than or equal to that of register rt, an exception occurs. TLT rs, rt The contents of register rs are compared with that of register rt, treating both operands as signed integers. If the contents of register rs are less than that of register rt, an exception occurs. TLTU rs, rt The contents of register rs are compared with that of register rt, treating both operands as unsigned integers. If the contents of register rs are less than that of register rt, an exception occurs. TEQ rs, rt If the contents of registers rs and rt are equal, an exception occurs. TNE rs, rt If the contents of registers rs and rt are not equal, an exception occurs. Trap If Greater Than Or Equal Unsigned Trap If Less Than Trap If Less Than Unsigned Trap If Equal Trap If Not Equal 96 CHAPTER 3 CPU INSTRUCTION SET SUMMARY Table 3-18. Special Instruction (Extended ISA) (2/2) Instruction Trap If Greater Than Or Equal Immediate Format and Description REGIMM rs sub immediate TGEI rs, immediate The contents of register rs are compared with 16-bit sign-extended immediate data, treating both operands as signed integers. If the contents of register rs are greater than or equal to 16-bit signextended immediate data, an exception occurs. TGEIU rs, immediate The contents of register rs are compared with 16-bit zero-extended immediate data, treating both operands as unsigned integers. If the contents of register rs are greater than or equal to 16-bit signextended immediate data, an exception occurs. TLTI rs, immediate The contents of register rs are compared with 16-bit sign-extended immediate data, treating both operands as signed integers. If the contents of register rs are less than 16-bit sign-extended immediate data, an exception occurs. TLTIU rs, immediate The contents of register rs are compared with 16-bit zero-extended immediate data, treating both operands as unsigned integers. If the contents of register rs are less than 16-bit sign-extended immediate data, an exception occurs. TEQI rs, immediate If the contents of register rs and immediate data are equal, an exception occurs. TNEI rs, immediate If the contents of register rs and immediate data are not equal, an exception occurs. Trap If Greater Than Or Equal Immediate Unsigned Trap If Less Than Immediate Trap If Less Than Immediate Unsigned Trap If Equal Immediate Trap If Not Equal Immediate 3.2.5 System Control Coprocessor (CP0) Instructions System control coprocessor (CP0) instructions perform operations specifically on the CP0 registers to manipulate the memory management and exception handling facilities of the processor. Table 3-19. System Control Coprocessor (CP0) Instructions (1/2) Instruction Move To System Control Coprocessor Format and Description COP0 sub rt rd 0 MTC0 rt, rd The word data of general-purpose register rt in the CPU are loaded into general-purpose register rd in the CP0. MFC0 rt, rd The word data of general-purpose register rd in the CP0 are loaded into general-purpose register rt in the CPU. DMTC0 rt, rd The doubleword data of general-purpose register rt in the CPU are loaded into general-purpose register rd in the CP0. DMFC0 rt, rd The doubleword data of general-purpose register rd in the CP0 are loaded into general-purpose register rt in the CPU. Move From System Control Coprocessor Doubleword Move To System Control Coprocessor 0 Doubleword Move From System Control Coprocessor 0 97 CHAPTER 3 CPU INSTRUCTION SET SUMMARY Table 3-19. System Control Coprocessor (CP0) Instructions (2/2) Instruction Read Indexed TLB Entry Format and Description COP0 CO funct TLBR The TLB entry indexed by the index register is loaded into the entryHi, entryLo0, entryLo1, or page mask register. TLBWI The contents of the entryHi, entryLo0, entryLo1, or page mask register are loaded into the TLB entry indexed by the index register. TLBWR The contents of the entryHi, entryLo0, entryLo1, or page mask register are loaded into the TLB entry indexed by the random register. TLBP The address of the TLB entry that matches with the contents of entryHi register is loaded into the index register. ERET The program returns from exception, interrupt, or error trap. Write Indexed TLB Entry Write Random TLB Entry Probe TLB For Matching Entry Return From Exception Instruction STANDBY Format and Description COP0 CO funct STANDBY The processor's operating mode is transited from fullspeed mode to standby mode. SUSPEND The processor's operating mode is transited from fullspeed mode to suspend mode. HIBERNATE The processor's operating mode is transited from fullspeed mode to hibernate mode. SUSPEND HIBERNATE Instruction Cache Operation Format and Description CACHE base op offset Cache op, offset (base) The 16-bit offset is sign extended to 32 bits and added to the contents of the register case, to form virtual address. This virtual address is translated to physical address with TLB. For this physical address, cache operation that is indicated by 5-bit sub-opcode is performed. 98 CHAPTER 4 VR4102 PIPELINE This chapter describes the basic operation of the VR4102 processor pipeline, which includes descriptions of the delay slots (instructions that follow a branch or load instruction in the pipeline), interrupts to the pipeline flow caused by interlocks and exceptions, and CP0 hazards. 4.1 PIPELINE STAGES The VR4102 has a five-stage instruction pipeline; each stage takes one PCycle (one cycle of Pclock), and each PCycle has two phases: )1 and )2, as shown in Figure 4-1. Thus, the execution of each instruction takes at least 5 PCycles. An instruction can take longer - for example, if the required data is not in the cache, the data must be retrieved from main memory. Once the pipeline has been filled, five instructions are executed simultaneously. Figure 4-1. Pipeline Stages PCycle PClock Phase Cycle )1 IF )2 )1 RF )2 )1 EX )2 )1 DC )2 )1 WB )2 The five pipeline stages are: -- IF - Instruction cache fetch -- RF - Register fetch -- EX - Execution -- DC - Data cache fetch -- WB - Write back Figure 4-2 shows the five stages of the instruction pipeline. In this figure, a row indicates the execution process of each instruction, and a column indicates the processes executed simultaneously. 99 CHAPTER 4 VR4102 PIPELINE Figure 4-2. Instruction Execution in the Pipeline PCycle IF1 IF2 (Five stages) RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2 IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2 IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2 IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2 IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2 Current CPU cycle 4.1.1 Pipeline Activities Figure 4-3 shows the activities that can occur during each pipeline stage; Table 4-1 describes these pipeline activities. Figure 4-3. Pipeline Activities PCycle PClock Phase Cycle I Fetch and Decode ALU Load/Store Branch BAC )1 IF1 IDC ITLB )2 IF2 ICA ITC IDEC RF EX DVA SA DCA DTLB DLA DTC )1 RF1 )2 RF2 )1 EX1 )2 EX2 )1 DC1 )2 DC2 )1 WB1 )2 WB2 WB WB DCW DTD 100 CHAPTER 4 VR4102 PIPELINE Table 4-1. Description of Pipeline Activities during Each Stage Cycle Phase )1 IF )2 )1 RF )2 )1 Mnemonic IDC ITLB ICA ITC IDEC RF BAC EX DVA EX )2 )1 DC SA DCA DTLB DLA DTC DTD WB )1 DCW WB Description Instruction cache address decode Instruction address translation Instruction cache array access Instruction tag check Instruction decode Register operand fetch Branch address calculation Execution stage Data virtual address calculation Store align Data cache address decode/array access Data address translation Data cache load align Data tag check Data transfer to data cache Data cache write Write back to register file 101 CHAPTER 4 VR4102 PIPELINE 4.2 BRANCH DELAY During a VR4102's pipeline operation, a one-cycle branch delay occurs when: x Target address is calculated by a Jump instruction x Branch condition of branch instruction is met and then logical operation starts for branch-destination comparison The instruction address generated at the EX stage in the Jump/Branch instruction are available in the IF stage, two instructions later. Figure 4-4 illustrates the branch delay and the location of the branch delay slot. Figure 4-4. Branch Delay PCycle Branch IF RF IF EX RF IF DC EX RF WB DC EX WB DC WB (Branch delay slot) Target Branch delay 4.3 LOAD DELAY A load instruction that does not allow its result to be used by the instruction immediately following is called a delayed load instruction. The instruction immediately following this delayed load instruction is referred to as the load delay slot. In the VR4102, the instruction immediately following a load instruction can use the contents of the loaded register, however in such cases hardware interlocks insert additional delay cycles. Consequently, scheduling load delay slots can be desirable, both for performance and VR-Series processor compatibility. 4.4 PIPELINE OPERATION The operation of the pipeline is illustrated by the following examples that describe how typical instructions are executed. The instructions described are: ADD, JALR, BEQ, TLT, LW, and SW. Each instruction is taken through the pipeline and the operations that occur in each relevant stage are described. 102 CHAPTER 4 VR4102 PIPELINE (1) Add instruction (Add rd, rs, rt) IF stage In )1 of the IF stage, the eleven least-significant bits of the virtual address are used to access the instruction cache. In )2 of the IF stage, the cache index is compared with the page frame number and the cache data is read out. The virtual PC is incremented by 4 so that the next instruction can be fetched. RF stage During )2, the 2-port register file is addressed with the rs and rt fields and the register data is valid at the register file output. At the same time, bypass multiplexers select inputs from either the EXor DC-stage output in addition to the register file output, depending on the need for an operand bypass. EX stage The ALU controls are set to do an A + B operation. The operands flow into the ALU inputs, and the ALU operation is started. The result of the ALU operation is latched into the ALU output latch during )1. DC stage This stage is a NOP for this instruction. The data from the output of the EX stage (the ALU) is moved into the output latch of the DC. WB stage During )1, the WB latch feeds the data to the inputs of the register file, which is accessed by the rd field. The file write strobe is enabled. By the end of )1, the data is written into the file. Figure 4-5. Add Instruction Pipeline Activities PCycle PClock Phase Cycle )1 IF1 IDC ITLB )2 IF2 ICA ITC IDEC RF EX WB )1 RF1 )2 RF2 )1 EX1 )2 EX2 )1 DC1 )2 DC2 )1 WB1 )2 WB2 103 CHAPTER 4 VR4102 PIPELINE (2) Jump and Link Register instruction (JALR rd, rs) IF stage Same as the IF stage for the ADD instruction. RF stage A register specified in the rs field is read from the file during )2 at the RF stage, and the value read from the rs register is input to the virtual PC latch synchronously. This value is used to fetch an instruction at the jump destination. The value of the virtual PC incremented during the IF stage is incremented again to produce the link address PC + 8 where PC is the address of the JALR instruction. The resulting value is the PC to which the program will eventually return. This value is placed in the Link output latch of the Instruction Address unit. EX stage The PC + 8 value is moved from the Link output latch to the output latch of the EX stage. DC stage The PC + 8 value is moved from the output latch of the EX stage to the output latch of the DC stage. WB stage Refer to the ADD instruction. Note that if no value is explicitly provided for rd then register 31 is used as the default. If rd is explicitly specified, it cannot be the same register addressed by rs; if it is, the result of executing such an instruction is undefined. Figure 4-6. JALR Instruction Pipeline Activities PCycle PClock Phase Cycle )1 IF1 IDC ITLB )2 IF2 ICA ITC IDEC RF BAC EX WB )1 RF1 )2 RF2 )1 EX1 )2 EX2 )1 DC1 )2 DC2 )1 WB1 )2 WB2 104 CHAPTER 4 VR4102 PIPELINE (3) Branch on Equal instruction (BEQ rs, rt, offset) IF stage Same as the IF stage for the ADD instruction. RF stage During )2, the register file is addressed with the rs and rt fields. A check is performed to determine if each corresponding bit position of these two operands has equal values. If they are equal, the PC is set to PC + target, where target is the sign-extended offset field. If they are not equal, the PC is set to PC + 4. EX stage The next PC resulting from the branch comparison is valid at the beginning of )2 for instruction fetch. DC stage This stage is a NOP for this instruction. WB stage This stage is a NOP for this instruction. Figure 4-7. BEQ Instruction Pipeline Activities PCycle PClock Phase Cycle )1 IF1 IDC ITLB )2 IF2 ICA ITC IDEC RF BAC EX )1 RF1 )2 RF2 )1 EX1 )2 EX2 )1 DC1 )2 DC2 )1 WB1 )2 WB2 105 CHAPTER 4 VR4102 PIPELINE (4) Trap if Less Than instruction (TLT rs, rt) IF stage Same as the IF stage for the ADD instruction. RF stage Same as the RF stage for the ADD instruction. EX stage ALU controls are set to do an A - B operation. The operands flow into the ALU inputs, and the ALU operation is started. The result of the ALU operation is latched into the ALU output latch during )1. The sign bits of operands and of the ALU output latch are checked to determine if a less than condition is true. If this condition is true, a Trap exception occurs. The value in the PC register is used as an exception vector value, and from now on any instruction will be invalid. DC stage No operation WB stage The EPC register is loaded with the value of the PC if the less than condition was met in the EX stage. The Cause register ExCode field and BD bit are updated appropriately, as is the EXL bit of the Status register. If the less than condition was not met in the EX stage, no activity occurs in the WB stage. Figure 4-8. TLT Instruction Pipeline Activities PCycle PClock Phase Cycle )1 IF1 IDC ITLB )2 IF2 ICA ITC IDEC RF EX )1 RF1 )2 RF2 )1 EX1 )2 EX2 )1 DC1 )2 DC2 )1 WB1 )2 WB2 106 CHAPTER 4 VR4102 PIPELINE (5) Load Word instruction (LW rt, offset (base)) IF stage Same as the IF stage for the ADD instruction. RF stage Same as the RF stage for the ADD instruction. Note that the base field is in the same position as the rs field. EX stage Refer to the EX stage for the ADD instruction. For LW, the inputs to the ALU come from GPR[base] through the bypass multiplexer and from the sign-extended offset field. The result of the ALU operation that is latched into the ALU output latch in )1 represents the effective virtual address of the operand (DVA). DC stage The cache tag field is compared with the Page Frame Number (PFN) field of the TLB entry. After passing through the load aligner, aligned data is placed in the DC output latch during )2. During )1, the cache read data is written into the register file addressed by the rt field. Figure 4-9. LW Instruction Pipeline Activities WB stage PCycle PClock Phase Cycle )1 IF1 IDC ITLB )2 IF2 ICA ITC IDEC RF EX DVA DCA DTLB DLA DTC )1 RF1 )2 RF2 )1 EX1 )2 EX2 )1 DC1 )2 DC2 )1 WB1 )2 WB2 WB 107 CHAPTER 4 VR4102 PIPELINE (6) Store Word instruction (SW rt, offset (base)) IF stage Same as the IF stage for the ADD instruction. RF stage Same as the RF stage for the LW instruction. EX stage Refer to the LW instruction for a calculation of the effective address. From the RF output latch, the GPR[rt] is sent through the bypass multiplexer and into the main shifter, where the shifter performs the byte-alignment operation for the operand. The results of the ALU are latched in the output latches during )1. The shift operations are latched in the output latches during )2. DC stage Refer to the LW instruction for a description of the cache access. WB stage If there was a cache hit, the content of the store data output latch is written into the data cache at the appropriate word location. Note that all store instructions use the data cache for two consecutive PCycles. If the following instruction requires use of the data cache, the pipeline is slipped for one PCycle to complete the writing of an aligned store data. Figure 4-10. SW Instruction Pipeline Activities PCycle PClock Phase Cycle )1 IF1 IDC ITLB )2 IF2 ICA ITC IDEC RF EX DVA SA DTLB DTC )1 RF1 )2 RF2 )1 EX1 )2 EX2 )1 DC1 )2 DC2 )1 WB1 )2 WB2 DTD DCW 108 CHAPTER 4 VR4102 PIPELINE 4.5 INTERLOCK AND EXCEPTION HANDLING Smooth pipeline flow is interrupted when cache misses or exceptions occur, or when data dependencies are detected. Interruptions handled using hardware, such as cache misses, are referred to as interlocks, while those that are handled using software are called exceptions. conditions are collectively referred to as faults. Figure 4-11. Interlocks, Exceptions, and Faults Faults Software Hardware As shown in Figure 4-11, all interlock and exception Exceptions Interlocks Abort Stall Slip At each cycle, exception and interlock conditions are checked for all active instructions. Because each exception or interlock condition corresponds to a particular pipeline stage, a condition can be traced back to the particular instruction in the exception/interlock stage, as shown in Table 4-2. For instance, an LDI Interlock is raised in the Register Fetch (RF) stage. Tables 4-2 to 4-4 describe the pipeline interlocks and exceptions listed in Table 4-2. 109 CHAPTER 4 VR4102 PIPELINE Table 4-2. Correspondence of Pipeline Stage to Interlock and Exception Condition Stage Status Interlock Stall ITM ICM DTM DCM DCB Slip LDI MDI SLI CP0 Exception IAErr NMI ITLB IPErr INTr IBE SYSC BP Cun RSVD Trap OVF DAErr Reset DTLB TMod DPErr WAT DBE IF RF EX DC WB Remark In the above table, exception conditions are listed up in higher priority order. 110 CHAPTER 4 VR4102 PIPELINE Table 4-3. Description of Pipeline Exception Exception IAErr NMI ITLB IPErr INTr IBE SYSC BP CUn RSVD Trap OVF DAErr Reset DTLB DTMod DPErr WAT DBE Description Instruction Address Error exception Non-maskable Interrupt exception ITLB exception Instruction Parity Error exception Interrupt exception Instruction Bus Error exception System Call exception Breakpoint exception Coprocessor Unusable exception Reserved Instruction exception Trap exception Overflow exception Data Address Error exception Reset exception DTLB exception DTLB Modified exception Data Parity Error exception Watch exception Data Bus Error exception Table 4-4. Pipeline Interlock Interlock ITM ICM LDI MDI SLI CP0 DTM DCM DCB Interrupt TLB Miss Interrupt Cache Miss Load Data Interlock MD Busy Interlock Store-Load Interlock Coprocessor 0 Interlock Data TLB Miss Data Cache Miss Data Cache Busy Description 111 CHAPTER 4 VR4102 PIPELINE 4.5.1 Exception Conditions When an exception condition occurs, the relevant instruction and all those that follow it in the pipeline are cancelled. Accordingly, any stall conditions and any later exception conditions that may have referenced this instruction are inhibited; there is no benefit in servicing stalls for a cancelled instruction. When an exceptional conditions is detected for an instruction, the VR4102 will kill it and all following instructions. When this instruction reaches the WB stage, the exception flag and various information items are written to CP0 registers. The current PC is changed to the appropriate exception vector address and the exception bits of earlier pipeline stages are cleared. This implementation allows all preceding instructions to complete execution and prevents all subsequent instructions from completing. Thus the value in the EPC is sufficient to restart execution. It also ensures that exceptions are taken in the order of execution; an instruction taking an exception may itself be killed by an instruction further down the pipeline that takes an exception in a later cycle. Figure 4-12. Exception Detection Ecxeption 1 2 1I 2I 1R 1I 2R 2I 1E 2E 1D 2D 1W 2W EX1 EX2 DC1 DC2 WB1 1R 2R 1E 2E 1D 2D 1W 2W RF1 RF2 EX1 EX2 DC1 DC2 WB1 1I IF1 2I IF2 1R 2R 1E 2E 1D 2D 1W 2W RF1 RF2 EX1 EX2 DC1 DC2 WB1 1F 2F 1R 2R 1E 2E 1D 2D 1W 2W Exception vector : Killed stage : Interpret 112 CHAPTER 4 VR4102 PIPELINE 4.5.2 Stall Conditions Stalls are used to stop the pipeline for conditions detected after the RF stage. When a stall occurs, the processor will resolve the condition and then the pipeline will continue. Figure 4-13 shows a data cache miss stall, and Figure 4-14 shows a CACHE instruction stall. Figure 4-13. Data Cache Miss Stall IF RF EX DC WB 1 WB 2 DC EX RF WB WB WB 3 IF RF IF EX RF IF DC EX RF DC EX RF DC EX RF DC EX RF WB DC EX WB DC WB 1 2 3 Detect data cache miss Start moving data cache line to write buffer Get last word into cache and restart pipeline If the cache line to be replaced is dirty * the W bit is set * the data is moved to the internal write buffer in the next cycle. The write-back data is returned to memory. The last word in the data is returned to the cache at 3, and pipelining restarts. Figure 4-14. CACHE Instruction Stall IF RF EX DC WB 1 IF RF IF EX RF IF DC EX RF DC EX RF DC EX RF DC EX RF WB WB WB WB 2 DC EX RF WB DC EX WB DC WB 1 2 CACHE instruction start CACHE instruction complete When the CACHE instruction enters the DC pipe-stage, the pipeline stalls while the CACHE instruction is executed. The pipeline begins running again when the CACHE instruction is completed, allowing the instruction fetch to proceed. 113 CHAPTER 4 VR4102 PIPELINE 4.5.3 Slip Conditions During )2 of the RF stage and )1 of the EX stage, internal logic will determine whether it is possible to start the current instruction in this cycle. If all of the source operands are available (either from the register file or via the internal bypass logic) and all the hardware resources necessary to complete the instruction will be available whenever required, then the instruction "run"; otherwise, the instruction will "slip". Slipped instructions are retired on subsequent cycles until they issue. The backend of the pipeline (stages DC and WB) will advance normally during slips in an attempt to resolve the conflict. NOPs will be inserted into the bubble in the pipeline. Instructions killed by branch likely instructions, ERET or exceptions will not cause slips. Figure 4-15. Load Data Interlock Load A Load B IF RF IF EX RF DC EX WB DC WB Bypass ADD A, B IF RF RF EX DC WB 1 2 IF RF EX DC WB 1 2 Detect load interlock Get the target data Load Data Interlock is detected in the RF stage shown in as Figure 4-15 and also the pipeline slips in the stage. Load Data Interlock occurs when data fetched by a load instruction and data moved from HI, LO or CP0 register is required by the next immediate instruction. The pipeline begins running again when the clock after the target of the load is read from the data cache, HI, LO and CP0 register. The data returned at the end of the DC stage is input into the end of the RF stage, using the bypass multiplexers. Figure 4-16. MD Busy Interlock IF RF EX DC WB Bypass MFLO/MFHI IF RF RF EX DC WB 1 2 IF RF EX DC WB 1 2 Detect MD busy interlock Get target data 114 CHAPTER 4 VR4102 PIPELINE MD Busy Interlock is detected in the RF stage as shown in Figure 4-16 and also the pipeline slips in the stage. MD Busy Interlock occurs when Hi/Lo register is required by MFHi/Lo instruction before finishing Mult/Div execution. The pipeline begins running again the clock after finishing Mult/Div execution. The data returned from the Hi/Lo register at the end of the DC stage is input into the end of the RF stage, using the bypass multiplexers. Store-Load Interlock is detected in the EX stage and the pipeline slips in the RF stage. Store-Load Interlock occurs when store instruction followed by load instruction is detected. The pipeline begins running again one clock after. Coprocessor 0 Interlock is detected in the EX stage and the pipeline slips in the RF stage. A coprocessor interlock occurs when an MTC0 instruction for the Configuration or Status register is detected. The pipeline begins running again one clock after. 4.5.4 Bypassing In some cases, data and conditions produced in the EX, DC and WB stages of the pipeline are made available to the EX stage (only) through the bypass data path. Operand bypass allows an instruction in the EX stage to continue without having to wait for data or conditions to be written to the register file at the end of the WB stage. Instead, the Bypass Control Unit is responsible for ensuring data and conditions from later pipeline stages are available at the appropriate time for instructions earlier in the pipeline. The Bypass Control Unit is also responsible for controlling the source and destination register addresses supplied to the register file. 4.6 CODE COMPATIBILITY The VR4100 CPU core can execute all programs that can be executed in other VR-Series processors. But the reverse is not necessarily true. Programs complied using a standard MIPS compiler can be executed in both types of processors. When using manual assembly, however, write programs carefully so that compatibility with other VRseries processors can be maintained. Matters which should be paid attention to when porting programs between the VR4100 CPU core and other VR-Series processors are listed below. * The VR4100 CPU core does not support floating-point instructions since it has no Floating-Point Unit (FPU). * Multiply-add instructions (DMADD16, MADD16) are added in the VR4100 CPU core. * Instructions for power modes (HIBERNATE, STANDBY, SUSPEND) are added in the VR4100 CPU core support power modes. CPU core does not support instructions which manipulate the LL bit (LL, LLD, SC, SCD). to * The VR4100 CPU core does not have the LL bit to perform synchronization of multiprocessing. Therefore, the * The CP0 hazards of the VR4100 CPU core are equally or less stringent than those of other processors (see Chapter 28 for details). For more information, refer to Chapter 27, the VR4000, VR4400 User's Manual, or the VR4200 TM User's Manual. 115 [MEMO] 116 CHAPTER 5 MEMORY MANAGEMENT SYSTEM The VR4102 provides a memory management unit (MMU) which uses a translation lookaside buffer (TLB) to translate virtual addresses into physical addresses. This chapter describes the virtual and physical address spaces, the virtual-to-physical address translation, the operation of the TLB in making these translations, and the CP0 registers that provide the software interface to the TLB. 5.1 TRANSLATION LOOKASIDE BUFFER (TLB) Virtual addresses are translated into physical addresses using an on-chip TLB 22. The on-chip TLB is a fullyassociative memory that holds 32 entries, which provide mapping to 32 odd/even page pairs for one entry. The pages can have five different sizes, 1 K, 4 K, 16 K, 64 K, and 256 K, and can be specified in each entry. If it is supplied with a virtual address, each of the 32 TLB entries is checked simultaneously to see whether they match the virtual addresses that are provided with the ASID field and saved in the EntryHi register. If there is a virtual address match, or "hit," in the TLB, the physical page number is extracted from the TLB and concatenated with the offset to form the physical address. If no match occurs (TLB "miss"), an exception is taken and software refills the TLB from the page table resident in memory. The software writes to an entry selected using the Index register or a random entry indicated in the Random register. If more than one entry in the TLB matches the virtual address being translated, the operation is undefined and the TLB may be disabled. In this case, the TLB-Shutdown (TS) bit of the Status register is set to 1, and the TLB becomes unusable (an attempt to access the TLB results in a TLB Mismatch exception regardless of whether there is an entry that hits). The TS bit can be cleared only by a reset. Note that virtual addresses may be converted to physical addresses without using a TLB, depending on the address space that is being subjected to address translation. For example, address translation for the kseg0 or kseg1 address space does not use mapping. The physical addresses of these address spaces are determined by subtracting the base address of the address space from the virtual addresses. 5.2 VIRTUAL ADDRESS SPACE The address space of the CPU is extended in memory management system, by converting (translating) huge virtual memory addresses into physical addresses. The physical address space of the VR4102 is 4 Gbytes and 32-bit width addresses are used. For the virtual address space, up to 2 Gbytes (2 ) are provided as a user's area and 32-bit width addresses are used in the 32-bit mode. In the 64-bit mode, up to 1 Tbyte (2 ) is provided as a user's area and 64-bit width addresses are used. For the format of the TLB entry in each mode, refer to 5.4.1. As shown in Figures 4-2 and 4-3, the virtual address is extended with an address space identifier (ASID), which reduces the frequency of TLB flushing when switching contexts. This 8-bit ASID is in the CP0 EntryHi register, and the Global (G) bit is in the EntryLo0 and EntryLo1 registers, described later in this chapter. 40 31 117 CHAPTER 5 MEMORY MANAGEMENT SYSTEM Figure 5-1. Virtual-to-Physical Address Translation Virtual address 1 The virtual page number (VPN) in the virtual address (VA) is compared with the VPN in the TLB. ASID VPN Offset G 2 If there is a match, the page frame number (PFN) representing the highorder bits of the physical address is output from the TLB. ASID PFN VPN TLB entry TLB 3 The offset is then added to the PFN passing through the TLB. PFN Physical address Offset 5.2.1 Virtual-to-Physical Address Translation Converting a virtual address to a physical address begins by comparing the virtual address from the processor with the virtual addresses in the TLB; there is a match when the virtual page number (VPN) of the address is the same as the VPN field of the entry, and either: -- the Global (G) bit of the TLB entry is set to 1, or -- the ASID field of the virtual address is the same as the ASID field of the TLB entry. This match is referred to as a TLB hit. If there is no match, a TLB Mismatch exception is taken by the processor and software is allowed to refill the TLB from a page table of virtual/physical addresses in memory. If there is a virtual address match in the TLB, the physical address is output from the TLB and concatenated with the offset, which represents an address within the page frame space. The offset does not pass through the TLB. Instead, the low-order bits of the virtual address are output without being translated. See descriptions about the virtual address space for details. For details about the physical address, see 5.4.9 Virtual-to-Physical Address Translation. The next two sections describe the 32-bit and 64-bit mode address translations. 118 CHAPTER 5 MEMORY MANAGEMENT SYSTEM 5.2.2 32-bit Mode Address Translation Figure 5-2 shows the virtual-to-physical-address translation of a 32-bit mode address. The pages can have five different sizes between 1 Kbyte (10 bits) and 256 Kbytes (18 bits), each being 4 times as large as the preceding one in ascending order, that is 1 K, 4 K, 16 K, 64 K, and 256 K. -- Shown at the top of Figure 5-2 is the virtual address space in which the page size is 1 Kbyte and the offset is 10 bits. The 22 bits excluding the ASID field represents the virtual page number (VPN), enabling selecting a page table of 4 M entries. -- Shown at the bottom of Figure 5-2 is the virtual address space in which the page size is 256 Kbytes and the offset is 18 bits. The 14 bits excluding the ASID field represents the VPN, enabling selecting a page table of 16 K entries. Figure 5-2. 32-bit Mode Virtual Address Translation Virtual address for 4M (2 ) 1-Kbyte pages 39 ASID 8 32 31 29 28 VPN 22 22 bits = 4M pages Virtual-to-physical address translation with the TLB The offset is passed to physical address without being changed. 10 9 Offset 10 0 22 TLB Bits 31 to 29 of the virtual address select the user, supervisor, or kernel address space. 31 PFN Virtual-to-physical address translation with the TLB TLB Offset 0 The offset is passed to physical address without being changed. 39 ASID 8 32 31 29 28 VPN 14 18 17 0 Offset 18 14 14 bits = 16K pages Virtual address for 16K (2 ) 256-Kbyte pages 119 CHAPTER 5 MEMORY MANAGEMENT SYSTEM 5.2.3 64-bit Mode Address Translation Figure 5-3 shows the virtual-to-physical-address translation of a 64-bit mode address. The pages can have five different sizes between 1 Kbyte (10 bits) and 256 Kbytes (18 bits), each being 4 times as large as the preceding one in ascending order, that is 1K, 4K, 16K, 64K, and 256K. This figure illustrates the two possible page sizes: a 1Kbyte page (10 bits) and a 256-Kbyte page (18 bits). a Shown at the top of Figure 5-3 is the virtual address space in which the page size is 1 Kbyte and the offset is 10 bits. The 30 bits excluding the ASID field represents the virtual page number (VPN), enabling selecting a a Shown at the bottom of Figure 5-3 is the virtual address space in which the page size is 256 Kbytes and the offset is 18 bits. The 22 bits excluding the ASID field represents the VPN, enabling selecting a page table of 4 M entries. Figure 5-3. 64-bit Mode Virtual Address Translation Virtual address for 1G (2 ) 1-Kbyte pages 71 ASID 8 2 64 63 62 61 40 39 VPN 30 30 bits = 1G pages Virtual-to-physical address translation with the TLB TLB Bits 62 and 63 of the virtual address select the user, supervisor, or kernel address space. 31 PFN Virtual-to-physical address translation with the TLB TLB Offset The offset is passed to physical address without being changed. 10 9 Offset 10 0 30 page table of 1 G entry. 0 or -1 22 32-bit physical address 0 The offset is passed to physical address without being changed. 71 64 63 62 61 40 39 18 17 0 ASID 8 2 0 or -1 22 VPN 22 Offset 18 22 bits = 4M pages Virtual address for 4M (2 ) 256-Kbyte pages 22 120 CHAPTER 5 MEMORY MANAGEMENT SYSTEM 5.2.4 Operating Modes The processor has three operating modes that function in both 32- and 64-bit operations: a User mode a Supervisor mode a Kernel mode User and Kernel modes are common to all VR-Series processors. Generally, Kernel mode is used to executing the operating system, while User mode is used to run application programs. The VR4000 series processors have a third mode, which is called Supervisor mode and categorized in between User and Kernel modes. This mode is used to configure a high-security system. When an exception occurs, the CPU enters Kernel mode, and remains in this mode until an exception return instruction (ERET) is executed. The ERET instruction brings back the processor to the mode in which it was just before the exception occurs. These modes are described in the next three sections. 5.2.5 User Mode Virtual Addressing During the single user mode, a 2-Gbyte (2 bytes) virtual address space (useg) can be used in the 32-bit mode. In the 64-bit mode, a 1-Tbyte (2 bytes) virtual address space (xuseg) can be used. As shown in Tables 5-2 and 5-3, each virtual address is extended independently as another virtual address by setting an 8-bit address space ID area (ASID), to support user processes of up to 256. The contents of TLB can be retained after context switching by allocating each process by ASID. useg and xuseg can be referenced via TLB. Whether a cache is used or not is determined for each page by the TLB entry (depending on the C bit setting in the TLB entry). The User segment starts at address 0 and the current active user process resides in either useg (in 32-bit mode) or xuseg (in 64-bit mode). The TLB identically maps all references to useg/xuseg from all modes, and controls cache accessibility. The processor operates in User mode when the Status register contains the following bit-values: 40 31 a KSU = 10 a EXL = 0 a ERL = 0 In conjunction with these bits, the UX bit in the Status register selects 32- or 64-bit User mode addressing as follows: a When UX = 0, 32-bit useg space is selected. a When UX = 1, 64-bit xuseg space is selected. Table 5-1 lists the characteristics of each user segment (useg and xuseg). 121 CHAPTER 5 MEMORY MANAGEMENT SYSTEM Figure 5-4. User Mode Address Space 32-bit modeNote 0xFFFF FFFF Address error 0x8000 0000 0x7FFF FFFF 2 Gbytes with TLB mapping 0x0000 0000 useg 0x0000 0000 0000 0000 0x0000 0100 0000 0000 0x0000 00FF FFFF FFFF 1 Tbyte with TLB mapping xuseg 0xFFFF FFFF FFFF FFFF Address error 64-bit mode Note The VR4102 uses 64-bit addresses within it. When the processor is running in Kernel mode, it saves the contents of each register or restores their previous contents to initialize them before switching the context. For 32-bit mode addressing, bit 31 is sign-extended to bits 32 to 63, and the resulting 32 bits are used for addressing. Usually, it is impossible for 32-bit mode programs to generate invalid addresses. If context switching occurs and the processor enters Kernel mode, however, an attempt may be made to save an address other than the sign-extended 32-bit address mentioned above to a 64-bit register. In this case, user-mode programs are likely to generate an invalid address. Table 5-1. Comparison of useg and xuseg Address bit value 32-bit A[31] = 0 Status register bit value KSU 10 EXL 0 ERL 0 UX 0 Segment name useg 0x0000 0000 to 0x7FFF FFFF 0x0000 0000 0000 0000 to 0x0000 00FF FFFF FFFF 2 Gbytes 31 (2 bytes) Address range Size 64-bit A[63..40] = 0 10 0 0 1 xuseg 1 Tbyte 40 (2 bytes) 122 CHAPTER 5 MEMORY MANAGEMENT SYSTEM (1) useg (32-bit mode) In User mode, when UX = 0 in the Status register and the most significant bit of the virtual address is 0, User mode addressing is compatible with the 32-bit addressing model shown in Figure 5-4, and a 2-Gbyte user address space is available, labeled useg. Any attempt to reference an address with the most-significant bit set while in User mode causes an Address Error exception (see CHAPTER 6 EXCEPTION PROCESSING). The TLB Mismatch exception vector is used for TLB misses. (2) xuseg (64-bit mode) In User mode, when UX = 1 in the Status register and bits 63 to 40 of the virtual address are all 0, User mode addressing is extended to the 64-bit addressing model shown in Figure 5-4. In 64-bit User mode, the processor provides a single address space of 240 bytes, labeled xuseg. Any attempt to reference an address with bits 63:40 equal to 1 causes an Address Error exception (see CHAPTER 6 EXCEPTION PROCESSING). The XTLB Mismatch exception vector is used for TLB misses. 123 CHAPTER 5 MEMORY MANAGEMENT SYSTEM 5.2.6 Supervisor-mode Virtual Addressing Supervisor mode is designed for layered operating systems in which a true kernel runs in Kernel mode, and the rest of the operating system runs in Supervisor mode. All of the suseg, sseg, xsuseg, xsseg, and csseg spaces are referenced via TLB. Whether cache can be used or not is determined by bit C of each page's TLB entry. The processor operates in Supervisor mode when the Status register contains the following bit-values: -- KSU = 01 -- EXL = 0 -- ERL = 0 In conjunction with these bits, the SX bit in the Status register selects 32- or 64-bit Supervisor mode addressing: -- When SX = 0, 32-bit supervisor space is selected. -- When SX = 1, 64-bit supervisor space is selected. Table 5-2 lists the characteristics of the Supervisor mode segments. 124 CHAPTER 5 MEMORY MANAGEMENT SYSTEM Figure 5-5. Supervisor Mode Address Space 32-bit modeNote 0xFFFF FFFF 0xE000 0000 0xDFFF FFFF 0xC000 0000 0xBFFF FFFF Address error 0x8000 0000 0x7FFF FFFF 2 Gbytes with TLB mapping suseg 0x0000 0100 0000 0000 0x0000 00FF FFFF FFFF 0x0000 0000 0x0000 0000 0000 0000 1 Tbyte with TLB mapping xsuseg 0x4000 0100 0000 0000 0x4000 00FF FFFF FFFF 0x4000 0000 0000 0000 0x3FFF FFFF FFFF FFFF 1 Tbyte with TLB mapping xsseg Address error 0.5 Gbytes with TLB mapping 0xFFFF FFFF FFFF FFFF 0xFFFF FFFF E000 0000 0xFFFF FFFF DFFF FFFF sseg 0x0000 0010 0000 0000 0xFFFF FFFF C000 0000 0x0000 000F FFFF FFFF 0xFFFF FFFF BFFF FFFF 64-bit mode Address error 0.5 Gbytes with TLB mapping csseg Address error Address error Note The VR4102 uses 64-bit addresses within it. For 32-bit mode addressing, bit 31 is sign-extended to bits 32 to 63, and the resulting 32 bits are used for addressing. Usually, it is impossible for 32-bit mode programs to generate invalid addresses. In an operation of base register + offset for addressing, Note that the result however, a two's complement overflow may occur, causing an invalid address. becomes undefined. Two factors that can cause a two's complement follow: -- When offset bit 15 is 0, base register bit 31 is 0, and bit 31 of the operation "base register + offset" is 1 -- When offset bit 15 is 1, base register bit 31 is 1, and bit 31 of the operation "base register + offset" is 0 125 CHAPTER 5 MEMORY MANAGEMENT SYSTEM Table 5-2. 32-bit and 64-bit Supervisor Mode Segments Address bit value 32-bit A[31] = 0 Status register bit value KSU 01 EXL 0 ERL 0 SX 0 Segment name suseg 0x0000 0000 to 0x7FFF FFFF 0xC000 0000 to 0xDFFF FFFF 0x0000 0000 0000 0000 to 0x0000 00FF FFFF FFFF 0x4000 0000 0000 0000 to 0x4000 00FF FFFF FFFF 0xFFFF FFFF C000 0000 to 0xFFFF FFFF DFFF FFFF 2 Gbytes 31 (2 bytes) Address range Size 32-bit A[31..29] = 110 01 0 0 0 sseg 512 Mbytes 29 (2 bytes) 64-bit A[63..62] = 00 01 0 0 1 xsuseg 1 Tbyte 40 (2 bytes) 64-bit A[63..62] = 01 01 0 0 1 xsseg 1 Tbyte 40 (2 bytes) 64-bit A[63..62] = 11 01 0 0 1 csseg 512 Mbytes 29 (2 bytes) (1) suseg (32-bit Supervisor mode, user space) When SX = 0 in the Status register and the most-significant bit of the virtual address space is set to 0, the suseg virtual address space is selected; it covers 2 Gbytes (2 bytes) of the current user address space. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. This mapped space starts at virtual address 0x0000 0000 and runs through 0x7FFF FFFF. (2) sseg (32-bit Supervisor mode, supervisor space) When SX = 0 in the Status register and the three most-significant bits of the virtual address space are 110, the sseg virtual address space is selected; it covers 512 Mbytes (229 bytes) of the current supervisor virtual address space. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. This mapped space begins at virtual address 0xC000 0000 and runs through 0xDFFF FFFF. (3) xsuseg (64-bit Supervisor mode, user space) When SX = 1 in the Status register and bits 63 and 62 of the virtual address space are set to 00, the xsuseg virtual address space is selected; it covers 1 Tbyte (2 bytes) of the current user address space. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. This mapped space starts at virtual address 0x0000 0000 0000 0000 and runs through 0x0000 00FF FFFF FFFF. 40 31 126 CHAPTER 5 MEMORY MANAGEMENT SYSTEM (4) xsseg (64-bit Supervisor mode, current supervisor space) When SX = 1 in the Status register and bits 63 and 62 of the virtual address space are set to 01, the xsseg virtual address space is selected; it covers 1 Tbyte (2 bytes) of the current supervisor virtual address space. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. This mapped space begins at virtual address 0x4000 0000 0000 0000 and runs through 0x4000 00FF FFFF FFFF. (5) csseg (64-bit Supervisor mode, separate supervisor space) When SX = 1 in the Status register and bits 63 and 62 of the virtual address space are set to 11, the csseg virtual address space is selected; it covers 512 Mbytes (2 bytes) of the separate supervisor virtual address space. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. This mapped space begins at virtual address 0xFFFF FFFF C000 0000 and runs through 0xFFFF FFFF DFFF FFFF. 5.2.7 Kernel-mode Virtual Addressing If the Status register satisfies any of the following conditions, the processor runs in Kernel mode. -- KSU = 00 -- EXL = 1 -- ERL = 1 The addressing width in Kernel mode varies according to the state of the KX bit of the Status register, as follows: -- When KX = 0, 32-bit kernel space is selected. -- When KX = 1, 64-bit kernel space is selected. The processor enters Kernel mode whenever an exception is detected and it remains in Kernel mode until an exception return (ERET) instruction is executed and results in ERL and/or EXL = 0. The ERET instruction restores the processor to the mode existing prior to the exception. Kernel mode virtual address space is divided into regions differentiated by the high-order bits of the virtual address, as shown in Figure 5-6. Table 5-3 lists the characteristics of the 32-bit Kernel mode segments, and Table 5-4 lists the characteristics of the 64-bit Kernel mode segments. 29 40 127 CHAPTER 5 MEMORY MANAGEMENT SYSTEM Figure 5-6. Kernel Mode Address Space 32-bit modeNote 1 0xFFFF FFFF 0.5 Gbytes with TLB mapping 0xE000 0000 0xDFFF FFFF 0.5 Gbytes with TLB mapping 0xC000 0000 0xBFFF FFFF ksseg kseg3 0xFFFF FFFF FFFF FFFF 0xFFFF FFFF E000 0000 0xFFFF FFFF DFFF FFFF 0xFFFF FFFF C000 0000 0xFFFF FFFF BFFF FFFF 0xFFFF FFFF A000 0000 0.5 Gbytes without TLB mapping uncacheable 0.5 Gbytes without TLB mapping cacheable Note2 kseg1 0xFFFF FFFF 9FFF FFFF 0xFFFF FFFF 8000 0000 0xFFFF FFFF 7FFF FFFF kseg0 0xC000 00FF 8000 0000 0xC000 00FF 7FFF FFFF With TLB mapping 0xC000 0000 0000 0000 0xBFFF FFFF FFFF FFFF 0x8000 0000 0000 0000 2 Gbytes with TLB mapping kuseg 0x7FFF FFFF FFFF FFFF 0x4000 0100 0000 0000 0x4000 00FF FFFF FFFF 0x4000 0000 0000 0000 0x3FFF FFFF FFFF FFFF 0x0000 0100 0000 0000 0x0000 00FF FFFF FFFF 0x0000 0000 0x0000 0000 0000 0000 1 Tbyte with TLB mapping xkuseg 1 Tbyte with TLB mapping xksseg Without TLB mapping (See Table 5-7 for details.) 64-bit mode 0.5 Gbytes with TLB mapping 0.5 Gbytes with TLB mapping 0.5 Gbytes without TLB mapping uncacheable 0.5 Gbytes without TLB mapping cacheable Note 2 Address error ckseg cksseg ckseg1 ckseg0 0xA000 0000 0x9FFF FFFF 0x8000 0000 0x7FFF FFFF xkseg xkphys Address error Address error Notes 1. The VR4102 uses 64-bit addresses within it. For 32-bit mode addressing, bit 31 is sign-extended to bits 32 to 63, and the resulting 32 bits are used for addressing. Usually, a 64-bit instruction is used for the program in 32-bit mode. In an operation of base register + offset for addressing, however, a two's complement overflow may occur, causing an invalid address. Note that the result becomes undefined. Two factors that can cause a two's complement follow: -- When offset bit 15 is 0, base register bit 31 is 0, and bit 31 of the operation "base register + offset" is 1 -- When offset bit 15 is 1, base register bit 31 is 1, and bit 31 of the operation "base register + offset" is 0 2. The K0 field of the Config register controls cacheability of kseg0 and ckseg0. 128 CHAPTER 5 MEMORY MANAGEMENT SYSTEM Figure 5-7. xkphys Area Address Space 0xBFFF FFFF FFFF FFFF Address error 0xB800 0001 0000 0000 0xB800 0000 FFFF FFFF 0xB800 0000 0000 0000 0xB7FF FFFF FFFF FFFF 0xB000 0001 0000 0000 0xB000 0000 FFFF FFFF 0xB000 0000 0000 0000 0xAFFF FFFF FFFF FFFF 0xA800 0001 0000 0000 0xA800 0000 FFFF FFFF 0xA800 0000 0000 0000 0xA7FF FFFF FFFF FFFF 0xA000 0001 0000 0000 0xA000 0000 FFFF FFFF 0xA000 0000 0000 0000 0x9FFF FFFF FFFF FFFF 0x9800 0001 0000 0000 0x9800 0000 FFFF FFFF 0x9800 0000 0000 0000 0x97FF FFFF FFFF FFFF 0x9000 0001 0000 0000 0x9000 0000 FFFF FFFF 0x9000 0000 0000 0000 0x8FFF FFFF FFFF FFFF 0x8800 0001 0000 0000 0x8800 0000 FFFF FFFF 0x8800 0000 0000 0000 0x87FF FFFF FFFF FFFF 0x8000 0001 0000 0000 0x8000 0000 FFFF FFFF 0x8000 0000 0000 0000 4 Gbytes without TLB mapping cacheable Address error 4 Gbytes without TLB mapping cacheable Address error 4 Gbytes without TLB mapping cacheable 4 Gbytes without TLB mapping cacheable Address error 4 Gbytes without TLB mapping cacheable Address error 4 Gbytes without TLB mapping cacheable Address error 4 Gbytes without TLB mapping cacheable Address error 4 Gbytes without TLB mapping cacheable Address error 129 CHAPTER 5 MEMORY MANAGEMENT SYSTEM Table 5-3. 32-bit Kernel Mode Segments Address bit value Status register bit value KSU 32-bit A[31] = 0 EXL KSU = 00 or EXL = 1 or ERL = 1 ERL KX 0 Segment name kuseg 0x0000 0000 to 0x7FFF FFFF 0x8000 0000 to 0x9FFF FFFF 0xA000 0000 to 0xBFFF FFFF 32-bit A[31..29] = 110 0 ksseg 0xC000 0000 to 0xDFFF FFFF 0xE000 0000 to 0xFFFF FFFF Virtual address Physical address TLB map 2 Gbytes 31 (2 bytes) Size 32-bit A[31..29] = 100 0 kseg0 0x0000 0000 to 0x1FFF FFFF 0x0000 0000 to 0x1FFF FFFF TLB map 512 Mbytes 29 (2 bytes) 32-bit A[31..29] = 101 0 kseg1 512 Mbytes 29 (2 bytes) 512 Mbytes 29 (2 bytes) 32-bit A[31..29] = 111 0 kseg3 TLB map 512 Mbytes 29 (2 bytes) (1) kuseg (32-bit Kernel mode, user space) When KX = 0 in the Status register, and the most-significant bit of the virtual address space is 0, the kuseg virtual address space is selected; it is the current 2-Gbyte (2 -byte) user address space. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. References to kuseg are mapped through TLB. Whether cache can be used or not is determined by bit C of each page's TLB entry. If the ERL bit of the Status register is 1, the user address space is assigned 2 Gbytes (2 bytes) without TLB mapping and becomes unmapped (with virtual addresses being used as physical addresses) and uncached so that the cache error handler can use it. This allows the Cache Error exception code to operate uncached using r0 as a base register. (2) kseg0 (32-bit Kernel mode, kernel space 0) When KX = 0 in the Status register and the most-significant three bits of the virtual address space are 100, the kseg0 virtual address space is selected; it is the current 512-Mbyte (2 -byte) physical space. References to kseg0 are not mapped through TLB; the physical address selected is defined by subtracting 0x8000 0000 from the virtual address. The K0 field of the Config register controls cacheability (see CHAPTER 6 EXCEPTION PROCESSING). 29 31 31 130 CHAPTER 5 MEMORY MANAGEMENT SYSTEM (3) kseg1 (32-bit Kernel mode, kernel space 1) When KX = 0 in the Status register and the most-significant three bits of the virtual address space are 101, the kseg1 virtual address space is selected; it is the current 512-Mbyte (2 -byte) physical space. References to kseg1 are not mapped through TLB; the physical address selected is defined by subtracting 0xA000 0000 from the virtual address. Caches are disabled for accesses to these addresses, and main memory (or memory-mapped I/O device registers) is accessed directly. (4) ksseg (32-bit Kernel mode, supervisor space) When KX = 0 in the Status register and the most-significant three bits of the virtual address space are 110, the ksseg virtual address space is selected; it is the current 512-Mbyte (2 -byte) virtual address space. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. References to ksseg are mapped through TLB. Whether cache can be used or not is determined by bit C of each page's TLB entry. (5) kseg3 (32-bit Kernel mode, kernel space 3) When KX = 0 in the Status register and the most-significant three bits of the virtual address space are 111, the kseg3 virtual address space is selected; it is the current 512-Mbyte (2 -byte) kernel virtual space. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. References to kseg3 are mapped through TLB. Whether cache can be used or not is determined by bit C of each page's TLB entry. 29 29 29 131 CHAPTER 5 MEMORY MANAGEMENT SYSTEM Table 5-4. 64-bit Kernel Mode Segments Address bit value 64-bit A[63..62] = 00 Status register bit value KSU EXL ERL KX 1 Segment name xkuseg 0x0000 0000 0000 0000 to 0x0000 00FF FFFF FFFF 0x4000 0000 0000 0000 to 0x4000 00FF FFFF FFFF 0x8000 0000 0000 0000 to 0xBFFF FFFF FFFF FFFF 0xC000 0000 0000 0000 to 0xC000 00FF 7FFF FFFF 0xFFFF FFFF 8000 0000 to 0xFFFF FFFF 9FFF FFFF 0xFFFF FFFF A000 0000 to 0xFFFF FFFF BFFF FFFF 0xFFFF FFFF C000 0000 to 0xFFFF FFFF DFFF FFFF 0xFFFF FFFF E000 0000 to 0xFFFF FFFF FFFF FFFF Virtual address Physical address TLB map 1 Tbyte 40 (2 bytes) Size 64-bit A[63..62] = 01 KSU = 00 or EXL = 1 or ERL = 1 1 xksseg TLB map 1 Tbyte 40 (2 bytes) 64-bit A[63..62] = 10 1 xkphys 0x0000 0000 to 0xFFFF FFFF TLB map 4 Gbytes 32 (2 bytes) 64-bit A[63..62] = 11 1 xkseg 40 31 2 -2 bytes 64-bit A[63..62] = 11 A[63..31] = -1 64-bit A[63..62] = 11 A[63..31] = -1 64-bit A[63..62] = 11 A[63..31] = -1 64-bit A[63..62] = 11 A[63..31] = -1 1 ckseg0 0x0000 0000 to 0x1FFF FFFF 0x0000 0000 to 0x1FFF FFFF TLB map 512 Mbytes 29 (2 bytes) 1 ckseg1 512 Mbytes 29 (2 bytes) 1 cksseg 512 Mbytes 29 (2 bytes) 1 ckseg3 TLB map 512 Mbytes 29 (2 bytes) (6) xkuseg (64-bit Kernel mode, user space) When KX = 1 in the Status register and bits 63 and 62 of the virtual address space are 00, the xkuseg virtual address space is selected; it is the 1-Tbyte (240 bytes) current user address space. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. References to xkuseg are mapped through TLB. Whether cache can be used or not is determined by bit C of each page's TLB entry. If the ERL bit of the Status register is 1, the user address space is assigned 2 Gbytes (2 bytes) without TLB mapping and becomes unmapped (with virtual addresses being used as physical addresses) and uncached so that the cache error handler can use it. This allows the Cache Error exception code to operate uncached using r0 as a base register. (7) xksseg (64-bit Kernel mode, current supervisor space) When KX = 1 in the Status register and bits 63 and 62 of the virtual address space are 01, the xksseg address space is selected; it is the 1-Tbyte (240 bytes)current supervisor address space. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. References to xksseg are mapped through TLB. Whether cache can be used or not is determined by bit C of each page's TLB entry. 31 132 CHAPTER 5 MEMORY MANAGEMENT SYSTEM (8) xkphys (64-bit Kernel mode, physical spaces) When the KX = 1 in the Status register and bits 63 and 62 of the virtual address space are 10, the virtual address space is called xkphys and selected as either cached or uncached. If any of bits 58 to 32 of the address is 1, an attempt to access that address results in an address error. Whether cache can be used or not is determined by bits 59 to 61 of the virtual address. Table 5-5 shows cacheability corresponding to 8 address spaces. Table 5-5. Cacheability and the xkphys Address Space Bits 61-59 0 Cacheability Cached Start address 0x8000 0000 0000 0000 to 0x8000 0000 FFFF FFFF 0x8800 0000 0000 0000 to 0x8800 0000 FFFF FFFF 0x9000 0000 0000 0000 to 0x9000 0000 FFFF FFFF 0x9800 0000 0000 0000 to 0x9800 0000 FFFF FFFF 0xA000 0000 0000 0000 to 0xA000 0000 FFFF FFFF 0xA800 0000 0000 0000 to 0xA800 0000 FFFF FFFF 0xB000 0000 0000 0000 to 0xB000 0000 FFFF FFFF 0xB800 0000 0000 0000 to 0xB800 0000 FFFF FFFF 1 Cached 2 Uncached 3 Cached 4 Cached 5 Cached 6 Cached 7 Cached (9) xkseg (64-bit Kernel mode, physical spaces) When the KX = 1 in the Status register and bits 63 and 62 of the virtual address space are 11, the virtual address space is called xkseg and selected as either of the following: * kernel virtual space, xkseg, the current kernel virtual space; the virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address References to xkseg are mapped through TLB. Whether cache can be used or not is determined by bit C of each page's TLB entry. * one of the four 32-bit kernel compatibility spaces, as described in the next section. 133 CHAPTER 5 MEMORY MANAGEMENT SYSTEM (10) 64-bit Kernel mode compatible spaces (ckseg0, ckseg1, cksseg, and ckseg3) If the conditions listed below are satisfied in Kernel mode, ckseg0, ckseg1, cksseg, or ckseg3 (each having 512 Mbytes) is selected as a compatible space according to the state of the bits 30 and 29 (two low-order bits) of the address. -- The KX bit of the Status register is 1. -- Bits 63 and 62 of the 64-bit virtual address are 11. -- Bits 61 to 31 of the virtual address are all 1. (i) ckseg0 This space is an unmapped region, compatible with the 32-bit mode kseg0 space. The K0 field of the Config register controls cacheability and coherency. (ii) ckseg1 This space is an unmapped and uncached region, compatible with the 32-bit mode kseg1 space. (iii) cksseg This space is the current supervisor virtual space, compatible with the 32-bit mode ksseg space. References to cksseg are mapped through TLB. Whether cache can be used or not is determined by bit C of each page's TLB entry. (iv) ckseg3 This space is the current supervisor virtual space, compatible with the 32-bit mode kseg3 space. References to ckseg3 are mapped through TLB. Whether cache can be used or not is determined by bit C of each page's TLB entry. 134 CHAPTER 5 MEMORY MANAGEMENT SYSTEM 5.3 PHYSICAL ADDRESS SPACE Using a 32-bit address, the processor physical address space encompasses 4 Gbytes. The VR4102 uses this 4Gbyte physical address space as shown in Figure 5-8. Figure 5-8. VR4102 Physical Address Space 0xFFFF FFFF 0x2000 0000 0x1FFF FFFF (Mirror Image of 0x0000 0000 to 0x1FFF FFFF A) ROM Area (Include Boot ROM) 0x1800 0000 0x17FF FFFF System Bus I/O Area (ISA-IO) 0x1400 0000 0x13FF FFFF System Bus I/O Area (ISA-MEM) 0x1000 0000 0x0FFF FFFF RFU 0x0D00 0000 0x0CFF FFFF Internal I/O Area 1 0x0C00 0000 0x0BFF FFFF Internal I/O Area 2 0x0B00 0000 0x0AFF FFFF LCD/High-Speed System Bus Area 0x0A00 0000 0x09FF FFFF RFU 0x0400 0000 0x03FF FFFF DRAM Area 0x0000 0000 135 CHAPTER 5 MEMORY MANAGEMENT SYSTEM Table 5-6. VR4102 Physical Address Space Physical address 0xFFFF FFFF to 0x2000 0000 0x1FFF FFFF to 0x1800 0000 0x17FF FFFF to 0x1400 0000 0x13FF FFFF to 0x1000 0000 0x0FFF FFFF to 0x0D00 0000 0x0CFF FFFF to 0x0C00 0000 0x0BFF FFFF to 0x0B00 0000 0x0AFF FFFF to 0x0A00 0000 0x09FF FFFF to 0x0400 0000 0x03FF FFFF to 0x0000 0000 Space Mirror image of 0x1FFF FFFF to 0x0000 0000 ROM space System bus I/O space (ISA-IO) System bus memory space (ISA-MEM) Space reserved for future use Internal I/O space 1 Internal I/O space 2 LCD/high-speed system bus memory space Space reserved for future use DRAM space Capacity (bytes) 3.5 G 128 M 64 M 64 M 48 M 16 M 16 M 16 M 96 M 64 M 136 CHAPTER 5 MEMORY MANAGEMENT SYSTEM 5.3.1 ROM Space The ROM space differs depending on the data bus' bit width and the capacity of the ROM being used. * The data bus' bit width is set via the DBUS32 pin. * The ROM capacity is set via the BCUNTREG1's ROM64 bit. The physical addresses of the ROM space are listed below. Table 5-7. ROM Addresses (when using 16-bit data bus) Physical address ADD[25:0] pin When using 32-M ROM Bank 3 (ROMCS[3]#) When using 64-M ROM Bank 3 (ROMCS[3]#) 0x1FFF FFFF to 0x1FC0 0000 0x3FF FFFF to 0x3C0 0000 0x1FBF FFFF to 0x1F80 0000 0x3BF FFFF to 0x380 0000 0x1F7F FFFF to 0x1F40 0000 0x37F FFFF to 0x340 0000 0x33F FFFF to 0x300 0000 Bank 2 (ROMCS[2]#) Bank 1 (ROMCS[1]#) Bank 2 (ROMCS[2]#) 0x1F3F FFFF to 0x1F00 0000 Bank 0 (ROMCS[0]#) 0x1EFF FFFF to 0x1E80 0000 0x2FF FFFF to 0x280 0000 0x1E7F FFFF to 0x1E00 0000 0x27F FFFF to 0x200 0000 0x1DFF FFFF to 0x1800 0000 0x1FF FFFF to 0x000 0000 ROM space reserved for future use Bank 1 (ROMCS[1]#) Bank 0 (ROMCS[0]#) ROM space reserved for future use Table 5-8. ROM Addresses (when using 32-bit data bus) Physical address 0x1FFF FFFF to 0x1F80 0000 ADD[25:0] pin 0x3FF FFFF to 0x380 0000 0x37F FFFF to 0x300 0000 When using 32-Mbit ROM Bank 1 (ROMCS[1]#) When using 64-Mbit ROM Bank 1 (ROMCS[1]#) 0x1F7F FFFF to 0x1F00 0000 Bank 0 (ROMCS[0]#) 0x1EFF FFFF to 0x1E00 0000 0x2FF FFF0 to 0x200 0000 0x1DFF FFFF to 0x1800 0000 0x1FF FFFF to 0x000 0000 ROM space reserved for future use Bank 0 (ROMCS[0]#) ROM space reserved for future use 137 CHAPTER 5 MEMORY MANAGEMENT SYSTEM 5.3.2 System Bus Space The following three types of system bus space are available. * System bus I/O space This corresponds to the ISA's I/O space. * System bus memory space This corresponds to the ISA's memory space. * High-speed system bus memory space The access speed can be set independently of the system bus memory space. There are 16 Mbytes of high-speed system bus memory space. Therefore, the ADD[25:24] pin is fixed as 10. When system bus memory has been accessed from the high-speed system bus memory space, the LCDCS# pin becomes active. The high-speed system bus memory space is used exclusively from the LCD space. To switch between these two types of space, set the ISAM/LCD bit in BCUCNTREG1. 138 CHAPTER 5 MEMORY MANAGEMENT SYSTEM 5.3.3 Internal I/O Space The VR4102 has two internal I/O spaces. Each of these spaces are described below. Table 5-9. Internal I/O Space 1 Physical address 0x0CFF FFFF to 0x0C00 0060 0x0C00 005F to 0x0C00 0040 0x0C00 003F to 0x0C00 0020 0x0C00 001F to 0x0C00 0000 Internal I/O Reserved for future use FIR HSP (Software modem interface) SIU (16550) Table 5-10. Internal I/O Space 2 Physical address 0x0BFF FFFF to 0x0B00 02C0 0x0B00 02BF to 0x0B00 02A0 0x0B00 029F to 0x0B00 0280 0x0B00 027F to 0x0B00 0260 0x0B00 025F to 0x0B00 0240 0x0B00 023F to 0x0B00 0220 0x0B00 021F to 0x0B00 0200 0x0B00 01FF to 0x0B00 01E0 0x0B00 01DF to 0x0B00 01C0 0x0B00 01BF to 0x0B00 01A0 0x0B00 019F to 0x0B00 0180 0x0B00 017F to 0x0B00 0160 0x0B00 015F to 0x0B00 0140 0x0B00 013F to 0x0B00 0120 0x0B00 011F to 0x0B00 0100 0x0B00 00FF to 0x0B00 00E0 0x0B00 00DF to 0x0B00 00C0 0x0B00 00BF to 0x0B00 00A0 0x0B00 009F to 0x0B00 0080 0x0B00 007F to 0x0B00 0060 0x0B00 005F to 0x0B00 0040 0x0B00 003F to 0x0B00 0020 0x0B00 001F to 0x0B00 0000 Internal I/O Reserved for future use PIU2 Reserved for future use A/D test LED Reserved for future use ICU2 Reserved for future use RTC2 DSIU KIU1 AIU Reserved for future use PIU1 GIU1 DSU RTC1 PMU ICU1 CMU DCU DMAAU BCU 139 CHAPTER 5 MEMORY MANAGEMENT SYSTEM 5.3.4 LCD Space This space is used to access the external LCD controller. All data that is accessed via this space is inverted-bit data. The LCD space is used exclusively from the high-speed system bus memory space. To switch between these two types of space, set the ISAM/LCD bit in BCUCNTREG1. 5.3.5 DRAM Space The DRAM space differs depending on the data bus' bit width and the capacity of the DRAM being used. * The data bus' bit width is set via the DBUS32 pin. * The DRAM capacity is set via the BCUCNTREG1's DRAM64 bit. The physical addresses of the DRAM space are listed below. Table 5-11. DRAM Addresses (when using 16-bit data bus) Physical address 0x03FF FFFF to 0x0200 0000 0x01FF FFFF to 0x0180 0000 0x017F FFFF to 0x0100 0000 0x00FF FFFF to 0x0080 0000 0x007F FFFF to 0x0060 0000 0x005F FFFF to 0x0040 0000 0x003F FFFF to 0x0020 0000 0x001F FFFF to 0x0000 0000 Bank 3 (MRAS[3]#/UUCAS#) Bank 2 (MRAS[2]#/ULCAS#) Bank 1 (MRAS[1]#) Bank 0 (MRAS[0]#) When using 16-Mbit DRAM DRAM space reserved for future use When using 64-Mbit DRAM DRAM space reserved for future use Bank 3 (MRAS[3]#/UUCAS#) Bank 2 (MRAS[2]#/ULCAS#) Bank 1 (MRAS[1]#) Bank 0 (MRAS[0]#) Table 5-12. DRAM Addresses (when using 32-bit data bus) Physical address 0x03FF FFFF to 0x0200 0000 0x01FF FFFF to 0x0180 0000 0x017F FFFF to 0x0100 0000 0x00FF FFFF to 0x0080 0000 0x007F FFFF to 0x0060 0000 0x005F FFFF to 0x0040 0000 0x003F FFFF to 0x0020 0000 0x001F FFFF to 0x0000 0000 Bank 0 (MRAS[0]#) Bank 1 (MRAS[1]#) Bank 0 (MRAS[0]#) When using 16-Mbit DRAM DRAM space reserved for future use When using 64-Mbit DRAM DRAM space reserved for future use Bank 1 (MRAS[1]#) 140 CHAPTER 5 MEMORY MANAGEMENT SYSTEM 5.4 SYSTEM CONTROL COPROCESSOR The System Control Coprocessor (CP0) is implemented as an integral part of the CPU, and supports memory management, address translation, exception handling, and other privileged operations. CP0 contains the registers shown in Figure 5-9 plus a 32-entry TLB. The sections that follow describe how the processor uses each of the memory management-related registers. Remark Each CP0 register has a unique number that identifies it; this number is referred to as the register number. See Chapter 1 for details. Also see Chapter 6 for the CP0 functions and the relationships between exception processing and registers. Figure 5-9. CP0 Registers and the TLB EntryHi 10* EntryLo0 2* EntryLo1 3* Index 0* Random 1* PageMask 5* Wired 6* Context 4* Count 9* Status 12* EPC 14* WatchHi 19* Parity Error 26* BadVAddr 8* Compare 11* Cause 13* WatchLo 18* XContext 20* Cache Error 27* ErrorEPC 30* 31 TLB (Safe entries) (See Random register for the TLB Wired boundary.) 0 127/255 LLAddr 17* TagLo 28* 0 PRId 15* Config 16* TagHi 29* Used for memory management Used for exception processing Remark *: Register number Caution When accessing the CP0 register, some instructions require consideration of the interval time until the next instruction is executed, because it takes a while from when the contents of the CP0 register change to when this change is reflected on the CPU operation. This time lag is called CP0 hazard. For details, see Chapter 28. 141 CHAPTER 5 MEMORY MANAGEMENT SYSTEM 5.4.1 Format of a TLB Entry Figure 5-10 shows the TLB entry formats for both 32- and 64-bit modes. Each field of an entry has a corresponding field in the EntryHi, EntryLo0, EntryLo1, or PageMask registers. Figure 5-10. Format of a TLB Entry (a) 32-bit mode 127 0 13 95 VPN2 21 63 60 59 PFN 22 28 27 PFN 22 6 5 C 3 115 114 MASK 8 75 74 73 72 G 1 0 2 107 106 0 11 71 ASID 8 35 34 33 32 C 3 3 D 1 2 D 1 V 1 1 V 1 0 1 0 0 1 64 96 38 37 0 4 31 0 4 (b) 64-bit mode 255 0 45 191 190 189 R 2 127 0 36 63 0 36 28 27 PFN 22 0 22 92 91 PFN 22 6 5 C 3 168 167 VPN2 29 211 210 MASK 8 139 138 137 136 135 G 1 203 202 0 11 128 ASID 8 67 66 65 64 C 3 3 D 1 2 D 1 V 1 1 V 1 0 1 0 0 1 192 0 2 70 69 The format of the EntryHi, EntryLo0, EntryLo1, and PageMask registers are nearly the same as the TLB entry. However, it is unknown what bit of the EntryHi register corresponds to the TLB G bit. 142 CHAPTER 5 MEMORY MANAGEMENT SYSTEM Figure 5-11. Format of a TLB Entry (1/2) (a) PageMask Register 31 0 13 19 18 MASK 8 11 10 0 11 0 MASK : Page comparison mask, which determines the virtual page size for the corresponding entry. 0 : Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read. (b) EntryHi Register (a) 32-bit mode 31 VPN2 21 11 10 0 3 8 7 ASID 8 0 (b) 64-bit mode 63 R 2 62 61 Fill 22 40 39 VPN2 29 11 10 0 3 8 7 ASID 8 0 VPN2: Virtual page number divided by two (mapping to two pages) ASID : Address space ID. An 8-bit ASID field that lets multiple processes share the TLB; each process has a distinct mapping of otherwise identical virtual page numbers. R Fill 0 : Space type (00 o user, 01 o supervisor, 11 o kernel). Matches bits 63 and 62 of the virtual address. : Reserved. Ignored on write. When read, returns zero. : Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read. 143 CHAPTER 5 MEMORY MANAGEMENT SYSTEM Figure 5-11. Format of a TLB Entry (2/2) (c) EntryLo0 and EntryLo1 Registers (a) 32-bit mode 31 EntryLo0 0 4 31 EntryLo1 0 4 28 27 PFN 22 28 27 PFN 22 6 5 C 3 6 5 C 3 3 3 2 D 1 2 D 1 1 V 1 1 V 1 0 G 1 0 G 1 (b) 64-bit mode 63 EntryLo0 0 36 63 EntryLo1 28 27 PFN 22 28 27 PFN 22 6 5 C 3 6 5 C 3 3 3 2 D 1 2 D 1 1 V 1 1 V 1 0 G 1 0 G 1 0 36 PFN : Page frame number; high-order bits of the physical address. C D V G 0 : Specifies the TLB page attribute. : Dirty. If this bit is set to 1, the page is marked as dirty and, therefore, writable. This bit is actually a write-protect bit that software can use to prevent alteration of data. : Valid. If this bit is set to 1, it indicates that the TLB entry is valid; otherwise, a TLB Invalid exception (TLBL or TLBS) occurs. : Global. If this bit is set in both EntryLo0 and EntryLo1, then the processor ignores the ASID during TLB lookup. : Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read. The coherency attribute (C) bits are used to specify whether to use the cache in referencing a page. When the cache is used, whether the page attribute is "cached" or "uncached" is selected by algorithm. Table 5-13 lists the page attributes selected according to the value in the C bits. 144 CHAPTER 5 MEMORY MANAGEMENT SYSTEM Table 5-13. Cache Algorithm C bit value 0 1 2 3 4 5 6 7 Cached Cached Uncached Cached Cached Cached Cached Cached Cache algorithm 145 CHAPTER 5 MEMORY MANAGEMENT SYSTEM 5.5 CP0 REGISTERS The CP0 registers explained below are accessed by the memory management system and software. parenthesized number that follows each register name is a register number. 5.5.1 Index Register (0) The Index register is a 32-bit, read/write register containing five bits to index an entry in the TLB. The mostsignificant bit of the register shows the success or failure of a TLB probe (TLBP) instruction. The Index register also specifies the TLB entry affected by TLB read (TLBR) or TLB write index (TLBWI) instructions. Figure 5-12. Index Register 31 30 P 1 0 26 5 4 Index 5 0 A P : Indicates whether probing is successful or not. It is set to 1 if the latest TLBP instruction fails. It is cleared to 0 when the TLBP instruction is successful. Index : Specifies an index to a TLB entry that is a target of the TLBR or TLBWI instruction. 0 : Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read. 5.5.2 Random Register (1) The Random register is a read-only register. The low-order 5 bits are used in referencing a TLB entry. This register is decremented each time an instruction is executed. The values that can be set in the register are as follows: -- The lower bound is the content of the Wired register. -- The upper bound is 31. The Random register specifies the entry in the TLB that is affected by the TLBWR instruction. The register is readable to verify proper operation of the processor. The Random register is set to the value of the upper bound upon Cold Reset. This register is also set to the upper bound when the Wired register is written. Figure 5-13 shows the format of the Random register. Figure 5-13. Random Register 31 5 4 Random 5 0 0 27 Random : TLB random index 0 : Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read. 146 CHAPTER 5 MEMORY MANAGEMENT SYSTEM 5.5.3 EntryHi (10), EntryLO0 (2), EntryLO1 (3), and PageMask (5) Registers These registers are used in address translation, to rewrite TLB or to find match of TLB entry. When a TLB exception occurs, the information of the address that causes the exception is loaded into these registers. For the formats of these registers, see Figure 5-11. (1) EntryHi Register (10) The EntryHi register is read/write-accessible. It is used to access the high-order bits of built-in TLB. The EntryHi register holds the high-order bits of a TLB entry for TLB read and write operations. If a TLB Mismatch, TLB Invalid, or TLB Modified exception occurs, the EntryHi register sets the virtual page number (VPN2) for a virtual address where an exception occurred and the ASID. See Chapter 6 for details of the TLB exception. The ASID is used to read from or write to the ASID field of the TLB entry. It is also checked with the ASID of the TLB entry as the ASID of the virtual address during address translation. The EntryHi register is accessed by the TLBP, TLBWR, TLBWI, and TLBR instructions. (2) EntryLo0 (2) and EntryLo1 (3) Registers The EntryLo register consists of two registers that have identical formats: EntryLo0, used for even virtual pages and EntryLo1, used for odd virtual pages. The EntryLo0 and EntryLo1 registers are both read-/write-accessible. They are used to access the low-order bits of the built-in TLB. When a TLB read/write operation is carried out, the EntryLo0 and EntryLo1 registers hold the contents of the low-order 32 bits of TLB entries at even and odd addresses, respectively. (3) PageMask Register (5) The PageMask register is a read/write register used for reading from or writing to the TLB; it holds a comparison mask that sets the five types of page sizes for each TLB entry, as shown in Table 5-14. Page sizes must be from 1 Kbyte to 256 Kbytes. TLB read and write instructions use this register as either a source or a destination; Bits 18 to 11 that are targets of comparison are masked during address translation. Table 5-14 lists the mask pattern for each page size. If the mask pattern is one not listed below, the TLB behaves unexpectedly. Table 5-14. Mask Values and Page Sizes Page size 18 1 Kbyte 4 Kbytes 16 Kbytes 64 Kbytes 256 Kbytes 0 0 0 0 1 17 0 0 0 0 1 16 0 0 0 1 1 15 0 0 0 1 1 Bit 14 0 0 1 1 1 13 0 0 1 1 1 12 0 1 1 1 1 11 0 1 1 1 1 147 CHAPTER 5 MEMORY MANAGEMENT SYSTEM 5.5.4 Wired Register (6) The Wired register is a read/write register that specifies the lower boundary of the random entry of the TLB as shown in Figure 5-14. Wired entries cannot be overwritten by a TLBWR instruction. They can, however, be overwritten by a TLBWI instruction. Random entries can be overwritten by both instructions. Figure 5-14. Positions Indicated by the Wired Register 31 Range specified by the Random register Value in the Wired register Range of Wired entries 0 The Wired register is set to 0 upon Cold Reset. Writing this register also sets the Random register to the value of its upper bound (see 5.5.2 Random register (1)). Figure 5-15 shows the format of the Wired register. Figure 5-15. Wired Register 31 0 27 5 4 Wired 5 0 Wired : TLB wired boundary 0 : Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read. 148 CHAPTER 5 MEMORY MANAGEMENT SYSTEM 5.5.5 Processor Revision Identifier (PRId) Register (15) The 32-bit, read-only Processor Revision Identifier (PRId) register contains information identifying the implementation and revision level of the CPU and CP0. Figure 5-16 shows the format of the PRId register. Figure 5-16. PRId Register 31 0 16 16 15 Imp 8 8 7 Rev 8 0 Imp : CPU core processor ID number (0x0C for the VR4102) Rev : CPU core processor revision number 0 : Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read. The processor revision number is stored as a value in the form y.x, where y is a major revision number in bits 7 to 4 and x is a minor revision number in bits 3 to 0. The processor revision number can distinguish some CPU core revisions, however there is no guarantee that changes to the CPU core will necessarily be reflected in the PRId register, or that changes to the revision number necessarily reflect real CPU core changes. Therefore, create a program that does not depend on the processor revision number area. 149 CHAPTER 5 MEMORY MANAGEMENT SYSTEM 5.5.6 Config Register (16) The Config register indicates and specifies various configuration options selected on VR4102 processors. Some configuration options, as defined by the EC and BE fields, are set by the hardware during Cold Reset and are included in the Config register as read-only status bits for the software to access. Other configuration options (AD, EP, and K0 fields) can be read/written and controlled by software; on Cold Reset these fields are undefined. Since only a subset of the VR4000 options are available in the VR4102, some bits are set to constants (e.g., bits 14:13) that were variable in the VR4000. The Config register should be initialized by software before caches are used. Figure 5-17 shows the format of the Config register. Figure 5-17. Config Register Format 31 30 0 1 EC 3 28 27 EP 4 24 23 22 AD 1 0 5 18 17 16 15 14 13 12 11 1 1 0 BE 1 1 1 1 0 1 CS 1 IC 3 98 65 DC 3 0 3 32 K0 3 0 EC : System interface clock ratio (read only) 000 o Processor clock frequency divided by 2 Others o Reserved EP : Transfer data pattern (cache write-back pattern) 0000 o DD: 1 word/1 cycle Others o Reserved AD : Accelerate data mode setting 0 o VR4000 Series compatible mode 1 o Reserved BE : BigEndianMem. Indicates endian. 0 o Little endian 1 o Reserved CS : Cache size mode indication 0 o Reserved 1 o Cache of small capacity IC : Instruction cache size indication. The size is 2 2 o 4 Kbytes Others o Reserved DC : Data cache size indication. The size is 2 0 o 1 Kbytes Others o Reserved K0 : kseg0 cache coherency algorithm 010 o Uncached Others o Cached 1: 1 is returned when it is read. 0: 0 is returned when it is read. (10+DC) (10+IC) bytes when CS bit is set to 1. bytes when CS bit is set to 1. 150 CHAPTER 5 MEMORY MANAGEMENT SYSTEM Caution The value that can be set is different from that of the VR4100. Be sure to set the EP field and the AD bit to 0. If they are set with any other values, the processor may behave unexpectedly. 5.5.7 Load Linked Address (LLAddr) Register (17) The read/write Load Linked Address (LLAddr) register is a read/write register, and not used with the V R4102 processor except for diagnostic purpose, and serves no function during normal operation. LLAddr register is implemented just for compatibility between the VR4102 and VR4000/VR4400. Figure 5-18. LLAddr Register 31 PAddr 32 0 PAddr: 32-bit physical address 151 CHAPTER 5 MEMORY MANAGEMENT SYSTEM 5.5.8 Cache Tag Registers (TagLo (28) and TagHi (29)) The TagLo and TagHi registers are 32-bit read/write registers that hold the primary cache tag and parity during cache initialization, cache diagnostics, or cache error processing. The Tag registers are written by the CACHE and MTC0 instructions. The P fields of these registers are ignored on Index Store Tag operations by the CACHE instruction. Parity is computed by the store operation. Figure 5-19 shows the format of these registers. Figure 5-19. TagLo and TagHi Registers 31 Data cache PTagLo 22 10 9 V 1 8 D 1 7 W 1 6 0 5 2 1 0 W' P 1 1 31 Instruction cache PTagLo 22 31 Tag Hi 0 32 10 9 V 1 8 0 8 1 0 P 1 0 PTagLo: Specifies physical address bits 31 to 10. V D : Valid bit : Dirty bit. However, this bit is defined only for the compatibility with the VR4000 Series processors, and does not indicate the status of cache memory in spite of its readability and writability. This bit cannot change the status of cache memory. W W' P 0 : Write-back bit (set if cache line has been updated) : Even parity for the write-back bit : Even parity bit for primary cache tag : Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read. 152 CHAPTER 5 MEMORY MANAGEMENT SYSTEM 5.5.9 Virtual-to-Physical Address Translation During virtual-to-physical address translation, the CPU compares the 8-bit ASID (and while the Global bit, G, is not set to 1) of the virtual address to the ASID of the TLB entry to see if there is a match. One of the following comparisons are also made: -- In 32-bit mode, the high-order bits -- In 64-bit mode, the high-order bits Note of the 32-bit virtual address are compared to the contents of the VPN2 of the 64-bit virtual address are compared to the contents of the R and (virtual page number divided by two) of each TLB entry. Note the VPN2 (virtual page number divided by two) of each TLB entry. If a TLB entry matches, the physical address and access control bits (C, D, and V) are retrieved from the matching TLB entry. While the V bit of the entry must be set to 1 for a valid address translation to take place, it is not involved in the determination of a matching TLB entry. Figure 5-20 illustrates the TLB address translation flow. Note The number of bits differs from page sizes. The table below shows the examples of high-order bits of the virtual address in page size of 256 Kbytes and 1 Kbytes. Page size Mode 32-bit mode 64-bit mode 256 Kbytes 1 Kbytes bits 31 to 19 bits 63, 62, 39 to 19 bits 31 to 11 bits 63, 62, 39 to 11 153 CHAPTER 5 MEMORY MANAGEMENT SYSTEM Figure 5-20. TLB Address Translation Virtual address (input) VPN and ASID Address error Exception No Legal address? Yes Yes User mode? No Yes Supervisor mode? No Legal address? Yes No Address error Exception Address error Exception No Legal address? Yes No Mapped address? Yes VPN match? Yes No Global No G = 1? ASID match? Yes No Yes Valid No V = 1? Yes Dirty 32-bit address? Yes No TLB Modified Exception Yes No Write? No D = 1? Yes Yes No Uncached area? TLB Invalid Exception TLB Mismatch Exception XTLB Mismatch Exception Access main memory Physical address (output) Access cache memory 154 CHAPTER 5 MEMORY MANAGEMENT SYSTEM 5.5.10 TLB Misses If there is no TLB entry that matches the virtual address, a TLB Refill (miss) exception occurs bit is 010, the retrieved physical address directly accesses main memory, bypassing the cache. Note See Chapter 6 for details of the TLB Miss exception. 5.5.11 TLB Instructions The instructions used for TLB control are described below. (1) Translation lookaside buffer probe (TLBP) The translation lookaside buffer probe (TLBP) instruction loads the Index register with a TLB number that matches the content of the EntryHi register. If there is no TLB number that matches the TLB entry, the highestorder bit of the Index register is set. (2) Translation lookaside buffer read (TLBR) The translation lookaside buffer read (TLBR) instruction loads the EntryHi, EntryLo0, EntryLo1, and PageMask registers with the content of the TLB entry indicated by the content of the Index register. (3) Translation lookaside buffer write index (TLBWI) The translation lookaside buffer write index (TLBWI) instruction writes the contents of the EntryHi, EntryLo0, EntryLo1, and PageMask registers to the TLB entry indicated by the content of the Index register. (4) Translation lookaside buffer write random (TLBWR) The translation lookaside buffer write random (TLBWR) instruction writes the contents of the EntryHi, EntryLo0, EntryLo1, and PageMask registers to the TLB entry indicated by the content of the Random register. Note . If the access control bits (D and V) indicate that the access is not valid, a TLB Modified or TLB Invalid exception occurs. If the C 155 [MEMO] 156 CHAPTER 6 EXCEPTION PROCESSING This chapter describes CPU exception processing, including an explanation of hardware that processes exceptions, followed by the format and use of each CPU exception register. The chapter concludes with a description of each exception's cause, together with the manner in which the CPU processes and services each exception. 6.1 HOW EXCEPTION PROCESSING WORKS The processor receives exceptions from a number of sources, including translation lookaside buffer (TLB) misses, arithmetic overflows, I/O interrupts, and system calls. When the CPU detects an exception, the normal sequence of instruction execution is suspended and the processor enters Kernel mode (see Chapter 5 for a description of system operating modes). The processor then disables interrupts and transfers control for execution to the exception handler (located at a specific address as an exception handling routine implemented by software). The handler saves the context of the processor, including the contents of the program counter, the current operating mode (User or Supervisor), statuses, and interrupt enabling. This context is saved so it can be restored when the exception has been serviced. When an exception occurs, the CPU loads the Exception Program Counter (EPC) register with a location where execution can restart after the exception has been serviced. The restart location in the EPC register is the address of the instruction that caused the exception or, if the instruction was executing in a branch delay slot, the address of the branch instruction immediately preceding the delay slot. The VR4102 processor supports a Supervisor mode and fast TLB refill for all address spaces. The VR4102 also provides the following functions: -- Interrupt enable (IE) bit -- Operating mode (User, Supervisor, or Kernel) -- Exception level (normal or exception is indicated by the EXL bit in the Status register) -- Error level (normal or error is indicated by the ERL bit in the Status register). Interrupts are enabled when the following conditions are satisfied: (1) Interrupt enable An interrupt is enabled when the following conditions are satisfied. x Interrupt enable bit (IE) = 1 x EXL bit = 0, ERL bit = 0 x Corresponding IM field bits in the Status register = 1 157 CHAPTER 6 EXCEPTION PROCESSING (2) Operating mode The operating mode is specified by KSU bit in the Status register when both the exception level and error level are normal (0). (3) Exception/error levels The operation enters Kernel mode when either EXL bit or ERL bit in the Status register is set to 1. Returning from an exception resets the exception level to normal (0) (for details, see Chapter 27). The registers that retain address, cause, and status information during exception processing are described in 6.3 EXCEPTION PROCESSING REGISTERS. For a description of the exception process, see 6.4 DETAILS OF EXCEPTIONS. 6.2 PRECISION OF EXCEPTIONS VR4102 exceptions are logically precise; the instruction that causes an exception and all those that follow it are aborted and can be re-executed after servicing the exception. When succeeding instructions are killed, exceptions associated with those instructions are also killed. Exceptions are not taken in the order detected, but in instruction fetch order. There is a special case in which the VR4102 processor may not be able to restart easily after servicing an exception. When a cache data parity error exception occurs on a load with a cache hit, the VR4102 processor does not prevent the cache data (with erroneous parity) from being written back into the register file during the WB stage. The exception is still precise, since both the EPC and CacheError registers are updated with the correct virtual address pointing to the offending load instruction, and the exception handler can still determine the cause of exception and its origin. The program can be restarted by rewriting the destination register - not automatically, however, as in the case of all the other precise exceptions where no status change occurs. 158 CHAPTER 6 EXCEPTION PROCESSING 6.3 EXCEPTION PROCESSING REGISTERS This section describes the CP0 registers that are used in exception processing. Table 6-1 lists these registers, along with their number-each register has a unique identification number that is referred to as its register number. The CP0 registers not listed in the table are used in memory management (see Chapter 5 for details). The exception handler examines the CP0 registers during exception processing to determine the cause of the exception and the state of the CPU at the time the exception occurred. The registers in Table 6-1 are used in exception processing, and are described in the sections that follow. Table 6-1. CP0 Exception Processing Registers Register name Context register BadVAddr register Count register Compare register Status register Cause register EPC register WatchLo register WatchHi register XContext register Parity Error register Cache Error register ErrorEPC register Register number 4 8 9 11 12 13 14 18 19 20 26 27 30 159 CHAPTER 6 EXCEPTION PROCESSING 6.3.1 Context Register (4) The Context register is a read/write register containing the pointer to an entry in the page table entry (PTE) array on the memory; this array is a table that stores virtual-to-physical address translations. When there is a TLB miss, the operating system loads the unsuccessfully translated entry from the PTE array to the TLB. The Context register is used by the TLB Refill exception handler for loading TLB entries. The Context register duplicates some of the information provided in the BadVAddr register, but the information is arranged in a form that is more useful for a software TLB exception handler. Figure 6-1 shows the format of the Context register. Figure 6-1. Context Register Format (a) 32-bit mode 31 PTEBase 7 25 24 BadVPN2 21 4 3 0 4 0 (b) 64-bit mode 63 PTEBase 39 25 24 BadVPN2 21 4 3 0 0 4 PTEBase : The PTEBase field is a read/write field. It is used by software as the pointer to the base address of the PTE table in the current user address space. BadVPN2 : The BadVPN2 field is written by hardware if a TLB miss occurs. This field holds the value (VPN2) obtained by halving the virtual page number of the most recent virtual address for which translation failed. 0 : Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read. The 21-bit BadVPN2 field contains bits 31-11 of the virtual address that caused the TLB miss; bit 10 is excluded because a single TLB entry maps to an even-odd page pair. For a 1-Kbyte page size, this format can directly address the pair-table of 8-byte PTEs. When the page size is 4 Kbytes or more, shifting or masking this value produces the correct PTE reference address. 160 CHAPTER 6 EXCEPTION PROCESSING 6.3.2 BadVAddr Register (8) The Bad Virtual Address (BadVAddr) register is a read-only register that saves the most recent virtual address that failed to have a valid translation, or that had an addressing error. Figure 6-2 shows the format of the BadVAddr register. Caution This register saves no information after a bus error exception, because it is not an address error exception. Figure 6-2. BadVAddr Register Format (a) 32-bit mode 31 BadVAddr 32 0 (b) 64-bit mode 63 0 (b) BadVAddr 64-bit mode 64 BadVAddr: Most recent virtual address for which an addressing error occurred, or for which address translation failed 6.3.3 Count Register (9) The read/write Count register acts as a timer. It is incremented in synchronization with the MasterOut clock, regardless of whether instructions are being executed, retired, or any forward progress is actually made through the pipeline. This register is a free-running type. When the register reaches all ones, it rolls over to zero and continues counting. This register is used for self-diagnostic test, system initialization, or the establishment of inter-process synchronization. Figure 6-3 shows the format of the Count register. Figure 6-3. Count Register Format 31 Count 32 0 Count: 32-bit up-date count value that is compared with the value of the Compare register 161 CHAPTER 6 EXCEPTION PROCESSING 6.3.4 Compare Register (11) The Compare register causes a timer interrupt; it maintains a stable value that does not change on its own. When the value of the Count register (see 6.3.3) equals the value of the Compare register, the IP(7) bit in the Cause register is set. This causes an interrupt as soon as the interrupt is enabled. Writing a value to the Compare register, as a side effect, clears the timer interrupt request. For diagnostic purposes, the Compare register is a read/write register. Normally, this register should be only used for a write. Figure 6-4 shows the format of the Compare register. Figure 6-4. Compare Register Format 31 Compare 32 0 Compare: Value that is compared with the count value of the Count register 6.3.5 Status Register (12) The Status register is a read/write register that contains the operating mode, interrupt enabling, and the diagnostic states of the processor. Figure 5-5 shows the format of the Status register. Figure 5-6 shows the details of the Diagnostic Status (DS) field. All DS field bits other than the TS bit are writable. Figure 6-5. Status Register Format 31 0 3 29 28 27 26 25 24 CU0 16 15 DS 9 IM (7:0) 8 8 7 6 5 4 3 2 1 0 IE 1 0 2 RE 1 KX SX UX 1 1 1 KSU 2 ERL EXL 1 1 1 CU0 0 RE DS IM : Enables/disables the use of the coprocessor (1 o Enabled, 0 o Disabled). CP0 can be used by the kernel at all times. : Reserved for future use. Write 0 in a write operation. When this bit is read, 0 is read. : Enables/disables reversing of the endian setting in User mode (0 o Disabled, 1 o Enabled). This bit must be set to 0 since the VR4102 supports the little-endian order only. : Diagnostic Status field (see Figure 6-6). : Interrupt Mask field used to enable/disable interrupts (0 o Disabled, 1 o Enabled). This field consists of 8 bits that are used to control eight interrupts. The bits are assigned to interrupts as follows: IM7 : Masks a timer interrupt. Note IM(6:2) : Mask ordinary interrupts (Int(4:0) ). However, Int4 Note never occur in the VR4102. IM(1:0) : Mask software interrupts or Cause register IP(1:0). Note Int(4:0) are internal signals of the VR4100 CPU core. For details about connection to the onchip peripheral units, refer to Chapter 14. 162 CHAPTER 6 EXCEPTION PROCESSING KX SX UX: KSU ERL EXL IE : Enables 64-bit addressing in Kernel mode (0 o 32-bit, 1 o 64-bit). If this bit is set, an XTLB Refill exception occurs if a TLB miss occurs in the Kernel mode address space. : Enables 64-bit addressing and operation in Supervisor mode (0 o 32-bit, 1 o 64-bit). If this bit is set, an XTLB Refill exception occurs if a TLB miss occurs in the Supervisor mode address space. : Enables 64-bit addressing and operation in User mode (0 o 32-bit, 1 o 64-bit). If this bit is set, an XTLB Refill exception occurs if a TLB miss occurs in the User mode address space. : Sets and indicates the operating mode (10 o User, 01 o Supervisor, 00 o Kernel). : Sets and indicates the error level (0 o Normal, 1 o Error). : Sets and indicates the exception level (0 o Normal, 1 o Exception). : Sets and indicates interrupt enabling/disabling (0 o Disabled, 1 o Enabled). Figure 6-6. Status Register Diagnostic Status Field 24 0 2 23 22 BEV 1 21 TS 1 20 SR 1 19 0 1 18 CH 1 17 CE 1 16 DE 1 BEV TS : Specifies the base address of a TLB Refill exception vector and common exception vector (0 o Normal, 1 o Bootstrap). : Occurs the TLB to be shut down (read-only) (0 o Not shut down, 1 o Shut down). This bit is used to avoid any problems that may occur when multiple TLB entries match the same virtual address. After the TLB has been shut down, reset the processor to enable restart. Note that the TLB is shut down even if a TLB entry matching a virtual address is marked as being invalid (with the V bit cleared). SR CH CE DE 0 : Occurs a Soft Reset or NMI exception (0 o Not occurred, 1 o Occurred). : CP0 condition bit (0 o False, 1 o True). This bit can be read and written by software only; it cannot be accessed by hardware. : When CE = 1, the contents of the PErr register are written to the check bits of the cache (See 6.3.10) : Specifies whether a cache parity error causes an exception (0 o Enable parity check, 1 o Disable parity check). : Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read. The status register has the following fields where the modes and access status are set. 163 CHAPTER 6 EXCEPTION PROCESSING (1) Interrupt enable Interrupts are enabled when all of the following conditions are true: -- IE is set to 1. -- EXL is cleared to 0. -- ERL is cleared to 0. -- The appropriate bit of the IM is set to 1. (2) Operating modes The following Status register bit settings are required for User, Kernel, and Supervisor modes. -- The processor is in User mode when KSU = 10, EXL = 0, and ERL = 0. -- The processor is in Supervisor mode when KSU = 01, EXL = 0, and ERL = 0. -- The processor is in Kernel mode when KSU = 00, EXL = 1, or ERL = 1. (3) 32- and 64-bit modes The following Status register bit settings select 32- or 64-bit operation for User, Kernel, and Supervisor operating modes. Enabling 64-bit operation permits the execution of 64-bit opcodes and translation of 64-bit addresses. 64-bit operation for User, Kernel and Supervisor modes can be set independently. -- 64-bit addressing for Kernel mode is enabled when KX bit = 1. 64-bit operations are always valid in Kernel mode. -- 64-bit addressing and operations are enabled for Supervisor mode when SX bit = 1. -- 64-bit addressing and operations are enabled for User mode when UX bit = 1. (4) Kernel address space accesses Access to the kernel address space is allowed when the processor is in Kernel mode. (5) Supervisor address space accesses Access to the supervisor address space is allowed when the processor is in Supervisor or Kernel mode. (6) User address space accesses Access to the user address space is allowed in any of the three operating modes. (7) Status after reset The contents of the Status register are undefined after resets, except for the following bits. x x x TS and SR are cleared to 0. ERL and BEV are set to 1. SR is 0 after Cold reset, and is 1 after Soft reset or NMI interrupt. Cold reset and Soft reset are CPU core reset (see 7.4 RESET OF THE CPU CORE). For the reset of all the VR4102 including peripheral units, refer to CHAPTER 7 INITIALIZATION INTERFACE and CHAPTER 15 PMU. Remark 164 CHAPTER 6 EXCEPTION PROCESSING 6.3.6 Cause Register (13) The 32-bit read/write Cause register holds the cause of the most recent exception. A 5-bit exception code indicates one of the causes (see Table 6-2). Other bits holds the detailed information of the specific exception. All bits in the Cause register, with the exception of the IP1 and IP0 bits, are read-only; IP1 and IP0 are used for software interrupts. Figure 6-7 shows the fields of this register; Table 6-2 describes the Cause register codes. Figure 6-7. Cause Register Format 31 30 29 28 27 BD 1 0 1 CE 2 0 12 16 15 IP(7..0) 8 8 7 0 1 6 2 1 0 2 0 ExcCode 5 BD CE IP : Indicates whether the most recent exception occurred in the branch delay slot (1 In delay slot, 0 Normal). : Indicates the coprocessor number in which a Coprocessor Unusable exception occurred. This field will remain undefined for as long as no exception occurs. : Indicates whether an interrupt is pending (1 Interrupt pending, 0 No interrupt pending). IM7 IM(6:2) IM(1:0) : A timer interrupt. : Ordinary interrupts (Int(4:0) by means of software. Note Int(4:0) are internal signals of the VR4100 CPU core. For details about connection to the onchip peripheral units, refer to Chapter 14. Note ). However, Int4 Note never occurs in the VR4102. : Software interrupts. Only these bits cause an interrupt exception, when they are set to 1 ExcCode : Exception code field (refer to Table 6-2 for details) 0 : Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read. 165 CHAPTER 6 EXCEPTION PROCESSING Table 6-2. Cause Register Exception Code Field Exception code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 to 22 23 24 to 31 Int Mod TLBL TLBS AdEL AdES IBE DBE Sys Bp RI CpU Ov Tr * WATCH * Mnemonic Interrupt exception TLB Modified exception TLB Refill exception (load or fetch) TLB Refill exception (store) Address Error exception (load or fetch) Address Error exception (store) Bus Error exception (instruction fetch) Bus Error exception (data load or store) System Call exception Breakpoint exception Reserved Instruction exception Coprocessor Unusable exception Integer Overflow exception Trap exception Reserved for future use Watch exception Reserved for future use Description The VR4102 has eight interrupt request sources, IP7 to IP0. For the detailed description of interrupts, refer to Chapter 9. (1) IP7 This bit indicates whether there is a timer interrupt request. It is set when the values of Count register and Compare register match. (2) IP6 to IP2 IP6 to IP2 reflect the state of the interrupt request signal of the CPU core. (3) IP1 and IP0 These bits are used to set/clear a software interrupt request. 166 CHAPTER 6 EXCEPTION PROCESSING 6.3.7 Exception Program Counter (EPC) Register (14) The Exception Program Counter (EPC) is a read/write register that contains the address at which processing resumes after an exception has been serviced. The EPC register contains either: -- Virtual address of the instruction that was the direct cause of the exception -- Virtual address of the immediately preceding branch or jump instruction (when the instruction associated with the exception is in a branch delay slot, and the BD bit in the Cause register is set to 1). The EXL bit in the Status register is set to 1 to keep the processor from overwriting the address of the exceptioncausing instruction contained in the EPC register in the event of another exception. Figure 6-8 shows the format of the EPC register. Figure 6-8. EPC Register Format (a) 32-bit mode 31 0 EPC 32 (b) 64-bit mode 63 0 EPC 64 EPC: Restart address after exception processing 167 CHAPTER 6 EXCEPTION PROCESSING 6.3.8 WatchLo (18) and WatchHi (19) Registers The VR4102 processor provides a debugging feature to detect references to a selected physical address; load and store instructions to the location specified by the WatchLo and WatchHi registers cause a Watch exception. Figures 5-9 and 5-10 show the format of the WatchLo and WatchHi registers. Figure 5-9. WatchLo and WatchHi Register Format WatchLo Register 31 PAddr0 29 3 2 0 1 1 R 1 0 W 1 WatchHi Register 31 0 0 32 PAddr0 : Specifies physical address bits 31 to 3. R W 0 : If this bit is set to 1, an exception will occur when a load instruction is executed. : If this bit is set to 1, an exception will occur when a store instruction is executed. : Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read. 168 CHAPTER 6 EXCEPTION PROCESSING 6.3.9 XContext Register (20) The read/write XContext register contains a pointer to an entry in the page table entry (PTE) array, an operating system data structure that stores virtual-to-physical address translations. If a TLB miss occurs, the operating system loads the untranslated data from the PTE into the TLB to handle the software error. The XContext register is used by the XTLB Refill exception handler to load TLB entries in 64-bit addressing mode. The XContext register duplicates some of the information provided in the BadVAddr register, and puts it in a form useful for the XTLB exception handler. This register is included solely for operating system use. The operating system sets the PTEBase field in the register, as needed. Figure 6-10 shows the format of the XContext register. Figure 6-10. XContext Register Format 63 PTEBase 29 35 34 33 32 R 2 BadVPN2 29 4 3 0 4 0 PTEBase : The PTEBase field is a read/write field, and is used by software as the pointer to the base address of the PTE table in the current user address space. BadVPN2 : The BadVPN2 field is written by hardware if a TLB miss occurs. This field holds the value (VPN2) obtained by halving the virtual page number of the most recent virtual address for which translation failed. R 0 : Space type (00 o User, 01o Supervisor, 11 o Kernel). The setting of this field matches virtual address bits 63 and 62. : Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read. The 29-bit BadVPN2 field has bits 39 to 11 of the virtual address that caused the TLB miss; bit 10 is excluded because a single TLB entry maps to an even-odd page pair. For a 1-Kbyte page size, this format may be used directly to address the pair-table of 8-byte PTEs. For 4-Kbyte-or-more page and PTE sizes, shifting or masking this value produces the appropriate address. 169 CHAPTER 6 EXCEPTION PROCESSING 6.3.10 Parity Error Register (26) The read/write Parity Error (PErr) register contains the cache data parity bits for cache initialization, cache diagnostics, or cache error processing. The PErr register is loaded by the Index_Load_Tag CACHE instruction. All bits of the parity field are valid on the data cache operation because data cache employs byte parity (1-bit parity for 1 byte). But a LSB of the parity field is valid on the instruction cache operation because instruction cache employs word parity (1-bit parity for 1 word). The contents of the PErr register are: -- written into the on-chip data cache on store instructions (instead of the computed parity) when the CE bit of the Status register is set to 1 -- substituted for the computed parity for the CACHE Fill instruction In the VR4102, parity check is performed only for cache memory. It is not performed for main memory or peripheral units. Figure 6-11 shows the format of the PErr register. Figure 6-11. Parity Error Register Format 31 0 24 8 7 Parity 8 0 Parity : Specifies the 8-bit parity data to be read from or written to the on-chip cache. 0 : Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read. 170 CHAPTER 6 EXCEPTION PROCESSING 6.3.11 Cache Error Register (27) The 32-bit read/write Cache Error (CacheErr) register processes parity errors in the on-chip cache. Parity errors cannot be corrected by on-chip hardware. The CacheErr register holds cache index and status bits that indicate the cause of the error. In the VR4102, parity check is performed only for cache memory. It is not performed for main memory or peripheral units. Figure 6-12 shows the format of the CacheErr register. Figure 6-12. CacheErr Register Format 31 30 29 28 27 26 25 24 ER 11 10 0 14 PIdx 11 0 0 ED ET 0 EE EB 1111111 ER : Reference type (0 o Instruction, 1 o Data) ED : Indicates whether an error occurred in the data field (0 o Normal, 1 o Error). ET : Indicates whether an error occurred in the tag field (0 o Normal, 1 o Error). EE : This bit is set if an error occurs on the SysAD bus. EB : This bit is set if a data error occurs subsequent to an instruction error. (The error status is indicated by the remaining bit positions.) In this case, the data cache must be flushed upon the completion of instruction error processing. PIdx: Cache index 0 : Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read. 6.3.12 ErrorEPC Register (30) The Error Exception Program Counter (ErrorEPC) register is similar to the EPC register. It is used to store the Program Counter value at which the Cache Error, Cold Reset, Soft Reset, or NMI exception has been serviced. The read/write ErrorEPC register contains the virtual address at which instruction processing can resume after servicing an error. This address can be: -- the virtual address of the instruction that caused the error exception -- the virtual address of the immediately preceding branch or jump instruction, when the instruction associated with the error exception is in a branch delay slot. The contents of the ErrorEPC register do not change when the ERL bit of the Status register is set to 1. This prevents the processor when other exceptions occur from overwriting the address of the instruction in this register which causes an error exception. There is no branch delay slot indication for the ErrorEPC register. Figure 6-13 shows the format of the ErrorEPC register. 171 CHAPTER 6 EXCEPTION PROCESSING Figure 6-13. The ErrorEPC Register Format (a) 32-bit mode 31 ErrorEPC 32 0 (b) 64-bit mode 63 ErrorEPC 64 0 ErrorEPC: Restart address after parity error exception processing. Also indicates the value of the program counter when Cold reset, Soft reset, or NMI exceptions occurred. 172 CHAPTER 6 EXCEPTION PROCESSING 6.4 DETAILS OF EXCEPTIONS This section describes causes, processes, and services of the VR4102's exceptions. 6.4.1 Exception Types This section gives sample exception handler operations for the following exception types: -- Cold Reset -- Soft Reset -- NMI -- Cache error -- Remaining processor exceptions When the EXL and ERL bits in the Status register are 0, either User, Supervisor, or Kernel operating mode is specified by the KSU bits in the Status register. When either the EXL or ERL bit is set to 1, the processor is in Kernel mode. When the processor takes an exception, the EXL bit is set to 1, meaning the system is in Kernel mode. After saving the appropriate state, the exception handler typically resets the EXL bit back to 0. The exception handler sets the EXL bit to 1 so that the saved state is not lost upon the occurrence of another exception while the saved state is being restored. Returning from an exception also resets the EXL bit to 0. For details, see Chapter 27. 6.4.2 Exception Vector Locations The Cold Reset, Soft Reset, and NMI exceptions are always branched to the following reset exception vector address (virtual). This address is in an uncached, unmapped space. -- 0xBFC0 0000 in 32-bit mode -- 0xFFFF FFFF BFC0 0000 in 64-bit mode Addresses for the remaining exceptions are a combination of a vector offset and a base address. 64-/32-bit mode exception vectors and their offsets are shown below. 173 CHAPTER 6 EXCEPTION PROCESSING Table 6-3. 64-Bit Mode Exception Vector Base Addresses Vector base address (virtual) Cold Reset Soft Reset NMI Cache Error 0xFFFF FFFF BFC0 0000 (BEV is automatically set to 1) 0xFFFF FFFF A000 0000 (BEV = 0) 0xFFFF FFFF BFC0 0200 (BEV = 1) 0xFFFF FFFF 8000 0000 (BEV = 0) 0xFFFF FFFF BFC0 0200 (BEV = 1) 0x0100 Vector offset 0x0000 TLB Refill (EXL = 0) XTLB Refill (EXL = 1) Other exceptions 0x0000 0x0080 0x0180 Table 6-4. 32-Bit Mode Exception Vector Base Addresses Vector base address (virtual) Cold Reset Soft Reset NMI Cache Error 0xBFC0 0000 (BEV is automatically set to 1) 0xA000 0000 (BEV = 0) 0xBFC0 0200 (BEV = 1) 0x8000 0000 (BEV = 0) 0xBFC0 0200 (BEV = 1) 0x0100 Vector offset 0x0000 TLB Refill (EXL = 0) XTLB Refill (EXL = 1) Other exceptions 0x0000 0x0080 0x0180 Examples 1. TLB Refill Exception Vector When BEV bit = 0, the vector base address (virtual) for the TLB Refill exception is in kseg0 (unmapped) space. -- 0x8000 0000 in 32-bit mode -- 0xFFFF FFFF 8000 0000 in 64-bit mode When BEV bit = 1, the vector base address (virtual) for the TLB Refill exception is in kseg1 (uncached, unmapped) space. -- 0xBFC0 0200 in 32-bit mode -- 0xFFFF FFFF BFC0 0200 in 64-bit mode This is an uncached, non-TLB-mapped space, allowing the exception handler to bypass the cache and TLB. 174 CHAPTER 6 EXCEPTION PROCESSING Example 2. Cache Error Exception Vector When BEV bit = 0, the vector base address (virtual) for the Cache Error exception is in kseg1 (uncached, unmapped) space. -- 0xA000 0000 in 32-bit mode -- 0xFFFF FFFF A000 0000 in 64-bit mode When BEV bit = 1, the vector base address (virtual) for the Cache Error exception is in kseg1 (uncached, unmapped) space. -- 0xBFC0 0200 in 32-bit mode -- 0xFFFF FFFF BFC0 0200 in 64-bit mode This is an uncached, non-TLB-mapped space, allowing the exception handler to bypass the cache and TLB. 175 CHAPTER 6 EXCEPTION PROCESSING 6.4.3 Priority of Exceptions While more than one exception can occur for a single instruction, only the exception with the highest priority is reported. Table 6-5 lists the priorities. Table 6-5. Exception Priority Order Priority High n ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ p Low Cold Reset Soft Reset NMI Address Error (instruction fetch) TLB/XTLB Refill (instruction fetch) TLB Invalid (instruction fetch) Cache Error (instruction fetch) Bus Error (instruction fetch) System Call Breakpoint Coprocessor Unusable Reserved Instruction Trap Integer Overflow Address Error (data access) TLB/XTLB Refill (data access) TLB Invalid (data access) TLB Modified (data write) Cache Error (data access) Watch Bus Error (data access) Interrupt (other than NMI) Exceptions Hereafter, handling exceptions by hardware is referred to as "process", and handling exception by software is referred to as "service". 176 CHAPTER 6 EXCEPTION PROCESSING 6.4.4 Cold Reset Exception Cause The Cold Reset exception occurs when the ColdReset# signal (internal) is asserted and then deasserted. This exception is not maskable. The Reset# signal (internal) must be asserted along with the ColdReset# signal (for details, see Chapter 7). Processing The CPU provides a special interrupt vector for this exception: 0xBFC0 0000 (virtual) in 32-bit mode 0xFFFF FFFF BFC0 0000 (virtual) in 64-bit mode The Cold Reset vector resides in unmapped and uncached CPU address space, so the hardware need not initialize the TLB or the cache to process this exception. It also means the processor can fetch and execute instructions while the caches and virtual memory are in an undefined state. The contents of all registers in the CPU are undefined when this exception occurs, except for the following register fields: When ERL bit of the Status register is 0, the program counter's value at the exception occurrence is saved to the EPC register. TS and SR of the Status register are cleared to 0. ERL and BEV of the Status register are set to 1. The Random register is initialized to the value of its upper bound (31) (refer to 5.4.2 Random Register (1)). The Wired register is initialized to 0. Bits 31 to 28 of the Config register are set to 0, and bits 22 to 3 to 0x04800. All other bits are undefined. Servicing The Cold Reset exception is serviced by: Initializing all processor registers, coprocessor registers, TLB, caches, and the memory system Performing diagnostic tests Bootstrapping the operating system 177 CHAPTER 6 EXCEPTION PROCESSING 6.4.5 Soft Reset Exception Cause A Soft Reset (sometimes called Warm Reset) occurs when the ColdReset# signal remains deasserted while the Reset# signal goes from assertion to deassertion (for details, see Chapter 7). A Soft Reset immediately resets all state machines, and sets the SR bit of the Status register. Execution begins at the reset vector when the reset is deasserted. This exception is not maskable. Caution In the VR4102, a soft reset never occurs. Processing The CPU provides a special interrupt vector for this exception (same location as Cold Reset): 4 0xBFC0 0000 (virtual) in 32-bit mode 4 0xFFFF FFFF BFC0 0000 (virtual) in 64-bit mode This vector is located within unmapped and uncached address space, so that the cache and TLB need not be initialized to process this exception. The SR bit of the Status register is set to 1 to distinguish this exception from a Cold Reset exception. When this exception occurs, the contents of all registers are preserved except for the following registers: 4 When ERL bit of the Status register is 0, the program counter's value at the exception occurrence is saved to the EPC register. 4 TS bit of the Status register is cleared to 0. 4 ERL, SR, and BEV bits of the Status register are set to 1. During a soft reset, access to the operating cache or system interface is aborted. This means that the contents of the cache and memory will be undefined if a Soft Reset occurs. Servicing The Soft Reset exception is serviced by: 4 Preserving the current processor states for diagnostic tests 4 Reinitializing the system in the same way as for a Cold Reset exception 178 CHAPTER 6 EXCEPTION PROCESSING 6.4.6 NMI Exception Cause The Nonmaskable Interrupt (NMI) exception occurs in response to the input of the NMI signal (internal). This interrupt is not maskable; it occurs regardless of the settings of the EXL, ERL, and the IE bits in the Status register (for details, see Chapters 9 and 14). Processing The CPU provides a special interrupt vector for this exception: 4 0xBFC0 0000 (virtual) in 32-bit mode 4 0xFFFF FFFF BFC0 0000 (virtual) in 64-bit mode This vector is located within unmapped and uncached address space so that the cache and TLB need not be initialized to process an NMI interrupt. The SR bit of the Status register is set to 1 to distinguish this exception from a Cold Reset exception. Unlike Cold Reset and Soft Reset, but like other exceptions, NMI is taken only at instruction boundaries. The states of the caches and memory system are preserved by this exception. When this exception occurs, the contents of all registers are preserved except for the following registers: 4 When ERL bit of the Status register is 0, the program counter's value at the exception occurrence is saved to the EPC register. 4 The TS bit of the Status register is cleared to 0. 4 The ERL, SR, and BEV bits of the Status register are set to 1. Servicing The NMI exception is serviced by: 4 Preserving the current processor states for diagnostic tests 4 Reinitializing the system in the same way as for a Cold Reset exception 179 CHAPTER 6 EXCEPTION PROCESSING 6.4.7 Address Error Exception Cause The Address Error exception occurs when an attempt is made to execute one of the following. This exception is not maskable. Execution of the LW, LWU, SW, or CACHE instruction for word data that is not located on a word boundary Execution of the LH, LHU, or SH instruction for half-word data that is not located on a half-word boundary Execution the LD or SD instruction for double-word data that is not located on a double-word boundary Referencing the kernel address space in User or Supervisor mode Referencing the supervisor space in User mode Referencing an address that does not exist in the kernel, user, or supervisor address space in 64-bit Kernel, User, or Supervisor mode Branching to an address that is not located on a word boundary Processing The common exception vector is used for this exception. The AdEL or AdES code in the Cause register is set. If this exception has been caused by an instruction reference or load operation, AdEL is set. If it has been caused by a store operation, AdES is set. When this exception occurs, the BadVAddr register stores the virtual address that was not properly aligned or was referenced in protected address space. The contents of the VPN field of the Context and EntryHi registers are undefined, as are the contents of the EntryLo register. The EPC register contains the address of the instruction that caused the exception, unless this instruction is in a branch delay slot. If it is in a branch delay slot, the EPC register contains the address of the preceding branch instruction and the BD bit of the Cause register is set to 1. Servicing The kernel reports the UNIX is usually fatal. TM SIGSEGV (segmentation violation) signal to the current process, and this exception 180 CHAPTER 6 EXCEPTION PROCESSING 6.4.8 TLB Exceptions Three types of TLB exceptions can occur: TLB Refill exception occurs when there is no TLB entry that matches a referenced address. A TLB Invalid exception occurs when a TLB entry that matches a referenced virtual address is marked as being invalid (with the V bit set to 0). The TLB Modified exception occurs when a TLB entry that matches a virtual address referenced by the store instruction is marked as being valid (with the V bit set to 1). The following three sections describe these TLB exceptions. (1) TLB Refill Exception (32-bit Space Mode)/XTLB Refill Exception (64-bit Space Mode) Cause The TLB Refill exception occurs when there is no TLB entry to match a reference to a mapped address space. This exception is not maskable. Processing There are two special exception vectors for this exception; one for references to 32-bit address spaces, and one for references to 64-bit address spaces. The UX, SX, and KX bits of the Status register determine whether the user, supervisor or kernel address spaces referenced are 32-bit or 64-bit spaces. When the EXL bit of the Status register is set to 0, either of these two special vectors is referenced. When the EXL bit is set to 1, the common exception vector is referenced. This exception sets the TLBL or TLBS code in the ExcCode field of the Cause register. If this exception has been caused by an instruction reference or load operation, TLBL is set. If it has been caused by a store operation, TLBS is set. When this exception occurs, the BadVAddr, Context, XContext and EntryHi registers hold the virtual address that failed address translation. The EntryHi register also contains the ASID from which the translation fault occurred. The Random register normally contains a valid location in which to place the replacement TLB entry. contents of the EntryLo register are undefined. The EPC register contains the address of the instruction that caused the exception, unless this instruction is in a branch delay slot, in which case the EPC register contains the address of the preceding branch instruction and the BD bit of the Cause register is set to 1. Servicing To service this exception, the contents of the Context or XContext register are used as a virtual address to fetch memory words containing the physical page frame and access control bits for a pair of TLB entries. The memory word is written into the TLB entry by using the EntryLo0, EntryLo1, or EntryHi register. It is possible that the physical page frame and access control bits are placed in a page where the virtual address is not resident in the TLB. This condition is processed by allowing a TLB Refill exception in the TLB Refill exception handler. In this case, the common exception vector is used because the EXL bit of the Status register is set to 1. The 181 CHAPTER 6 EXCEPTION PROCESSING (2) TLB Invalid Exception Cause The TLB Invalid exception occurs when the TLB entry that matches with the virtual address to be referenced is invalid (the V bit is set to 0). This exception is not maskable. Processing The common exception vector is used for this exception. The TLBL or TLBS code in the ExcCode field of the Cause register is set. If this exception has been caused by an instruction reference or load operation, TLBL is set. If it has been caused by a store operation, TLBS is set. When this exception occurs, the BadVAddr, Context, Xcontext, and EntryHi registers contain the virtual address that failed address translation. The EntryHi register also contains the ASID from which the translation fault occurred. The Random register normally stores a valid location in which to place the replacement TLB entry. The contents of the EntryLo register are undefined. The EPC register contains the address of the instruction that caused the exception unless this instruction is in a branch delay slot, in which case the EPC register contains the address of the preceding branch instruction and the BD bit of the Cause register is set to 1. Servicing Usually, the V bit of a TLB entry is cleared in the following cases: When a virtual address does not exist When the virtual address exists, but is not in main memory (a page fault) When a trap is required on any reference to the page (for example, to maintain a reference bit) After servicing the cause of a TLB Invalid exception, the TLB entry is located with a TLBP (TLB Probe) instruction, and replaced by an entry with its Valid bit set to 1. 182 CHAPTER 6 EXCEPTION PROCESSING (3) TLB Modified Exception Cause The TLB Modified exception occurs when the TLB entry that matches with the virtual address referenced by the store instruction is valid (bit V is 1) but is not writable (bit D is 0). This exception is not maskable. Processing The common exception vector is used for this exception, and the Mod code in the ExcCode field of the Cause register is set. When this exception occurs, the BadVAddr, Context, Xcontext, and EntryHi registers contain the virtual address that failed address translation. The EntryHi register also contains the ASID from which the translation fault occurred. The contents of the EntryLo register are undefined. The EPC register contains the address of the instruction that caused the exception unless that instruction is in a branch delay slot, in which case the EPC register contains the address of the preceding branch instruction and the BD bit of the Cause register is set to 1. Servicing The kernel uses the failed virtual address or virtual page number to identify the corresponding access control bits. The page identified may or may not permit write accesses; if writes are not permitted, a write protection violation occurs. If write accesses are permitted, the page frame is marked dirty (/writable) by the kernel in its own data structures. The TLBP instruction places the index of the TLB entry that must be altered into the Index register. The word data containing the physical page frame and access control bits (with the D bit set to 1) is loaded to the EntryLo register, and the contents of the EntryHi and EntryLo registers are written into the TLB. 183 CHAPTER 6 EXCEPTION PROCESSING 6.4.9 Cache Error Exception Cause The Cache Error exception occurs when a cache parity error is detected. This exception is not maskable, but error detection can be disabled by setting the DE bit of the Status register. If a parity error is detected when the DE bit of Status register is not set, a cache error exception is taken during one of the following operations: An instruction fetch from instruction cache A load from the data cache Tag parity check on a store Main memory read by the processor Most of the CACHE instructions (no exception is taken for the Index_Load_Tag and Index_Store_Tag CACHE instructions) In the VR4102, the parity error from the external bus and on-chip peripheral buses is not checked. Processing The processor sets the ERL bit in the Status register, saves the address to recover from the exception to the ErrorEPC register, and then transfers to a special vector in uncached space. If the BEV bit = 0, the vector is one of the following: -- 0xA000 0100 (virtual) in 32-bit mode -- 0xFFFF FFFF A000 0100 (virtual) in 64-bit mode If the BEV bit = 1, the vector is one of the following: -- 0xBFC0 0300 (virtual) in 32-bit mode -- 0xFFFF FFFF BFC0 0300 (virtual) in 64-bit mode Servicing All errors should be logged. To correct cache parity errors, the system uses the CACHE instruction to invalidate the cache block, overwrites the old data through a cache miss, and resumes execution with an ERET instruction. Other errors are not correctable and are likely to be fatal to the current process. 184 CHAPTER 6 EXCEPTION PROCESSING 6.4.10 Bus Error Exception Cause A Bus Error exception is raised by board-level circuitry for events such as bus time-out, local bus parity errors, and invalid physical memory addresses or access types. This exception is not maskable. A Bus Error exception occurs only when a cache miss refill, uncached reference, or unbuffered write occurs synchronously. In other words, it occurs when an illegal access is detected during BCU read. For details of illegal accesses, refer to 10.4.6 Illegal Access Notification. Processing The common interrupt vector is used for a Bus Error exception. The IBE or DBE code in the ExcCode field of the Cause register is set, signifying whether the instruction caused the exception by an instruction reference, load operation, or store operation. The EPC register contains the address of the instruction that caused the exception, unless it is in a branch delay slot, in which case the EPC register contains the address of the preceding branch instruction and the BD bit of the Cause register is set to 1. Servicing The physical address at which the fault occurred can be computed from information available in the System Control Coprocessor (CP0) registers. If the IBE code in the Cause register is set (indicating an instruction fetch), the virtual address is contained in the EPC register (or 4 + the contents of the EPC register if the BD bit of the Cause register is set to 1). If the DBE code is set (indicating a load or store), the virtual address of the instruction that caused the exception (the address of the preceding branch instruction if the BD bit of the Cause register is set to 1) is saved to the EPC register (or 4 + the contents of the EPC register if the BD bit of the Cause register is set to 1). The virtual address of the load and store instruction can then be obtained by interpreting the instruction. The physical address can be obtained by using the TLBP instruction and reading the EntryLo register to compute the physical page number. At the time of this exception, the kernel reports the UNIX SIGBUS (bus error) signal to the current process, but the exception is usually fatal. 185 CHAPTER 6 EXCEPTION PROCESSING 6.4.11 System Call Exception Cause A System Call exception occurs during an attempt to execute the SYSCALL instruction. This exception is not maskable. Processing The common exception vector is used for this exception, and the Sys code in the ExcCode field of the Cause register is set. The EPC register contains the address of the SYSCALL instruction unless it is in a branch delay slot, in which case the EPC register contains the address of the preceding branch instruction. If the SYSCALL instruction is in a branch delay slot, the BD bit of the Status register is set to 1; otherwise this bit is cleared. Servicing When this exception occurs, control is transferred to the applicable system routine. To resume execution, the EPC register must be altered so that the SYSCALL instruction does not re-execute; this is accomplished by adding a value of 4 to the EPC register before returning. If a SYSCALL instruction is in a branch delay slot, interpretation of the branch instruction is required to resume execution. 6.4.12 Breakpoint Exception Cause A Breakpoint exception occurs when an attempt is made to execute the BREAK instruction. This exception is not maskable. Processing The common exception vector is used for this exception, and the BP code in the ExcCode field of the Cause register is set. The EPC register contains the address of the BREAK instruction unless it is in a branch delay slot, in which case the EPC register contains the address of the preceding branch instruction. If the BREAK instruction is in a branch delay slot, the BD bit of the Status register is set to 1; otherwise this bit is cleared. Servicing When the Breakpoint exception occurs, control is transferred to the applicable system routine. Additional distinctions can be made by analyzing the unused bits of the BREAK instruction (bits 25 to 6), and loading the contents of the instruction whose address the EPC register contains. A value of 4 must be added to the contents of the EPC register to locate the instruction if it resides in a branch delay slot. To resume execution, the EPC register must be altered so that the BREAK instruction does not re-execute; this is accomplished by adding a value of 4 to the EPC register before returning. If a BREAK instruction is in a branch delay slot, interpretation (decoding) of the branch instruction is required to resume execution. 186 CHAPTER 6 EXCEPTION PROCESSING 6.4.13 Coprocessor Unusable Exception Cause The Coprocessor Unusable exception occurs when an attempt is made to execute a coprocessor instruction for either: a corresponding coprocessor unit that has not been marked usable (Status register bit, CU[0] = 0), or CP0 instructions, when the unit has not been marked usable (Status register bit, CU[0] = 0) and the process executes in User or Supervisor mode. This exception is not maskable. Processing The common exception vector is used for this exception, and the CPU code in the ExcCode field of the Cause register is set. The CE bit of the Cause register indicates which of the four coprocessors was referenced. The EPC register contains the address of the coprocessor instruction that causes an exception unless it is in a branch delay slot, in which case the EPC register contains the address of the preceding branch instruction and the BD bit of the Cause register is set to 1. Servicing The coprocessor unit to which an attempted reference was made is identified by the CE bit of the Cause register. One of the following processing is performed by the handler: If the process is entitled access to the coprocessor, the coprocessor is marked usable and the corresponding state is restored to the coprocessor. If the process is entitled access to the coprocessor, but the coprocessor does not exist or has failed, interpretation of the coprocessor instruction is possible. If the BD bit in the Cause register is set to 1, the branch instruction must be interpreted; then the coprocessor instruction can be emulated and execution resumed with the EPC register advanced past the coprocessor instruction. If the process is not entitled access to the coprocessor, the kernel reports UNIX SIGILL/ILL_PRIVIN_FAULT (illegal instruction/privileged instruction fault) signal to the current process, and this exception is fatal. 187 CHAPTER 6 EXCEPTION PROCESSING 6.4.14 Reserved Instruction Exception Cause The Reserved Instruction exception occurs when an attempt is made to execute one of the following instructions: -- Instruction with an undefined major opcode (bits 31 to 26) -- SPECIAL instruction with an undefined minor opcode (bits 5 to 0) -- REGIMM instruction with an undefined minor opcode (bits 20 to 16) -- 64-bit instructions in 32-bit User or Supervisor mode 64-bit operations are always valid in Kernel mode regardless of the value of the KX bit in the Status register. This exception is not maskable. Processing The common exception vector is used for this exception, and the RI code in the ExcCode field of the Cause register is set. The EPC register contains the address of the reserved instruction unless it is in a branch delay slot, in which case the EPC register contains the address of the preceding branch instruction and the BD bit of the Cause register is set to 1. Servicing All currently defined MIPS ISA instructions can be executed. The process executing at the time of this exception is handled by a UNIX SIGILL/ILL_RESOP_FAULT (illegal instruction/reserved operand fault) signal. This error is usually fatal. 6.4.15 Trap Exception Cause The Trap exception occurs when a TGE, TGEU, TLT, TLTU, TEQ, TNE, TGEI, TGEUI, TLTI, TLTUI, TEQI, or TNEI instruction results in a TRUE condition. This exception is not maskable. Processing The common exception vector is used for this exception, and the Tr code in the ExcCode field of the Cause register is set. The EPC register contains the address of the trap instruction causing the exception unless the instruction is in a branch delay slot, in which case the EPC register contains the address of the preceding branch instruction and the BD bit of the Cause register is set to 1. Servicing At the time of a Trap exception, the kernel reports the UNIX SIGFPE/FPE_INTOVF_TRAP (floating-point exception/integer overflow) signal to the current process, but the exception is usually fatal. 188 CHAPTER 6 EXCEPTION PROCESSING 6.4.16 Integer Overflow Exception Cause An Integer Overflow exception occurs when an ADD, ADDI, SUB, DADD, DADDI or DSUB instruction results in a 2's complement overflow. This exception is not maskable. Processing The common exception vector is used for this exception, and the Ov code in the ExcCode field of the Cause register is set. The EPC register contains the address of the instruction that caused the exception unless the instruction is in a branch delay slot, in which case the EPC register contains the address of the preceding branch instruction and the BD bit of the Cause register is set to 1. Servicing At the time of the exception, the kernel reports the UNIX SIGFPE/FPE_INTOVF_TRAP (floating-point exception/integer overflow) signal to the current process, and this exception is usually fatal. 6.4.17 Watch Exception Cause A Watch exception occurs when a load or store instruction references the physical address specified by the WatchLo/WatchHi registers. The WatchLo/WatchHi registers specify whether a load or store or both could have initiated this exception. When the R bit of the WatchLo register is set to 1: Load instruction When the W bit of the WatchLo register is set to 1: Store instruction When both the R bit and W bit of the WatchLo register are set to 1: Load instruction or store instruction The CACHE instruction never causes a Watch exception. The Watch exception is postponed while the EXL bit in the Status register is set to 1, and Watch exception is only maskable by setting the EXL bit in the Status register to 1. Processing The common exception vector is used for this exception, and the WATCH code in the ExcCode field of the Cause register is set. The EPC register contains the address of the load or store instruction that caused the exception unless it is in a branch delay slot, in which case the EPC register contains the address of the preceding branch instruction and the BD bit of the Cause register is set to 1. 189 CHAPTER 6 EXCEPTION PROCESSING Servicing The Watch exception is a debugging aid; typically the exception handler transfers control to a debugger, allowing the user to examine the situation. To continue, once the Watch exception must be disabled to execute the faulting instruction. The Watch exception must then be reenabled. The faulting instruction can be executed either by the debugger or by setting breakpoints. 6.4.18 Interrupt Exception Cause The Interrupt exception occurs when one of the eight interrupt conditions interrupt sources (Int [3:0]) or NMI. Each of the eight interrupts can be masked by clearing the corresponding bit in the IM field of the Status register, and all of the eight interrupts can be masked at once by clearing the IE bit of the Status register or setting the EXL/ERL bit. Note: They are 1 timer interrupt, 5 ordinary interrupts, and 2 software interrupts. Of the five ordinary interrupts, Int4 is never asserted active. Processing The common exception vector is used for this exception, and the Int code in the ExcCode field of the Cause register is set. The IP field of the Cause register indicates current interrupt requests. It is possible that more than one of the bits can be simultaneously set (or cleared) if the interrupt request signal is asserted and then deasserted before this register is read. The EPC register contains the address of the instruction that caused the exception unless it is in a branch delay slot, in which case the EPC register contains the address of the preceding branch instruction and the BD bit of the Cause register is set to 1. Servicing If the interrupt is caused by one of the two software-generated exceptions (SW0 or SW1), the interrupt condition is cleared by setting the corresponding Cause register bit to 0. If the interrupt is caused by hardware, the interrupt condition is cleared by deactivating the corresponding interrupt request signal. Note is asserted. In the VR4102, interrupt requests from internal peripheral units first enter the ICU and are then notified to the CPU core via one of four 190 CHAPTER 6 EXCEPTION PROCESSING 6.5 EXCEPTION PROCESSING AND SERVICING FLOWCHARTS The remainder of this chapter contains flowcharts for the following exceptions and guidelines for their handlers: -- Common exceptions and a guideline to their exception handler -- TLB/XTLB Refill exception and a guideline to their exception handler -- Cache Error exception -- Cold Reset, Soft Reset and NMI exceptions, and a guideline to their handler. Generally speaking, the exceptions are "processed" by hardware (HW); the exceptions are then "serviced" by software (SW). 191 CHAPTER 6 EXCEPTION PROCESSING Figure 6-14. Common Exception Handler (1/2) (a) Processing exceptions other than Cold reset, Soft reset, NMI, TLB/XTLB Mismatch, and Cache Error exceptions (hardware) Start EntryHi VPN2, ASID X/Context VPN2 Set Cause Register (ExcCode, CE) ; The EntryHi and X/Context registers are set only when a TLB Mismatch, TLB Invalid, or TLB Modified exception occurs. EXL = 1? (SR1) No Yes Instruction in branch delay slot? Yes ; Check for multiple exceptions No BD bit 1 EPC PC - 4 BD bit 0 EPC PC ; BadVAddr is set only when a TLB Mismatch, TLB Invalid, or TLB Modified exception occurs. (BadVAddr is not set when a Bus Error exception occurs. EXL 1 ; Kernel mode is set, and interrupts are disabled. = 0 (normal) BEV = 1 (bootstrap) PC 0xFFFF FFFF 8000 0000 + 180 (Unmapped, cacheable space) PC 0xFFFF FFFF BFC0 0200 + 180 (Unmapped, uncached space) To guideline of general exception handler Remark The exceptions can be masked by the IE or IM bit. The Watch exception can be set to pending status by setting the EXL bit. 192 CHAPTER 6 EXCEPTION PROCESSING Figure 6-14. Common Exception Handler (2/2) (b) Guideline of general exception handler (software) Guideline of general exception handler ; The occurance of TLB Mismatch, TLB Invalid, and TLB Modified exceptions is disabled by using an unmapped space. ; The occurance of the Watch and Interrupt exceptions is disabled by setting EXL = 1. ; Other exceptions are avoided in the OS programs ; However, the Cache error, Cold reset, Soft reset, and NMI exceptions are enabled. Execute MFC0 instruction X/Context register EPC register Status register Cause register Execute MTC0 instruction (Status bit setting) KSU bit 00 EXL bit 0 IE bit = 1 (In Kernel mode, interrupts are enabled.) Check the Cause register, and jump to each routine ; After EXL = 0 is set, all exceptions are enabled (except for the interrupt exception masked by IE or IM and the Cache Error exception masked by DE. No TS bit = 0? (SR21) Yes The processor is reset Servicing by each exception routine ; The register files are saved. EXL = 1 Execute MTC0 instruction EPC register Status register ; The execution of the ERET instruction is disabled in the branch delay slots of the other jump instructions. ; The processor does not execute an instruction in the branch delay slot of the ERET instruction. : PC EPC, EXL 0 ERET 193 CHAPTER 6 EXCEPTION PROCESSING Figure 6-15. TLB/XTLB Refill Exception Handler (1/2) (a) Hardware Start Yes Instruction in branch delay slot? EntryHi VPN2, ASID X/Context VPN2 Set Cause Register (ExcCode) No EntryHi VPN2, ASID X/Context VPN2 Set Cause Register (ExcCode) EXL = 0? (SR1) Yes No EXL = 0? (SR1) Yes No ; Check for multiple exceptions. BD bit 1 EPC PC - 4 BD bit 0 EPC PC Yes XTLB exception? No XTLB Mismatch vector offset = 0x080 TLB Mismatch vector offset = 0x000 General Exception vector offset = 0x180 EXL 1 ; Kernel mode is set and interrpts are disabled. = 0 (normal) BEV (SR22) = 1 (bootstrap) PC 0xFFFF FFFF 8000 0000 + vector offset (Unmapped, cacheable space) PC 0xFFFF FFFF BFC0 0200 + vector offset (Unmapped, uncached space) To guideline of TLB/XTLB exception hadler 194 CHAPTER 6 EXCEPTION PROCESSING Figure 6-15. TLB/XTLB Refill Exception Handler (2/2) (b) Guideline of TLB/XTLB exception handler (software) Guideline of TLB/XTLB exception handler ; The occurence of TLB Mismatch, TLB Invalid, and TLB Modified exception is disabled by using an unmapped space. ; The occurence of the Watch and Interrupt exceptions is disabled by setting EXL = 1. ; Other exceptions are avoided in the OS programs. ; However, the Cache error, Cold reset, Soft reset, and NMI exceptions are enabled. ; The physical address for a virtual address loaded into the X/Context register is loaded into the EntryLo register and written to the TLB. ; As long as a data/instruction address exists in the mapping space, another TLB Mismatch exception may occur. In such a case, EXL = 1 is set, causing a jump to the common exception vector. (In this case, the common exception handler handles the TLB miss or the ERET instruction returns control to the user program, then a TLB Mismatch exception is generated again.) ; The execution of the ERET instruction is disabled in the branch delay slots of other jump instructions. ; The processor does not execute an instruction in the branch delay slot of the ERET instruction. ; PC EPC, EXL 0 Execute MFC0 instruction X/Context register Servicing by each exceoption routine ERET 195 CHAPTER 6 EXCEPTION PROCESSING Figure 6-16. Cache Error Exception Handler Hardware Start Set cache error register ERL = 1? (SR2) Yes No Yes Instruction in branch delay slot? ; Check for multple exceptions No BD bit 1 Error EPC PC - 4 BD bit 0 Error EPC PC ERL 1 = 0 (normal) BEV (SR22) = 1 (bootstrap) PC 0xFFFF FFFF A000 0000 + 100 (Unmapped, uncached space) PC 0xFFFF FFFF BFC0 0200 + 100 (Unmapped, uncached space) Software ; The Cache Error and TLB-related Error exceptions do not occur because of unmapped/uncache vector. ; The occurence of the Watch and Interrupt exceptions is disabled by setting ERL = 1. ; Other exceptions are avoided in the OS programs. ; However, the Cold reset, Soft reset, and NMI exceptions are enabled. ; The execution of the ERET instruction is disabled in the branch delay slots of other jump instructions. ; The processor does not execute an instruction in the branch delay slot of the ERET instruction. ; PC Error EPC, ERL 0 Servicing by exception routine ERET Remark The Cache Error exception can be masked by setting the DE (SR16) bit to 1. When ERL = 1, Cache Error exceptions are masked. 196 CHAPTER 6 EXCEPTION PROCESSING Figure 6-17. Cold Reset, Soft Reset, and NMI Exception Handler Hardware Soft reset or NMI exception Cold reset exception ERL = 1? (SR2) No Yes Instruction in branch delay slot? Yes ERL = 1? (SR2) No Yes Instruction in branch delay slot? Yes No BD bit 1 Error EPC PC - 4 BD bit 0 Error EPC PC BD bit 1 Error EPC PC - 4 No BD bit 0 Error EPC PC Set Status register BEV bit 1 TS bit 0 SR bit 1 ERL bit 1 Random register 31 Wired register 0 Update Config register bits 31:28 22:6 Set Status register BEV bit 1 TS bit 0 SR bit 0 ERL bit 1 PC 0xFFFF FFFF BFC0 0000 Software Yes ; The processor provides no means of distinguishing between an NMI exception and Soft reset exception, such that this must be determined at the system level. NMI? No Servicing by NMI exception routine SR = 1? (SR20) Yes No ERET Servicing by Soft reset exception routine Servicing by Cold reset exception routine 197 [MEMO] 198 CHAPTER 7 INITIALIZATION INTERFACE This chapter describes the initialization interface and processor modes. that can be selected by the user. Remark # that follows signal names indicates active low. It also explains the reset signal descriptions and types, signal- and timing-related dependence, and the initialization sequence during each mode 7.1 RESET FUNCTION There are five ways to reset the VR4102. Each is summarized below. 7.1.1 RTC Reset During power-on, set the RTCRST# pin as active. After waiting (about 600 ms) for the 32.768-kHz oscillator to begin oscillating when the power supply is stable at 3.0 V or above, setting the RTCRST# pin as inactive causes the RTC unit to begin counting. Next, when the POWER pin, DCD# pin, or GPIO[3] pin becomes inactive, the VR4102 asserts the POWERON pin and uses the BATTINH/BATTINT# signal to perform a battery level check. If the battery check's result is OK, the VR4102 asserts the MPOWER pin and waits for the stabilization time period (about 350 ms) for the external agent's DC/DC converter, then begins PLL oscillation and starts all clocks (a period of about 16 ms following the start of PLL oscillation is required for stabilization of PLL oscillation). An RTC reset does not save any of the status information and it completely initializes the processor's internal state. Since the DRAM is not switched to self refresh mode, the contents of DRAM after an RTC reset are not at all guaranteed. After a reset, the processor becomes the system bus master and it begins the Cold reset exception sequence to access the reset vectors in the ROM space. Since only part of the internal status is reset when a reset occurs in the VR4102, the processor should be completely initialized by software. 199 CHAPTER 7 INITIALIZATION INTERFACE Figure 7-1. RTC Reset RTCRST#(i) POWER(i) POWERON(o) MPOWER(o) ColdReset#(internal) Reset#(internal) PLL(internal) RTC (internal, 32kHz) Undefined Stable oscillation >600ms 350ms >32ms Undefined Stable oscillation 16ms 16MasterClock Note Note MasterClock is the basic clock used in the CPU core. 200 CHAPTER 7 INITIALIZATION INTERFACE 7.1.2 RSTSW After the RSTSW# pin becomes active and then becomes inactive 100 Ps later, the VR4102 starts PLL oscillation and starts all clocks (a period of about 16 ms following the start of PLL oscillation is required for stabilization of PLL oscillation). A reset by RSTSW initializes the entire internal state except for the RTC timer and the PMU. Since the DRAM is not switched to self refresh mode, the contents of DRAM after an RTC reset are not at all guaranteed. After a reset, the processor becomes the system bus master and it begins the Cold reset exception sequence to access the reset vectors in the ROM space. Since only part of the internal status is reset when a reset occurs in the VR4102, the processor should be completely initialized by software. Figure 7-2. RSTSW RSTSW#(i) MRAS(0:3)#(o) UCAS#/LCAS#(o) POWER(i) MPOWER(o) ColdReset#(internal Reset#(internal) PLL(internal) RTC (internal, 32kHz) Stable oscillation 16ms >3RTC 16MasterClock Note L H Stable oscillation Undefined Stable oscillation Note MasterClock is the basic clock used in the CPU core. 201 CHAPTER 7 INITIALIZATION INTERFACE 7.1.3 Deadman's Switch After the Deadman's switch unit is enabled, if the Deadman's switch is not cleared within the specified time period, the VR4102 is immediately returned to reset status. performed by software. A reset by the Deadman's switch initializes the entire internal state except for the RTC timer and the PMU. Since the DRAM is not switched to self refresh mode, the contents of DRAM after a Deadman's switch reset are not at all guaranteed. After a reset, the processor becomes the system bus master and it begins the Cold reset exception sequence to access the reset vectors in the ROM space. Since only part of the internal status is reset when a reset occurs in the VR4102, the processor should be completely initialized by software. Figure 7-3. Deadman's Switch Setting and clearing of the Deadman's switch is RSTSW#(i) POWER(i) MPOWER(o) ColdReset#(internal) Reset#(internal) PLL(internal) RTC (internal, 32kHz) H L H Stable oscillation Stable oscillation Stable oscillation Undefined 16ms 16MasterClock Note Note MasterClock is the basic clock used in the CPU core. 202 CHAPTER 7 INITIALIZATION INTERFACE 7.1.4 Software Shutdown When the software executes the HIBERNATE instruction, the VR4102 sets the DRAM to self refresh mode and sets the MPOWER pin as inactive, then enters reset status. Recovery from reset status occurs when the POWER pin is asserted, when a WakeUpTimer interrupt occurs, or when the DCD# pin is asserted. A reset by software shutdown initializes the entire internal state except for the RTC timer and the PMU. After a reset, the processor becomes the system bus master and it begins the Cold reset exception sequence to access the reset vectors in the ROM space. Since only part of the internal status is reset when a reset occurs in the VR4102, the processor should be completely initialized by software. Figure 7-4. Software Shutdown MRAS(0:3)#/ UCAS#/LCAS# (o) POWER(i) POWERON(o) MPOWER(o) ColdReset#(internal) Reset#(internal) PLL(internal) RTC (internal, 32kHz) Stable oscillation >32ms Undefined Stable oscillation 16ms 350ms 16MasterClock Note Stopped Note MasterClock is the basic clock used in the CPU core. 203 CHAPTER 7 INITIALIZATION INTERFACE 7.1.5 HALTimer Shutdown After an RTC reset is canceled, if the HAL timer is not canceled by software within about four seconds (the HALTIMERRST bit of the PMUCNTREG register is not set to 1), the VR4102 enters reset status. Recovery from reset status occurs when the POWER pin is asserted or when a WakeUpTimer interrupt occurs. A reset by HAL timer initializes the entire internal state except for the RTC timer and the PMU. After a reset, the processor becomes the system bus master and it begins the Cold reset exception sequence to access the reset vectors in the ROM space. Since only part of the internal status is reset when a reset occurs in the VR4102, the processor should be completely initialized by software. Figure 7-5. HALTimer Shutdown MRAS(0:3)#/ UCAS#/LCAS# (o) POWER(i) POWERON(o) MPOWER(o) ColdReset#(internal Reset#(internal) PLL(internal) RTC (internal, 32kHz) Stable oscillation >32ms Undefined Stable oscillation 16ms 4s 350ms 16MasterClock Note Stopped Note MasterClock is the basic clock used in the CPU core. 204 CHAPTER 7 INITIALIZATION INTERFACE 7.2 POWERON SEQUENCE The factors that cause the VR4102 to switch from hibernate mode or shutdown mode to full speed mode are called power-on factors. There are four power-on factors: assertion of the POWERON pin, assertion of the DCD# pin, activation of the wakeup timer, and assertion of the GPIO pins (GPIO[3..0], GPIO[12..9]). When an activation factor occurs, the VR4102 asserts the POWERON pin, then provides notification to external agents that the VR4102 is ready for power-on. Three RTC clocks after the POWERON pin is asserted, the VR4102 checks the state of the BATTINH/BATTINT# pin. If the BATTINH/BATTINT# pin's state is low, the POWERON pin is deasserted one RTC clock after the BATTINH/BATTINT# pin check is completed, then the VR4102 is not activated. BATTINH/BATTINT# pin check is completed, then the MPOWER pin is asserted and the VR4102 is activated. Figure 7-6 shows a timing chart of VR4102 activation and Figure 7-7 shows a timing chart of when activation fails due to the BATTINH/BATTINT# pin's "low" state. For details of poweron sequence according to each power-on factor, refer to chapter 15. If the BATTINH/BATTINT# pin's state is high, the POWERON pin is deasserted three RTC clocks after the 205 CHAPTER 7 INITIALIZATION INTERFACE Figure 7-6. VR4102 Activation Sequence (when Battery Check Is OK) POWERON(o) MPOWER(o) ColdReset#(internal) Reset#(internal) BATTINH/BATTINT#(i) PLL(internal) RTC (internal, 32kHz) Stopped Undefined Detection of activation factor Check BATTINH/ BATTINT# pin Activation of CPU Stable oscillation Figure 7-7. VR4102 Activation Sequence (when Battery Check Is NG) POWERON(o) MPOWER(o) L ColdReset#(internal) L Reset#(internal) L BATTINH/BATTINT#(i) PLL(internal) H RTC (internal, 32kHz) Detection of activation Check BATTINH/ BATTINT# pin CPU not activated 206 CHAPTER 7 INITIALIZATION INTERFACE 7.3 RESET OF THE CPU CORE This section describes the reset sequence of the VR4100 CPU core. For details about factors of reset or reset of the whole VR4102, refer to 7.1 and Chapter 15. 7.3.1 Cold Reset In the VR4102, a cold reset sequence is executed in the CPU core in the following cases: x RTC reset x RSTSW reset x Deadman's SW shutdown x Software shutdown x HAL Timer shutdown x Battery low shutdown x Battery lock release shutdown A Cold Reset completely initializes the CPU core, except for the following register bits. x The TS and SR bits of the Status register are cleared to 0. x The ERL and BEV bits of the Status register are set to 1. x The upper limit value (31) is set in the Random register. x The Wired register is initialized to 0. x Bits 31 to 28 of the Config register are set to 0 and bits 22 to 3 to 0x04800; the other bits are undefined. x The values of the other registers are undefined. Once power to the processor is established, the ColdReset# (internal) and the Reset# (internal) signals are asserted and a Cold Reset is started. After approximately 2 ms assertion, the ColdReset# signal is deasserted synchronously with MasterOut. Then the Reset# signal is deasserted synchronously with MasterOut, and the Cold Reset is completed. Upon reset, the CPU core becomes bus master and drives the SysAD bus (internal). After Reset# is deasserted, the CPU core branches to the Reset exception vector and begins executing the reset exception code. 207 CHAPTER 7 INITIALIZATION INTERFACE 7.3.2 Soft Reset Caution Soft Reset is not supported in the present VR4102. A Soft Reset initializes the CPU core without affecting the clocks; in other words, a Soft Reset is a logic reset. In a Soft Reset, the CPU core retains as much state information as possible; all state information except for the following is retained: x The TS bit of the Status register is cleared to 0. x The SR, ERL and BEV bits of the Status register are set to 1. x The Count register is initialized to 0. x The IP7 bit of the Cause register is cleared to 0. x Any Interrupts generated on the SysAD bus are cleared. x NMI is cleared. x The Config register is initialized. A Soft Reset is started by assertion of the Reset# signal, and is completed at the deassertion of the Reset# signal synchronized with MasterOut. In general, data in the CPU core is preserved for debugging purpose. Upon reset, the CPU core becomes bus master and drives the SysAD bus (internal). After Reset# is deasserted, the CPU core branches to the Reset exception vector and begins executing the reset exception code. 208 CHAPTER 7 INITIALIZATION INTERFACE Figure 7-8. Cold Reset VDD MasterClock (Internal) ColdReset# (Internal) Reset# (Internal) MasterOut (Internal) TClock Note Undefined Undefined (Internal) Note MasterClock is the basic clock used in the CPU core. Figure 7-9. Soft Reset VDD MasterClock (Internal) Reset# (Internal) MasterOut (Internal) TClock Note H (Internal) Note MasterClock is the basic clock used in the CPU core. 209 CHAPTER 7 INITIALIZATION INTERFACE 7.4 VR4102 PROCESSOR MODES The VR4102 supports various modes, which can be selected by the user. The CPU core mode is set each time a write occurs in the Status register and Config register. The on-chip peripheral unit mode is set by writing to the I/O register. This section describes the CPU core's operation modes. For operation modes of on-chip peripheral units, see the chapters describing the various units. 7.4.1 Power Modes The VR4102 supports four power modes: Fullspeed mode, Standby mode, Suspend mode, and Hibernate mode. (1) Fullspeed Mode This is the normal operation mode. The VR4102's default status sets operation under Fullspeed mode. After the processor is reset, the VR4102 returns to Fullspeed mode. (2) Standby Mode When a STANDBY instruction has been executed, the processor can be set to Standby mode. During Standby mode, all of the internal clocks in the CPU core except for the timer and interrupt clocks are held at high level. The peripheral units all operate as they do during Fullspeed mode. This means that DMA operations are enabled during Standby mode. When the STANDBY instruction completes the WB stage, the VR4102 remains idle until the SysAD internal bus enters the idle state. Next, the clocks in the CPU core are shut down and pipeline operation is stopped. However, the PLL, timer, and interrupt clocks continue to operate, as do the internal bus clocks (TClock and MasterOut). During Standby mode, the processor is returned to Fullspeed mode if any interrupt occurs, including a timer interrupt that occurs internally. (3) Suspend Mode When the SUSPEND instruction has been executed, the processor can be set to Suspend mode. During Suspend mode, the processor stalls the pipeline and supplying all of the internal clocks in the CPU core except for PLL timer and interrupt clocks are stopped. The VR4102 stops supplying TClock to peripheral units. Accordingly, during Suspend mode peripheral units can only be activated by a special interrupt unit (DCD# control, etc.). While in this mode, the register and cache contents are retained. When the SUSPEND instruction completes the WB stage, the VR4102 switches the DRAM to self refresh mode and then waits for the SysAD internal bus to enter the idle state. Next, the clocks in the CPU core are shut down and pipeline operation is stopped. The VR4102 then stops supplying TClock to peripheral units. However, the PLL, timer, and interrupt clocks continue to operate, as do the MasterOut. The processor remains in Suspend mode until an interrupt is received, at which time it returns to Fullspeed mode. 210 CHAPTER 7 INITIALIZATION INTERFACE (4) Hibernate Mode When the HIBERNATE instruction has been executed, the processor can be set to Hibernate mode. During Hibernate mode, the processor stops supplying clocks to all units. The register and cache contents are retained and output of TClock and MasterOut is stopped. The processor remains in Hibernate mode until the POWER pin is asserted, a WakeUpTimer interrupt occurs, DCD# pin is asserted, or GPIO[3] is asserted, at which the processor returns to Fullspeed mode. Power consumption during Hibernate mode is about 0 W (it does not go completely to 0 W due to the existence of a 32.768-kHz oscillator, on-chip peripheral units that operate at 32.768 kHz, or DRAM self refresh). 7.4.2 Privilege Mode The VR4102 supports three system modes: kernel expanded addressing mode, supervisor expanded addressing mode, and user expanded addressing mode. These three modes are described below. (1) Kernel Expanded Addressing Mode When the Status register's KX bit has been set, an expanded TLB miss exception vector is used when a TLB miss occurs for the kernel address. While in kernel mode, the MIPS III operation code can always be used, regardless of the KX bit. (2) Supervisor Expanded Addressing Mode When the Status register's SX bit has been set, the MIPS III operation code can be used when in supervisor mode and an expanded TLB miss exception vector is used when a TLB miss occurs for the supervisor address. (3) User Expanded Addressing Mode When the Status register's UX bit has been set, the MIPS III operation code can be used when in user mode, and an expanded TLB miss exception vector is used when a TLB miss occurs for the user address. When this bit is cleared, the MIPS I and II operation codes can be used, as can 32-bit virtual addresses. 7.4.3 Reverse Endian When the Status register's RE bit has been set, the endian ordering is reversed to adopt the user software's perspective. However, the RE bit of the Status register must be set to 0 since the VR4102 supports the little-endian order only. 7.4.4 Bootstrap Exception Vector (BEV) The BEV bit is used to generate an exception during operation testing (diagnostic testing) of the cache and main memory system. This bit is automatically set to 1 after reset or NMI exception. When the Status register's BEV bit has been set, the address of the TLB miss exception vector is changed to the virtual address 0xFFFF FFFF BFC0 0200 and the ordinary execution vector is changed to address 0xFFFF FFFF BFC0 0380. When the BEV bit is cleared, the TLB miss exception vector's address is changed to 0xFFFF FFFF 8000 0000 and the ordinary execution vector is changed to address 0xFFFF FFFF 8000 0180. 211 CHAPTER 7 INITIALIZATION INTERFACE 7.4.5 Cache Error Check When the Status register's CE bit has been set, the contents of the PErr register can be written to the data cache's parity bit instead of the parity generated by the STORE instruction. If the CACHE instruction's "Fill" option is executed, the contents of the PErr register can be written to the instruction cache's parity bit instead of the instruction parity. 7.4.6 Parity Error Prohibit When the Status register's DE bit has been set, the processor does not issue any cache parity error exceptions. 7.4.7 Interrupt Enable (IE) When the Status register's IE bit has been cleared, no interrupts can be received except for reset interrupts and nonmaskable interrupts. 212 CHAPTER 8 CACHE MEMORY This chapter describes in detail the cache memory: its place in the VR4100 CPU core memory organization, and individual organization of the caches. This chapter uses the following terminology: -- The data cache may also be referred to as the D-cache. -- The instruction cache may also be referred to as the I-cache. These terms are used interchangeably throughout this book. 8.1 MEMORY ORGANIZATION Figure 8-1 shows the VR4100 CPU core system memory hierarchy. In the logical memory hierarchy, the caches lie between the CPU and main memory. They are designed to make the speedup of memory accesses transparent to the user. Each functional block in Figure 8-1 has the capacity to hold more data than the block above it. For instance, physical main memory has a larger capacity than the caches. At the same time, each functional block takes longer to access than any block above it. For instance, it takes longer to access data in main memory than in the CPU onchip registers. Figure 8-1. Logical Hierarchy of Memory VR4100 CPU core Register Register Register I-cache D-cache Cache Cache Faster access time Main memory Memory Increasing data capacity Disc, CD-ROM, tape, etc. Memory media 213 CHAPTER 8 CACHE MEMORY The VR4100 CPU core has two on-chip caches: one holds instructions (the instruction cache), the other holds data (the data cache). The instruction and data caches can be read in one PClock cycle. Data writes are pipelined and can complete at a rate of one per PClock cycle. In the first stage of the cycle, the store address is translated and the tag is checked; in the second stage, the data is written into the data RAM. 8.2 CACHE ORGANIZATION This section describes the organization of the on-chip data and instruction caches. Figure 8-2 provides a block diagram of the VR4100 CPU core cache and memory model. Figure 8-2. Cache Support VR4100 CPU core Cache controller Main memory I-cache Caches D-cache I-cache: Instruction cache D-cache: Data cache (1) Cache Line Lengths A cache line is the smallest unit of information that can be fetched from main memory for the cache, and that is represented by a single tag. The line size for the instruction/data cache is 4 words (16 bytes). For cache tag, refer to 8.2.1 and 8.2.1. (2) Cache Sizes The instruction cache in the VR4100 CPU core is 4 Kbytes; the data cache is 1 Kbytes. 8.2.1 Organization of the Instruction Cache (I-Cache) Each line of I-cache data (although it is actually an instruction, it is referred to as data to distinguish it from its tag) has an associated 24-bit tag that contains a 22-bit physical address, a single Valid bit, and a single Parity bit. Word parity is used on I-cache data (1 bit of parity per word). The VR4100 CPU core I-cache has the following characteristics: -- direct-mapped -- indexed with a virtual address -- checked with a physical tag -- organized with a 4-word (16-byte) cache line. Figure 8-3 shows the format of a 4-word (16-byte) I-cache line. 214 CHAPTER 8 CACHE MEMORY Figure 8-3. Cache Line Format 23 P 1 PTag 22 V 1 Physical tag (bits 31 to 10 of the physical address) When a tag is specified by the Cache instruction, however, the high-order 20 bits are used. Valid bit Even parity for the Ptag and V bit I-cache data Even parity for the data (1-bit parity for 4-byte data) 21 PTag 22 32 DataP DataP DataP DataP 31 Data Data Data Data 0 0 V P Data DataP 8.2.2 Organization of the Data Cache (D-Cache) Each line of D-cache data has an associated 26-bit tag that contains a 22-bit physical address, a Valid bit, a Parity bit, a Write-back bit, and a parity bit for Write-back. The VR4100 CPU core D-cache has the following characteristics : -- write-back -- direct-mapped -- indexed with a virtual address -- checked with a physical tag -- organized with a 4-word (16-byte) cache line. Figure 8-4 shows the format of a 4-word (16-byte) D-cache line. Figure 8-4. Data Cache Line Format 25 W' 1 PTag V P W W' Data DataP 24 W 1 23 P 1 22 V 1 21 PTag 22 71 DataP DataP 64 63 Data Data 0 0 Physical tag (bits 31 to 10 of the physical address) Valid bit Even parity for the Ptag and V bit Write-back bit (set if cache line has been written) Even parity for the write-back bit D-cache data Even parity for the data (1-bit parity for 4-byte data) 215 CHAPTER 8 CACHE MEMORY 8.2.3 Accessing the Caches Figure 8-5 shows the virtual address (VA) index into the caches. The number of virtual address bits used to index the instruction and data caches depends on the cache size. (1) Data cache addressing This addressing uses bits VA [9:4]. The most significant bit is VA9 because the cache size is 1 Kbyte. The least significant bit is VA4 because the line size is 4 words (16 bytes). (2) Instruction cache addressing This addressing uses bits VA [11:4]. The most significant bit is VA11 because the cache size is 4 Kbytes. The least significant bit is VA4 because the line size is 4 words (16 bytes). Figure 8-5. Cache Data and Tag Organization Tags Tags Data Tag line Tag line Tags Tags Data line VA (9:4) for 1-Kbyte D-cache and VA (11:4) for 4-Kbyte I-cache 64 P V Tag W Data 216 CHAPTER 8 CACHE MEMORY 8.3 CACHE OPERATIONS As described earlier, caches provide fast temporary data storage, and they make the speedup of memory accesses transparent to the user. In general, the CPU core accesses cache-resident instructions or data through the following procedure: 1. The CPU core, through the on-chip cache controller, attempts to access the next instruction or data in the appropriate cache. 2. The cache controller checks to see if this instruction or data is present in the cache. -- If the instruction/data is present, the CPU core retrieves it. This is called a cache hit. -- If the instruction/data is not present in the cache, the cache controller must retrieve it from memory. This is called a cache miss. 3. The CPU core retrieves the instruction/data from the cache and operation continues. It is possible for the same data to be in two places (main memory and cache) simultaneously. This data is kept consistent through the use of a write-back methodology; that is, modified data is not written back to memory until the cache line is to be replaced. Instruction and data cache line replacement operations are described in the following sections. 8.3.1 Cache Write Policy The VR4100 CPU core manages its data cache by using a write-back policy; that is, it stores write data into the cache, instead of writing it directly to memory Note . Some time later this data is independently written into memory. In the VR4102 implementation, a modified cache line is not written back to the main memory until the cache line is to be replaced either in the course of satisfying a cache miss, or during the execution of a write-back CACHE instruction. When the CPU core writes a cache line back to the main memory, it does not ordinarily retain a copy of the cache line, and the state of the cache line is changed to invalid. Note Write-through cache policy performs the function contrary to the write-back policy. Data written into memory is also written into cache simultaneously. 217 CHAPTER 8 CACHE MEMORY 8.4 CACHE STATES (1) Cache line The three terms below are used to describe the state of a cache line: -- Dirty: a cache line containing data that has changed since it was loaded from memory. -- Clean: a cache line that contains data that has not changed since it was loaded from memory. -- Invalid: a cache line that does not contain valid information must be marked invalid, and cannot be used. For example, after a Soft Reset, software sets all cache lines to invalid. A cache line in any other state than invalid is assumed to contain valid information. Neither Cold reset nor Soft reset sets caches invalid. Software can invalidate caches. (2) Data cache The data cache supports three cache states: -- invalid -- valid clean -- valid dirty (3) Instruction cache The instruction cache supports two cache states: -- invalid -- valid The state of a valid cache line may be modified when the processor executes a CACHE operation. CACHE operations are described in Chapter 27. 218 CHAPTER 8 CACHE MEMORY 8.5 CACHE STATE TRANSITION DIAGRAMS The following section describes the cache state diagrams for the data and instruction caches. These state diagrams do not cover the initial state of the system, since the initial state is system-dependent. 8.5.1 Data Cache State Transition The following diagram illustrates the data cache state transition sequence. A load or store operation may include one or more of the atomic read and/or write operations shown in the state diagram below, which may cause cache state transitions. -- Read (1) indicates a read operation from memory to cache, inducing a cache state transition. -- Write (1) indicates a write operation from CPU core to cache, inducing a cache state transition. -- Read (2) indicates a read operation from cache to the CPU core, which induces no cache state transition. -- Write (2) indicates a write operation from CPU core to cache, which induces no cache state transition. Figure 8-6. Data Cache State Diagram CACHE op Invalid Write (1) Read (1) CACHE op Read (2) Write (2) Write (1) Valid Dirty CACHE op Write-back Valid Clean Read (2) 8.5.2 Instruction Cache State Transition The following diagram illustrates the instruction cache state transition sequence. -- Read (1) indicates a read operation from memory to cache, inducing a cache state transition. -- Read (2) indicates a read operation from cache to the CPU core, which induces no cache state transition. Figure 8-7. Instruction Cache State Diagram CACHE op Read (2) Valid Read (1) Invalid 219 CHAPTER 8 CACHE MEMORY 8.6 CACHE DATA INTEGRITY The D- and I-cache data RAM arrays are protected by parity (byte parity for D-cache, word parity for I-cache). Dand I-cache tag RAM arrays are also protected by parity. These parity bits are checked for errors on every cache read access. Cache error exception occurs if the CPU core encounters a parity error during an instruction cache access, a data cache access, or memory read access. The CacheErr register indicates the source of the error. Figure 8-8 to Figure 8-22 shows the parity generation and checking operations for various cache accesses. Figure 8-8. Data flow on Instruction Fetch Start TagParity OK, DE = 1 or ERL = 1 Error Cache Error Exception Hit TagCheck Miss or Invalid (See Figure 8-21) Refill Desigerd Data Parity Error OK, DE = 1 or ERL = 1 Data Fetch Cache Error Exception END 220 CHAPTER 8 CACHE MEMORY Figure 8-9. Data Integrity on Load Operations Start TagParity OK, DE = 1 or ERL = 1 Error Cache Error Exception Hit TagCheck Miss or Invalid Wbit Parity OK, DE = 1 or ERL = 1 Valid bit & TagCheck Wbit V = 1 (valid) and W = 1 (dirty) (See Figure 8-22) Writeback & Refill Refill (See Figure 8-21) Error V = 0 (invalid) or W = 0 (clean) Cache Error Exception Desigerd Data Parity Error OK, DE = 1 or ERL = 1 Data Load to register Cache Error Exception END 221 CHAPTER 8 CACHE MEMORY Figure 8-10. Data Integrity on Store Operations Start TagParity OK, DE = 1 or ERL = 1 Error Cache Error Exception Hit TagCheck Miss Error Wbit Parity OK, DE = 1 or ERL = 1 Valid bit & TagCheck Wbit V = 1 (valid) and W = 1 (dirty) (See Figure 8-22) Writeback & Refill V = 0 (invalid) or W = 0 (clean) Cache Error Exception Refill (See Figure 8-21) CEbit of SR =0 Data Parity Generate =1 Data Parity from PErr reg. Data Write to D-Cache END 222 CHAPTER 8 CACHE MEMORY Figure 8-11. Data Integrity on Index_Invalidate Operations Start TagParity OK, DE = 1 or ERL = 1 Valid bit clear Error Cache Error Exception END Figure 8-12. Data Integrity on Index_Writeback_Invalidate Operations Start Tag Parity, Wbit Parity Error OK, DE = 1 or ERL = 1 =0 Valid bit = 1 (valid) = 0 (clean) Wbit = 1 (dirty) (See Figure 8-20) Writeback Data Parity OK, DE = 1 or ERL = 1 Cache Error Exception Error Valid bit and Wbit clear Cache Error Exception END 223 CHAPTER 8 CACHE MEMORY Figure 8-13. Data Integrity on Index_Load_Tag Operations Start Tag and Tag Parity Read to TagLo Wbit and Wbit Parity Read to TagLo D-Cache only END Figure 8-14. Data Integrity on Index_Store_Tag Operations Start CEbit of SR =0 Tag Parity Generate =1 Tag Parity from TagLo D-Cache only Wbit Parity Generate Wbit Parity from TagLo Tag Write from TagLo END 224 CHAPTER 8 CACHE MEMORY Figure 8-15. Data Integrity on Create_Dirty Operations Start Tag Parity, Wbit Parity Error Cache Error Exception Miss or Invalid OK, DE = 1 or ERL = 1 TagCheck Hit =0 (clean) Valid bit & Wbit = 1 (dirty) (See Figure 8-20) Data Parity or ERL = 1 Error Writeback OK, DE = 1 Cache Error Exception Valid bit and Wbit set. Tag write. Wbit parity and Tag parity generate. END Figure 8-16. Data Integrity on Hit_Invalidate Operations Start TagParity OK, DE = 1 or ERL = 1 TagCheck Hit Error Miss or Invalid Cache Error Exception Valid bit clear. Tag parity generate. END 225 CHAPTER 8 CACHE MEMORY Figure 8-17. Data Integrity on Hit_Writeback_Invalidate Operations Start Tag Parity, Wbit Parity Error OK, DE = 1 or ERL = 1 Miss or Invalid TagCheck Hit = 0 (clean) Wbit Error = 1 (dirty) (See Figure 8-20) Writeback OK, DE = 1 or ERL = 1 Cache Error Exception Data Error Data Cache Error Exception Valid bit clear. Tag parity generate. OK, DE = 1 or ERL = 1 Cache Error Exception END Figure 8-18. Data Integrity on Fill Operations Start (See Figure 8-21) Refill END 226 CHAPTER 8 CACHE MEMORY Figure 8-19. Data Integrity on Hit_Writeback Operations Start Tag Parity, Wbit Parity Error Wbit Parity check is D-Cache only Miss or Invalid OK, DE = 1 or ERL = 1 TagCheck Hit Cache Error Exception = 0 (clean) Wbit = 1 (dirty) Writeback Data Parity OK, DE = 1 or ERL = 1 D-Cache only Error (See Figure 8-20) Cache Error Exception D-Cache only Wbit clear END 227 CHAPTER 8 CACHE MEMORY Figure 8-20. Data Integrity on Writeback Flow Writeback Data Parity Error OK, DE = 1 or ERL = 1 Erroneous bit = 0 Writeback to memory Erroneous bit = 1 No EOD? Yes Writeback Data Parity Error existed in writeback data OK, DE = 1 or ERL = 1 Cache Error Exception Figure 8-21. Data Integrity on Refill Flow Write data to cache No EOD? Yes Error existed in refill data Cache line Invalidate Erroneous bit OK Bus Error Exception 228 CHAPTER 8 CACHE MEMORY Figure 8-22. Data Integrity on Writeback & Refill Flow Writeback Data Parity Error OK, DE = 1 or ERL = 1 Erroneous bit = 0 Writeback to memory No EOD? Yes Refill start Erroneous bit = 1 Writeback Data Parity Error existed in writeback data OK, DE = 1 or ERL = 1 Write data to cache No EOD? Yes Writeback Data Parity Error existed in writeback data Cache Error Exception OK, DE = 1 or ERL = 1 Erroneous bit Error existed in refill data Cache line Invalidate OK Bus Error Exception Remark Write-back Procedure: On a store miss write-back, data tag and tag parity are checked and data parity is transferred to the write buffer. Byte parity is generated for the physical address and transferred to write buffer. If an error is detected on the data field, the write back is not terminated; the erroneous data is still written out. If an error is detected in the tag field, the write-back bus cycle is not issued. In both cases a cache error exception is taken. During a Cache operation, cache data may not be checked in some cases, but tag parity is always checked. At that time, if a tag parity error occurs, the Cache Error exception is taken and the operation is not permitted to complete. 229 CHAPTER 8 CACHE MEMORY 8.7 MANIPULATION OF THE CACHES BY AN EXTERNAL AGENT The VR4102 does not provide any mechanisms for an external agent to examine and manipulate the state and contents of the caches. 230 CHAPTER 9 CPU CORE INTERRUPTS Four types of interrupt are available on the CPU core. These are: -- one non-maskable interrupt, NMI -- five ordinary interrupts -- two software interrupts -- one timer interrupt These are described in this chapter. 9.1 NON-MASKABLE INTERRUPT (NMI) The non-maskable interrupt request signal is acknowledged by asserting the NMI signal (internal), forcing the processor to branch to the Reset Exception vector. This NMI signal is latched into an internal register at the rising edge of MasterOut, as shown in Figure 9-1. NMI only takes effect when the processor pipeline is running. This interrupt cannot be masked. Figure 9-1 shows the internal derivation of the NMI signal. The NMI signal is latched into an internal register at the rising edge of MasterOut. The latched NMI signal is inverted and then transmitted as an NMI request. Figure 9-1. Non-maskable Interrupt Signal (Internal register) NMI signal NMI request MasterOut 9.2 ORDINARY INTERRUPTS Ordinary interrupts are set by asserting the Int(4:0) signals (internal). VR4102. These interrupts can be masked with the IM(6..2), IE, and EXL fields of the Status register. However, Int4 never occur on the 231 CHAPTER 9 CPU CORE INTERRUPTS 9.3 SOFTWARE INTERRUPTS GENERATED IN CPU CORE Software interrupts generated in the CPU core are acknowledged by setting bits 1 and 0 of the IP (interrupt pending) field in the Cause register. These may be written by software, but there is no hardware mechanism to set or clear these bits. After the processing of a software interrupt exception, corresponding bit of the IP field in the Cause register must be cleared before returning to ordinary routine or enabling multiple interrupts. These interrupts are maskable through the IM(1:0), IE, and EXL fields of the Status register. 9.4 TIMER INTERRUPT The timer interrupt uses bit 15 of the Cause register, which is bit 7 of the IP (interrupt pending) field. This bit is automatically set whenever the value of the Count register equals the value of the Compare register, to acknowledge an interrupt request. This interrupt is maskable by setting IM7 of the Status register. 9.5 ASSERTING INTERRUPTS 9.5.1 Detecting Hardware Interrupts Figure 9-2 shows how the hardware interrupt request is detected through the Cause register. -- The timer interrupt signal, IP7, is directly readable as bit 15 of the Cause register. -- Bits 4:0 of the Interrupt register are bit-wise ORed with the current value of the Int(4:0) signals and the result is directly readable as bits 14:10 of the Cause register. IP(1:0) of the Cause register, which are described in Chapter 6, are software interrupts. There is no hardware mechanism for setting or clearing the software interrupts. 232 CHAPTER 9 CPU CORE INTERRUPTS Figure 9-2. Hardware Interrupt Signals 4 3 2 1 0 Interrupt register (4:0) IP2 IP3 IP4 IP5 IP6 Timer interrupt IP7 10 11 12 See Figure 9-3 13 14 15 Cause register (15:10) 4 MasterOut 3 2 1 0 (Internal register) Int3 Int4 Int2 Int1 Int0 Remark Int4 never occurs in the VR4102. 233 CHAPTER 9 CPU CORE INTERRUPTS 9.5.2 Masking Interrupt Signals Figure 9-3 shows the masking of the CPU core interrupt signals. -- Cause register bits 15 to 8 (IP7 to IP0) are AND-ORed with Status register interrupt mask bits 15 to 8 (IM7 to IM0) to mask individual interrupts. -- Status register bit 0 is a global Interrupt Enable bit (IE). It is ANDed with the output of the AND-OR logic to produce the CPU core interrupt signal. The EXL bit in the Status register also enables these interrupts. Figure 9-3. Masking of the CPU Core Interrupts Status register SR (0) IE Status register SR (15:8) 8 IM0 IM1 IM2 IM3 IM4 IM5 IM6 IM7 9 10 11 12 13 14 15 1 Cause register (15:8) 8 IP0 IP1 IP2 IP3 Ordinary interrupts IP4 IP5 IP6 Timer interrupt IP7 9 10 11 12 13 14 15 AND-OR logic 8 AND logic 1 CPU core interrupt 8 Software interrupts generated in CPU core Bit IE Function Interrupt enable for all interrupts 1: Enable 0: Disable Setting IM (7:0) Interrupt mask 1: Enable for individual bits 0: Disable for individual bits IP (7:0) Interrupt request 1: Pending request for individual bits 0: No pending for individual bits 234 CHAPTER 10 BCU (BUS CONTROL UNIT) This chapter describes the BCU's operations and register settings. 10.1 GENERAL In the VR4102, the BCU receives data that has passed via the VR4100 CPU core and the SysAD bus. The BCU also controls external agents via the system bus, such as an LCD controller, DRAM, ROM (Flash memory or masked ROM), or PCMCIA controller, and it transmits and receives data with these external agents via the ADD bus and DATA bus. 10.2 REGISTER SET The BCU registers are listed below. Table 10-1. BCU Registers Address 0x0B00 0000 0x0B00 0002 0x0B00 000A 0x0B00 000C 0x0B00 000E 0x0B00 0010 0x0B00 0012 0x0B00 0014 R/W R/W R/W R/W R/W R/W R R/W R/W Register symbols BCUCNTREG 1 BCUCNTREG 2 BCUSPEEDREG BCUERRSTREG BCURFCNTREG REVIDREG BCURFCOUNTREG CLKSPEEDREG Function BCU Control Register 1 BCU Control Register 2 BCU Access Cycle Change Register BCU BUS ERROR Status Register BCU Refresh Control Register Revision ID Register BCU Refresh Count Register Clock Speed Register Each register is described in detail as follows. 235 CHAPTER 10 BCU (BUS CONTROL UNIT) 10.2.1 BCUCNTREG 1 (0x0B00 0000) (1/2) Bit Name R/W RTCRST Other resets D15 ROM64 R/W 0 0 D14 DRAM64 R/W 0 0 D13 ISAM/LCD R/W 0 0 D12 PAGE128 R/W 0 0 D11 Reserved R 0 0 D10 PAGEROM2 R/W 0 0 D9 Reserved R 0 0 D8 PAGEROM0 R/W 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 ROMWEN2 R/W 0 0 D5 Reserved R 0 0 D4 ROMWEN0 R/W 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 BUSHERREN R/W 0 0 D0 RSTOUT R/W 0 0 Bit D[15] ROM64 Name Function Sets the capacity of the ROM to be used 1: 64M-bit ROM 0: 32M-bit ROM Sets the capacity of the DRAM to be used 1 : 64M-bit DRAM 0 : 16M-bit DRAM Assigns space from 0x0A00 0000 to 0x0AFF FFFF as the physical address space. 1 : As ISA high-speed memory space 0 : As LCD space Sets the maximum burst acceleration size for Page ROM. 1 : 128-bit (16 byte) 0 : 64-bit (8 byte) Write 0 when writing. 0 is returned after a read. This is the page ROM access enable bit for the ROM space in banks 3 and 2 (16-bit mode) or in bank 1 (32-bit mode). 1 : Page ROM 0 : Ordinary ROM Write 0 when writing. 0 is returned after a read. This is the page ROM access enable bit for the ROM space in banks 1 and 0 (16-bit mode) or in bank 0 (32-bit mode). 1 : Page ROM 0 : Ordinary ROM D[14] DRAM64 D[13] ISAM/LCD D[12] PAGE128 D[11] D[10] Reserved PAGEROM2 D[9] D[8] Reserved PAGEROM0 236 CHAPTER 10 BCU (BUS CONTROL UNIT) (2/2) Bit D[7] D[6] Reserved ROMWEN2 Name Function Write 0 when writing. 0 is returned after a read. This enables flash memory write and issues a flash memory register read-only bus cycle for the ROM space in banks 3 and 2 (16-bit mode) or in bank 1 (32-bit mode). 1 : Enable (Not affected by PAGEROM2) 0 : Prohibit Write 0 when writing. 0 is returned after a read. This enables flash memory write and issues a flash memory register read-only bus cycle for the ROM space in banks 1 and 0 (16-bit mode) or in bank 0 (32-bit mode). 1 : Enable (Not affected by PAGEROM0) 0 : Prohibit Write 0 when writing. 0 is returned after a read. This is the bus timeout detection enable bit, which is used when a bus hold has been received. 1 : Performs timeout detection when a bus hold has been received. 0 : Does not perform timeout detection when a bus hold has been received. RSTOUT control bit 1 : High level 0 : Low level D[5] D[4] Reserved ROMWEN0 D[3..2] D[1] Reserved BUSHERREN D[0] RSTOUT This register is used to set parameters such as the bus interface's bus cycle. For the setting of the PAGEROM2 and ROMWEN2 bits, the target ROM area differs depending on a data bus mode. The access target ROM area is banks 3 and 2 in 16-bit data bus mode, and bank 1 in 32-bit data bus mode. For the setting of the PAGEROM0 and ROMWEN0 bits, the target ROM area differs depending on the data bus mode. The access target ROM area is banks 1 and 0 in 16-bit data bus mode, and bank 0 in 32-bit data bus mode. When a timeout is detected while the BUSHERREN bit is set to 1, the BERRST bit of the BCUERRSTREG register is set to 1 and an interrupt request is sent to the CPU. The RSTOUT pin is set to high to request bus release from the external bus master. 237 CHAPTER 10 BCU (BUS CONTROL UNIT) 10.2.2 BCUCNTREG 2 (0x0B00 0002) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 Reserved R 0 0 D0 GMODE R/W 0 0 Bit D[15..1] D[0] Reserved GMODE Name Function Write 0 when writing. 0 is returned after a read. This is the access data control bit for LCD space. 1 : Do not invert the access data for LCD space 0 : Invert the access data for LCD space This register is used to specify whether data is inverted (translated to 2's complement) or not when accessing the LCD space. The LCD space is accessed when the ISAM/LCD bit of BCUCNTREG1 is 0. When it is 1, this address space is used as the ISA high-speed memory space. In this case, the contents of the BCUCNTREG2 register are invalid, and inversion of access data is not performed. 238 CHAPTER 10 BCU (BUS CONTROL UNIT) 10.2.3 BCUSPEEDREG (0x0B00 000A) (1/2) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 WPROM[1] R/W 0 0 D12 WPROM[0] R/W 0 0 D11 Reserved R 0 0 D10 WLCD/M[2] R/W 0 0 D9 WLCD/M[1] R/W 0 0 D8 WLCD/M[0] R/W 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 WISAA [2] R/W 0 0 D5 WISAA [1] R/W 0 0 D4 WISAA [0] R/W 0 0 D3 Reserved R 0 0 D2 WROMA[2] R/W 0 0 D1 WROMA[1] R/W 0 0 D0 WROMA[0] R/W 0 0 Bit D[15..14] D[13..12] Reserved Name Function Write 0 when writing. 0 is returned after a read. Page ROM access speed 11 : RFU 10 : 1TClock 01 : 2TClock 00 : 3TClock Write 0 when writing. 0 is returned after a read. Access speed to physical address space from 0x0A00 0000 to 0x0AFF FFFF LCD(ISAM/LCD=0) ISA-MEM(ISAM/LCD=1) 111 : RFU 1TClock 110 : RFU 2TClock 101 : RFU 3TClock 100 : RFU 4TClock 011 : 2TClock 5TClock 010 : 4TClock 6TClock 001 : 6TClock 7TClock 000 : 8TClock 8TClock Write 0 when writing. 0 is returned after a read. WPROM[1..0] D[11] D[10..8] Reserved WLCD/M[2..0] D[7] Reserved 239 CHAPTER 10 BCU (BUS CONTROL UNIT) (2/2) Bit D[6..4] Name WISAA[2..0] Function System bus access speed 111 : RFU. Operation is not guaranteed when this value has been set. 110 : RFU. Operation is not guaranteed when this value has been set. Note 101 : 3TClock Note 100 : 4TClock 011 : 010 : 001 : 000 : D[3] D[2..0] Reserved WROMA[2..0] 5TClock 6TClock 7TClock 8TClock Write 0 when writing. 0 is returned after a read. ROM access speed 111 : 2TClock 110 : 3TClock 101 : 4TClock 100 : 5TClock 011 : 6TClock 010 : 7TClock 001 : 8TClock 000 : 9TClock Note When the WISAA [2:0] bits are set to 101 or 100, the AC characteristics between BUSCLK and the system bus interface signals (ADD [25:0], SHB#, MEMR#, MEMW#, IOR#, and IOW#) are not guaranteed. This register is used to set the access speed for the LCD, system bus, page ROM, and ROM. The lowest speed is set when "0" is set to all of the following bits: WLCD/M[2..0], WPROM[1..0], WISAA[2..0], and WROMA[2..0]. Setting "1" to all of these bits sets the highest speed. The value set to WPROM[1..0] is valid only when "1" has been set to the PAGEROM bit in BCUCNTREG. 240 CHAPTER 10 BCU (BUS CONTROL UNIT) 10.2.4 BCUERRSTREG (0x0B00 000C) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 Reserved R 0 0 D0 BERRST R/W1C 0 0 Bit D[15..1] D[0] Reserved BERRST Name Function Write 0 when writing. 0 is returned after a read. Bus error status. Clear to 0 when 1 is written. 1 : Bus error 0 : Normal This register is used to indicate when a bus error interrupt request has occurred. 241 CHAPTER 10 BCU (BUS CONTROL UNIT) 10.2.5 BCURFCNTREG (0x0B00 000E) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 BRF[13] R/W 0 Undefined D12 BRF[12] R/W 0 Undefined D11 BRF[11] R/W 0 Undefined D10 BRF[10] R/W 0 Undefined D9 BRF[9] R/W 1 Undefined D8 BRF[8] R/W 0 Undefined Bit Name R/W RTCRST Other resets D7 BRF[7] R/W 0 Undefined D6 BRF[6] R/W 0 Undefined D5 BRF[5] R/W 0 Undefined D4 BRF[4] R/W 0 Undefined D3 BRF[3] R/W 0 Undefined D2 BRF[2] R/W 0 Undefined D1 BRF[1] R/W 0 Undefined D0 BRF[0] R/W 0 Undefined Bit D[15..14] D[13..0] Reserved Name Function Write 0 when writing. 0 is returned after a read. Use this bit to set the number of refresh cycles (with TClock cycle). BRF[13..0] This register is used to specify the number of refresh cycles (with Tclock cycle). 242 CHAPTER 10 BCU (BUS CONTROL UNIT) 10.2.6 REVIDREG (0x0B00 0010) Bit Name R/W RTCRST Other resets D15 RID[3] R 0 0 D14 RID[2] R 0 0 D13 RID[1] R 0 0 D12 RID[0] R 1 1 D11 MJREV[3] R Undefined Undefined D10 MJREV[2] R Undefined Undefined D9 MJREV[1] R Undefined Undefined D8 MJREV[0] R Undefined Undefined Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 MNREV[(3] R Undefined Undefined D2 MNREV[2] R Undefined Undefined D1 MNREV[1] R Undefined Undefined D0 MNREV[0] R Undefined Undefined Bit D[15..12] D[11..8] D[7..4] D[3..0] RID[3:0] Name Function This is the processor revision ID. 0x01 indicates the VR4102. Major revision number Write 0 when writing. 0 is returned after a read. Minor revision number MJREV[3..0] Reserved MNREV[3..0] This register is used to indicate revisions of the VR4102's peripheral units. The revision number is stored as a value in the form y.x, where y is a major revision number and x is a minor revision number. Major revision number and minor revision number can distinguish the revision of the CPU and the peripheral units, however there is no guarantee that changes to the CPU and the peripheral units will necessarily be reflected in this register, or that changes to the revision number necessarily reflect real CPU's and units' changes. For this reason, these values are not listed and software should not rely on the revision number in PREVIDREG to characterize the units. 243 CHAPTER 10 BCU (BUS CONTROL UNIT) 10.2.7 BCURFCOUNTREG (0x0B00 0012) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 BRFC[13] R/W 0 0 D12 BRFC[12] R/W 0 0 D11 BRFC[11] R/W 0 0 D10 BRFC[10] R/W 0 0 D9 BRFC[9] R/W 0 0 D8 BRFC[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 BRFC[7] R/W 0 0 D6 BRFC[6] R/W 0 0 D5 BRFC[5] R/W 0 0 D4 BRFC[4] R/W 0 0 D3 BRFC[3] R/W 0 0 D2 BRFC[2] R/W 0 0 D1 BRFC[1] R/W 0 0 D0 BRFC[0] R/W 0 0 Bit D[15..14] D[13..0] Reserved Name Function Write 0 when writing. 0 is returned after a read. This is the down counter that counts the number of refresh cycles (with TClock cycle). BRFC[13..0] This register is used to indicate the current refresh cycle count value. 244 CHAPTER 10 BCU (BUS CONTROL UNIT) 10.2.8 CLKSPEEDREG (0x0B00 0014) Bit Name R/W RTCRST Other resets D15 DIV2B R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 CLKSP[4] R Undefined Undefined D3 CLKSP[3] R Undefined Undefined D2 CLKSP[2] R Undefined Undefined D1 CLKSP[1] R Undefined Undefined D0 CLKSP[0] R Undefined Undefined Bit D[15] DIV2B Name Function The multiplier of TClock frequency. This bit always indicates 0 in the current VR4102. 1: Reserved 0: Multiplied by 16 Write 0 when writing. 0 is returned after a read. These bits indicate the value used to calculate the frequency of PClock and TClock. D[14..5] D[4..0] Reserved CLKSP[4..0] This register is used to indicate the value to calculate the frequencies of the peripheral unit's operating clock (TClock) and CPU core's operating clock (PClock). The PClock frequency obtained from this register's setting is the same as the frequency selected by setting CLKSEL[2:0] pins. The following method is used to calculate TClock frequency. TClock = (18.432 MHz/CLKSP[4..0])*16 The following method is used to calculate PClock frequency. PClock = (18.432 MHz/CLKSP[4..0])*32 245 CHAPTER 10 BCU (BUS CONTROL UNIT) 10.3 CONNECTION OF ADDRESS PINS Physical address output from the CPU core is provided to external devices through ADD bus. The correspondence between the address output to ADD bus and the address bits of external devices differs depending on the external devices as shown in Table 10-2. Therefore, connect ADD bus and address pin of the external device as shown in Table 10-3. Table 10-2. Address Bit Correspondence between ADD Bus and External Devices Devices connected 0 ROM, LCD, ISA, DRAM (ROW) DRAM (COLUMN), DATA [15:0] DRAM (COLUMN), DATA [31:0] 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 ADD bus 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 19 20 19 20 21 22 23 24 25 0 1 2 3 4 5 6 7 8 21 2 3 4 5 6 7 8 19 20 19 20 21 22 23 24 25 Table 10-3. Address Connection Table with External Devices VR4102 pin 16M-bit DRAM ADD[9] ADD[10] ADD[11] ADD[12] ADD[13] ADD[14] ADD[15] ADD[16] ADD[17] ADD[18] ADD[19] ADD[20] ADD[21] ADD[22] ADD[23] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/NC A11/NC Note 1 Note 1 Address bits of external devices 64M-bit DRAM, DATA[15..0] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A12/NC A10 A11 Note 2 64M-bit DRAM, DATA[31..0] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A12/NC A10 A11 Note 3 Notes 1. A10, A11 : PPD42S16165, NC : PPD42S18165 2. A12 : PPD42S64165, NC : PPD42S65165 3. A12 : PPD42S64165, NC : PPD42S65165 246 CHAPTER 10 BCU (BUS CONTROL UNIT) 10.4 NOTES ON USING BCU 10.4.1 CPU Core Bus Modes The VR4102 is designed on the assumption that the CPU core is set to the following mode. * Writeback data rate :D * Accelerate data ratio : VR4x00 compatible mode Therefore, set the Config Register as below: * * EP : 0000 AD : 0 10.4.2 Access Data Size In the VR4102, access size is restricted for each address space. Access sizes for the following address spaces are listed below. Table 10-4. Access Size Restrictions for Address Spaces Address space R/W 16 ROM/PageROM Flash memory System bus I/O space System bus memory space On-chip I/O space 1 On-chip I/O space 2 LCD space High-speed system bus memory space DRAM R W R/W R/W R/W R/W R/W R/W R/W { u { { { u u u { 8 { u { { { { { { { { { { { { { { Access size (bytes) 4 { 3 { u u u u u u u { { { { { { { { 2 { 1 { u { { { u { { { Notes 2, 3 Note 3 Note 1 Remark Notes 1. The access size when writing to flash memory must be the same as the data bus width such as below; In 32-bit mode: 4 bytes In 16-bit mode: 2 bytes 2. 3. Use as uncached. The LCD space and high-speed system bus memory space are mapped to the same physical address. Use BCUCNTREG1's ISAM/LCD bit to switch between the two. Remark {, : accessible, u : not accessible 247 CHAPTER 10 BCU (BUS CONTROL UNIT) 10.4.3 ROM Interface (1) Switching among ROM, PageROM, and Flash Memory Modes The VR4102 supports three modes (ROM, PageROM and Flash Memory). The mode setting in ROM bank 3/2 is set via BCUCNTREG1's ROMWEN2 and PAGEROM2 bits, and the mode setting in ROM bank 1/0 is set via the ROMWEN0 and PAGEROM0 bits. In Ordinary ROM mode or Flash Memory mode, the VR4102 can access to memories regardless of its mode name. Table 10-5 shows accessible memory types and methods of access in each mode. Table 10-5. Summary of ROM Modes Mode Setting ROMWEN2/0 PAGEROM2/0 Memory read Access-enabled devices Flash Memory register read N/A Flash Memory write N/A Ordinary ROM 0 0 Ordinary ROM PageROM Flash Memory PageROM Ordinary ROM PageROM Flash Memory PageROM Flash Memory 0 1 1 don't care N/A Flash Memory N/A Flash Memory Remark The initial setting is Ordinary ROM mode. (2) Access Speed Setting The VR4102 enables the access speed to be changed when operating in Ordinary ROM mode or PageROM mode. For details, see 10.5.1. 248 CHAPTER 10 BCU (BUS CONTROL UNIT) 10.4.4 Flash Memory Interface (1) Notes for Specific Modes The following two modes are available for flash memory. * Ordinary ROM mode (memory read only) * Flash Memory mode (supports memory write and register read) The following notes apply to these modes. (a) Notes for Ordinary ROM mode * Write is prohibited The WR# pin is not asserted even when a write operation is attempted. * Flash memory register read is prohibited The Ordinary ROM mode is the mode in which bus cycles suite for memory read operations are issued. Since the AC characteristics of flash memory are different for register read and memory read operations, accurate data cannot be obtained by reading the flash memory register while in this mode. (b) Notes for Flash Memory mode * Be sure to access in double-byte units when writing to flash memory. (2) Example of write sequence for flash memory An example of a write sequence for flash memory is shown below. Caution This example's operations have not been confirmed using an actual system. 1 Using GPIO as an output port, apply the flash memory write voltage (VPP). If the VR4102's on-chip GPIOs cannot be used, set up an external output port and then control the write voltage. 2 3 4 5 6 7 Set the VR4102 to flash memory mode (Set "1" to the BCUCNTREG's ROMWEN bit). Wait until the flash memory write voltage become stable. Issue the flash memory write command from the VR4102. Write data from the VR4102 to flash memory. Wait until the flash memory write completion signal (ry/by) becomes stable. Wait until the flash memory write completion signal gives notification of write completion. After write to flash memory is completed, notification can be obtained by receiving an interrupt from the flash memory write completion signal (ry/by) or by polling the flash memory register. 8 Read the flash memory register. * If write succeeded, start processing from "9". * If write failed, start processing from "12". 9 If writing new data to flash memory, start processing from "4". If write to flash memory is completed, start processing from "10". 249 CHAPTER 10 BCU (BUS CONTROL UNIT) 10 Compare the data written to flash memory with the original data. * If the data matches, perform processing at "11". * If the data does not match Start processing from "1" when rewriting. If processing is interrupted, start processing from "11". 11 Reduce the flash memory write voltage (VPP) and end processing after flash memory mode has been canceled. 12 Clear any error data in the flash memory register. * If writing again If the write voltage is too low, start processing from "1". In all other cases, start processing from "4". * If processing is completed, perform processing at "11". 10.4.5 LCD Control Interface (1) Access Size Available access sizes for accessing the LCD controller interface are 1 byte, 2 bytes, 4 bytes, and 8 bytes. (2) Data Inversion When "0" has been set to the BCUCNTREG1's ISAM/LCD bit and to BCUCNTREG2's GMODE bit, the VR4102 inverts the bits in the data being read or written via the LCD controller interface. Table 10-6. Example of Bit Inversion in Data in VR4102 and at DATA [15:0] Pins Data in VR4102 0x0000 0xA5A5 0x1234 Data at DATA [15:0] Pins 0xFFFF 0x5A5A 0xEDCB 250 CHAPTER 10 BCU (BUS CONTROL UNIT) 10.4.6 Illegal Access Notification (1) Types of Illegal Access Under the following circumstances, the VR4102 provides notification concerning illegal access of the CPU core. * Bus deadlock If CBR refresh does not occur at least twice, a deadlock is judged as having occurred due to the non-return of a ready signal via the system bus or LCD controller interface, in which case notification of illegal access is given. * Address space reserved for future use Notification of illegal access is given when the processor has accessed any of the following addresses. 0x0FFF FFFF to 0x0C00 0000 0x09FF FFFF to 0x0400 0000 (2) Notification Method for Illegal Access The methods used to notify the CPU core are listed below. Table 10-7. Illegal Access Notification Methods Access type Processor read request Processor write request Illegal access notification method Notification by bus error caused by SysCmd Notification by interrupt exception (Int0) Remark To clear the interrupt source caused by a processor write request, write "1" to BCUERRSTREG's bit1. 251 CHAPTER 10 BCU (BUS CONTROL UNIT) 10.5 BUS OPERATIONS The bus operations of buses controlled by the BCU are described below. The BCU's operating clock (TClock) appears in the timing chart for each bus operation. Remark # that follows signal names indicates active low. 10.5.1 ROM Access The VR4102 supports the following three modes for ROM access. Use BCUCNTREG1's PAGEROM2/0 bits and ROMWEN2/0 bits to set the mode. x Ordinary ROM read mode (ROMWEN, PAGEROM = 00) x PageROM read mode (ROMWEN, PAGEROM = 01) x Flash Memory mode (ROMWEN = 1) (1) Ordinary ROM Read Mode Set ROMWEN = 0 and PAGEROM = 0. WROMA[2:0] (BCUSPEEDREG [2:0]) can be used to set the access time. Figures 10-1 and 10-2 show 4-byte read timing chart data for when WROMA [2:0] is set to "110". If access uses a data size larger than 4 bytes, the Trom cycle is continued until the required access size is reached. Table 10-8. Access Times during Ordinary ROM Read Mode WROMA [2:0] 000 001 010 011 100 101 110 111 Trom (TClock) 9 8 7 6 5 4 3 2 252 CHAPTER 10 BCU (BUS CONTROL UNIT) Figure 10-1. ROM 4-byte Read, 16-bit Mode (WROMA[2:0] = 110) Trom TClock(internal) ADD[25:0] ROMCS[3:0]# RD# Trom DATA[15:0] Remark The dotted lines indicate high impedance. Figure 10-2. ROM 4-byte Read, 32-bit Mode (WROMA[2:0] = 110) Trom TClock(Internal) ADD[25:0] ROMCS[3:0]# RD# DATA[31:0] Remark The dotted lines indicate high impedance. Data is sampled at the rising edge of the TClock following the last Trom-state TClock. The bus operation types for ordinary ROM are as follows. 1-byte read, 2-byte read, 3-byte read, 1-word read, 2-word read, and 4-word read (1 word = 4 bytes) 253 CHAPTER 10 BCU (BUS CONTROL UNIT) (2) PageROM Read Mode Set ROMWEN = 0 and PAGEROM = 1. WROMA[2:0] (BCUSPEEDREG [2:0]) and WPROM[1:0] (BCUSPEEDREG [13:12]) can be used to set the access time. Figures 10-3 and 10-4 show 16-byte read timing charts for when WROMA [2:0] is set to "111" and WPROM [1:0] is set to "10". The ROMCS[3:0]# and RD# pins are held at low level during Trom cycles. Table 10-9. PageROM Read Mode Access Time WROMA [2:0] 000 001 010 011 100 101 110 111 Trom (TClock) 9 8 7 6 5 4 3 2 WPROM [1:0] 00 01 10 11 Tprom (TClock) 3 2 1 RFU Figure 10-3. PageROM 4-word Read, 16-bit Mode (WROMA[2:0] = 111, WPROM[1:0] = 10) Trom TClock(Internal) ADD[25:0] ROMCS[3:0]# RD# DATA[15:0] Tprom Tprom Tprom Tprom Tprom Tprom Tprom Remark The dotted lines indicate high impedance. 254 CHAPTER 10 BCU (BUS CONTROL UNIT) Figure 10-4. PageROM 4-word Read, 32-bit Mode (WROMA[2:0] = 111, WPROM[1:0] = 10) Trom Tprom Tprom Tprom TClock(Internal) ADD[25:0] ROMCS[3:0]# RD# DATA[31:0] Remark (3) Flash Memory Mode Set ROMWEN = 1. The dotted lines indicate high impedance. This mode is used to meet the electrical characteristics required for writing to flash memory and for accessing the flash register. This mode can also be used to read to flash memory. Note that the access time is constant when in this mode. Figure 10-5. Flash Memory Mode, 2-byte Access Flash Memory mode access cycle TClock(Internal) ADD[25:0] ROMCS[3:0]# RD#/WR# 255 CHAPTER 10 BCU (BUS CONTROL UNIT) 10.5.2 System Bus Access (1) Bus Operations in System Bus WISAA[2:0] (BCUSPEEDREG [6:4]) can be used to set the access time. Table 10-10. System Bus Access Times WISAA [2:0] 000 001 010 011 100 101 110 111 Tisa (TClock) 8 7 6 5 4 3 RFU RFU Figure 10-6. 1-byte Access to Even Address Using 16-bit Bus (WISAA[2:0] = 101) Tisa TClock(Internal) ADD[25:0] SHB# IOCS16# MEMCS16# IOR#/IOW# MEMR#/MEMW# IOCHRDY H Tisa Tisa ZWS# DATA[15:0](Write) DATA[15:0](Read) Remark The dotted lines indicate high impedance. 256 CHAPTER 10 BCU (BUS CONTROL UNIT) Figure 10-7 illustrates 2-byte access when sampling IOCHRDY at high level. If the system bus access time has been set as three TClocks (WISAA[2:0] = 101), the bus cycle will end after waiting for at least 3 TCLocks (Tisa periods) after the ready signal is sampled using IOCHRDY. Sampling of the IOCHRDY signal occurs at the rising edge of the TClock that follows the second or subsequent Tisa period. Figure 10-7. 2-byte Access when Sampling IOCHRDY at High Level Using 16-bit Bus (WISAA[2:0] = 101) Tisa TClock(Internal) ADD[25:0] SHB# IOCS16# MEMCS16# IOR#/IOW# MEMR#/MEMW# IOCHRDY L Tisa Tisa ZWS# DATA[15:0] (Write) DATA[15:0] (Read) Remark The dotted lines indicate high impedance. 257 CHAPTER 10 BCU (BUS CONTROL UNIT) Figures 10-8 and 10-9 show timing charts for 1-byte access. Figure 10-8. 1-byte Access to Odd Address Using 16-bit Bus (WISAA[2:0] = 101) Tisa TClock(Internal) Tisa Tisa ADD[25:0] SHB# IOCS16# MEMCS16# IOR#/IOW# MEMR#/MEMW# IOCHRDY L ZWS# DATA[15:0] (Write) DATA[15:0] (Read) Remark The dotted lines indicate high impedance. Figure 10-9. 1-byte Access to Odd Address Using 8-bit Bus (WISAA[2:0] = 101) Tisa TClock(Internal) Tisa Tisa ADD[25:0] SHB# IOCS16# MEMCS16# IOR#/IOW# MEMR#/MEMW# IOCHRDY L ZWS# DATA[15:0] (Write) DATA[15:0] (Read) Remark The dotted lines indicate high impedance. 258 CHAPTER 10 BCU (BUS CONTROL UNIT) Figures 10-10 and 10-11 illustrate 2-byte access when sampling ZWS# at low level. The bus cycle will end after waiting for at least 1 TCLock (Tisa period) after the ready signal is sampled using ZWS#. Sampling of the ZWS# signal occurs at the rising edge of the TClock that follows the second or subsequent Tisa period. Figure 10-10. 2-byte Access when Sampling ZWS# at Low Level on 16-bit Bus (WISAA[2:0] = 101) Tisa TClock(Internal) Tisa ADD[25:0] SHB# IOCS16# MEMCS16# IOR#/IOW# MEMR#/MEMW# IOCHRDY L ZWS# DATA[15:0] (Write) DATA[15:0] (Read) Remark The dotted lines indicate high impedance. 259 CHAPTER 10 BCU (BUS CONTROL UNIT) Figure 10-11. 2-byte Access when Sampling ZWS# at Low Level on 8-bit Bus (WISAA[2:0] = 101) Tisa TClock(Internal) ADD[25:0] IOCS16# MEMCS16# IOR#/IOW# MEMR#/MEMW# IOCHRDY Tisa Tisa Tisa ZWS# DATA[15:0] (Write) DATA[15:0] (Read) Remark The dotted lines indicate high impedance. (2) Bus Operations in High-Speed System Bus The space of physical address from 0x0A00 0000 to 0x0AFF FFFF can be used as the high-speed system bus memory space by setting the ISAM/LCD bit of BCUCNTREG1. WLCD/M [2:0] (BCUSPEEDREG [10:8]) can be used to set the access time for access to this space, as shown in the table below. Table 10-11. High-Speed System Bus Access Times WLCD/W [2:0] 000 001 010 011 100 101 110 111 Tisa (TClock) 8 7 6 5 4 3 2 1 260 CHAPTER 10 BCU (BUS CONTROL UNIT) Figure 10-12. 2-byte Access on 16-bit Bus (WLCD/M[2:0] = 101) Tisa TClock (internal) ADD (25:0) SHB# LCDCS# MEMCS16# MEMR#/MEMW# L Tisa Tisa IOCHRDY ZWS# DATA (15:0) (Write) DATA (15:0) (Read) Hi-Z Figure 10-13. 1-byte Access on 8-bit Bus (WLCD/M[2:0] = 101) Tisa TClock (internal) ADD (25:0) SHB# LCDCS# MEMCS16# MEMR#/MEMW# H Tisa Tisa IOCHRDY ZWS# DATA (15:0) (Write) DATA (15:0) (Read) Hi-Z 261 CHAPTER 10 BCU (BUS CONTROL UNIT) Figure 10-14. 2-byte Access when Sampling ZWS# at Low Level on 16-bit Bus (WLCD/M[2:0] = 101) Tisa TClock (internal) ADD (25:0) SHB# LCDCS# MEMCS16# MEMR#/MEMW# IOCHRDY ZWS# DATA (15:0) (Write) DATA (15:0) (Read) Hi-z L Tisa Figure 10-15. 1-byte Access when Sampling ZWS# at Low Level on 8-bit Bus (WLCD/M[2:0] = 101) Tisa TClock (internal) ADD (25:0) SHB# LCDCS# MEMCS16# MEMR#/MEMW# IOCHRDY ZWS# DATA (15:0) (Write) DATA (15:0) (Read) Hi-z H Tisa 262 CHAPTER 10 BCU (BUS CONTROL UNIT) 10.5.3 LCD Interface The space of the physical address, from 0x0A00 0000 to 0x0AFF FFFF can be used as the LCD space by setting the ISM/LCD bit of the BCUCNTREG1. WLCD/M[2:0] (BCUSPEEDREG [10:8]) can be used to set the access time. Table 10-12. Access Times for LCD Interface WLCD/M [2:0] 000 001 010 011 100 - 111 Tlcd (TClock) 8 6 4 2 RFU Figure 10-16. 2-byte Access to LCD Controller (WLCD/M[2:0] = 010) Tlcd TClock(Internal) ADD[25:0] LCDCS# RD#/WR# LCDRDY Figure 10-17. 2-byte Access to LCD Controller (WLCD/M[2:0] = 011) Wait cycle insertion via LCDRDY signal Tlcd TClock(Internal) ADD[25:0] SHB# L LCDCS# RD#/WR# LCDRDY DATA[15:0] (Write) DATA[15:0] (Read) Remark The dotted lines indicate high impedance. 263 CHAPTER 10 BCU (BUS CONTROL UNIT) 10.5.4 DRAM Access (EDO Type) The access time is constant for DRAM. Figure 10-18. 4-byte Access to DRAM (16-bit Mode) TClock(Internal) MRAS[3:0]# UCAS#/LCAS# ADD[25:19]/ ADD[8:0] ADD[18:9] Row Row Col. Col. RD#/WR# DATA[15:0] (Read) DATA[15:0] (Write) Data0 Data0 Data1 Data1 Remark The dotted lines indicate high impedance. Figure 10-19. 8-byte Access to DRAM (32-bit Mode) TClock(Internal) MRAS[1:0]# UUCAS#/ULCAS#/ UCAS#/LCAS# ADD[25:19]/ ADD[8:0] ADD[18:9] Row Row Col. Col. RD#/WR# DATA[31:0] (Read) DATA[31:0] (Write) Data0 Data0 Data1 Data1 Remark The dotted lines indicate high impedance. 264 CHAPTER 10 BCU (BUS CONTROL UNIT) Figure 10-20. Byte Read of Odd Address in DRAM (16-bit Mode) TClock(Internal) MRAS[3:0]# UCAS# H LCAS# ADD[20:19] Row ADD[18:9] Row Col. Col. RD# DATA[15:0] Data Remark The dotted lines indicate high impedance. Figure 10-21. Byte Read of Even Address in DRAM (16-bit Mode) T C loc k (Internal) M R A S [3:0]# UCAS# LC A S # H A D D [20 :19] R ow A D D [18 :9] R ow C ol. C ol. RD# D ATA [15:0] D ata Remark The dotted lines indicate high impedance. 265 CHAPTER 10 BCU (BUS CONTROL UNIT) Figure 10-22. Byte Write to Odd Address in DRAM (16-bit Mode) TClock(Internal) MRAS[3:0]# UCAS# H LCAS# ADD[20:19] Row ADD[18:9] Row Col. Col. WR# DATA[15:0] Data Figure 10-23. Byte Write to Even Address in DRAM (16-bit Mode) TClock(Internal) M R AS[3:0]# U CAS# LC AS# H AD D[20:19] R ow AD D[18:9] R ow C ol. C ol. W R# D ATA[15:0] D ata 266 CHAPTER 10 BCU (BUS CONTROL UNIT) 10.5.5 Refresh The VR4102 supports CBR refresh and self refresh. (1) CBR Refresh Figure 10-24. CBR Refresh (16-bit Mode) TClock(Internal) MRAS# UCAS#/LCAS# WR# (2) Self Refresh Figure 10-25. Self Refresh (16-bit Mode) TClock(Internal) MRAS# UCAS#/LCAS# WR# 267 CHAPTER 10 BCU (BUS CONTROL UNIT) 10.5.6 Bus Hold Caution The BUSCLK signal is fixed at low level during execution of the SUSPEND instruction. Consequently, while the SUSPEND instruction is being executed, the bus is being used by an external master device and cannot be used for BUSCLK. Figure 10-26. Bus Hold in Fullspeed Mode (a) Transition to Bus Hold from Ordinary Operation TClock(Internal) MasterOut(Internal) HLDRQ# HLDACK# Note 1 Note 2 BUSCLK (b)Transition to Ordinary Operation from Bus Hold TClock(Internal) MasterOut(Internal) HLDRQ# HLDACK# Note 1 Note 2 BUSCLK Notes 1. UUCAS#/MRAS[3]#, ULCAS#/MRAS[2]#, MRAS[1..0]#, UCAS#, LCAS# 2. SHB#, IOR#, IOW#, MEMR#, MEMW#, RD#, WR#, ADD[25..0], DATA[15..0], DATA[31..16]/GPIO[31..16] (in 32-bit data bus mode) Remark The dotted lines indicate high impedance. 268 CHAPTER 10 BCU (BUS CONTROL UNIT) Figure 10-27. Bus Hold in Suspend Mode (a) Transition to Bus Hold from Ordinary Operation MasterOut(Internal) HLDRQ# HLDACK# Note 1 Note 2 Note 3 L BUSCLK (b) Transition to Ordinary Operation from Bus Hold MasterOut(Internal) HLDRQ# HLDACK# Note 1 Note 2 Note 3 BUSCLK L Notes 1. UUCAS#/MRAS[3]#, ULCAS#/MRAS[2]#, MRAS[1..0]# (in 16-bit data bus mode) MRAS[1..0]# (in 32-bit data bus mode) 2. UCAS#, LCAS# (in 16-bit data bus mode) UUCAS#/MRAS#[3], ULCAS#/MRAS[2]#, UCAS#, LCAS# (in 32-bit data bus mode) 3. SHB#, IOR#, IOW#, MEMR#, MEMW#, RD#, WR#, ADD[25..0], DATA[15..0], DATA[31..16]/GPIO[31..16] (in 32-bit data bus mode) Remark The dotted lines indicate high impedance. 269 [MEMO] 270 CHAPTER 11 DMAAU (DMA ADDRESS UNIT) This chapter describes the DMAAU register's operations and settings. 11.1 GENERAL The DMAAU register controls the DMA addresses for the AIU and IrDA 4-Mbps communication module (FIR). The DMA channel used for each unit can set a DMA start address as any half-word address in the space from 0x0000 0000 to 0x01FF FFFE, and is retained in DRAM as a 2-Kbyte block that starts at the address which is generated by masking the low-order 10 bits of the DMA start address. After a DMA start address is set to the DMA base address register, the VR4102 performs DMA transfer using the registers of DMAAU as below. (1) When the DMA start address is included in the first page of the DMA space 1. The VR4102 starts a DMA transfer after writing the start address to the DMA address register. 2. When the DMA transfer reaches the first page boundary, the VR4102 adds 1 Kbyte to the contents of the DMA base address register, writes the value to the DMA address register, and continues the DMA transfer. 3. When the DMA transfer reaches the second page boundary, the VR4102 writes the contents of the DMA base address register to the DMA address register and continues the DMA transfer. 4. The VR4102 repeats 2. and 3. until all the data is transferred. (2) When the DMA start address is included in the second page of the DMA space 1. The VR4102 starts a DMA transfer after writing the start address to the DMA address register. 2. When the DMA transfer reaches the second page boundary, the VR4102 subtracts 1 Kbyte from the contents of the DMA base address register, writes the value to the DMA address register, and continues the DMA transfer. 3. When the DMA transfer reaches the first page boundary, the VR4102 writes the contents of the DMA base address register to the DMA address register and continues the DMA transfer. 4. The VR4102 repeats 2. and 3. until all the data is transferred. Figure 11-1. DMA Space Used in DMA Transfers (a) When the DMA start address is included in the first page of the DMA space Second page 2 4 6 8 Base address o First page boundary Base address o 1 3 5 7 2 DMA space address DMA space address 4 6 8 First page boundary 1 3 5 7 (b) When the DMA start address is included in the second page of the DMA space Second page Caution DMA operations are not guaranteed if an address overlaps with another DMA buffer. 271 CHAPTER 11 DMAAU (DMA ADDRESS UNIT) 11.2 REGISTER SET The DMAAU registers are listed below. Table 11-1. DMAAU Registers Address 0x0B00 0020 0x0B00 0022 0x0B00 0024 0x0B00 0026 0x0B00 0028 0x0B00 002A 0x0B00 002C 0x0B00 002E 0x0B00 0030 0x0B00 0032 0x0B00 0034 0x0B00 0036 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register Symbols AIUIBALREG AIUIBAHREG AIUIALREG AIUIAHREG AIUOBALREG AIUOBAHREG AIUOALREG AIUOAHREG FIRBALREG FIRBAHREG FIRALREG FIRAHREG Function AIU IN DMA Base Address Register Low AIU IN DMA Base Address Register High AIU IN DMA Address Register Low AIU IN DMA Address Register High AIU OUT DMA Base Address Register Low AIU OUT DMA Base Address Register High AIU OUT DMA Address Register Low AIU OUT DMA Address Register High FIR DMA Base Address Register Low FIR DMA Base Address Register High FIR DMA Address Register Low FIR DMA Address Register High These registers are described in detail below. 272 CHAPTER 11 DMAAU (DMA ADDRESS UNIT) 11.2.1 AIU IN DMA Base Address Registers (1) AIUIBALREG (0x0B00 0020) Bit Name R/W RTCRST Other resets D15 AIUIBA[15] R/W 1 1 D14 AIUIBA[14] R/W 1 1 D13 AIUIBA[13] R/W 1 1 D12 AIUIBA[12] R/W 1 1 D11 AIUIBA[11] R/W 1 1 D10 AIUIBA[10] R/W 0 0 D9 AIUIBA[9] R/W 0 0 D8 AIUIBA[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 AIUIBA[7] R/W 0 0 D6 AIUIBA[6] R/W 0 0 D5 AIUIBA[5] R/W 0 0 D4 AIUIBA[4] R/W 0 0 D3 AIUIBA[3] R/W 0 0 D2 AIUIBA[2] R/W 0 0 D1 AIUIBA[1] R/W 0 0 D0 AIUIBA[0] R 0 0 Bit D[15:1] D[0] Name AIUIBA[15:1] AIUIBA[0] DMA base address [15:1] for AIU input Function DMA base address [0] for AIU input Write 0 when writing. 0 is returned after a read. (2) AIUIBAHREG (0x0B00 0022) Bit Name R/W RTCRST Other resets D15 AIUIBA[31] R 0 0 D14 AIUIBA[30] R 0 0 D13 AIUIBA[29] R 0 0 D12 AIUIBA[28] R 0 0 D11 AIUIBA[27] R 0 0 D10 AIUIBA[26] R 0 0 D9 AIUIBA[25] R 0 0 D8 AIUIBA[24] R/W 1 1 Bit Name R/W RTCRST Other resets D7 AIUIBA[23] R/W 1 1 D6 AIUIBA[22] R/W 1 1 D5 AIUIBA[21] R/W 1 1 D4 AIUIBA[20] R/W 1 1 D3 AIUIBA[19] R/W 1 1 D2 AIUIBA[18] R/W 1 1 D1 AIUIBA[17] R/W 1 1 D0 AIUIBA[16] R/W 1 1 Bit D[15:9] Name AIUIBA[31:25] Function DMA base address [31:25] for AIU input Write 0 when writing. 0 is returned after a read. DMA base address [24:16] for AIU input D[8:0] AIUIBA[24:16] 273 CHAPTER 11 DMAAU (DMA ADDRESS UNIT) AIUIBALREG and AIUIBAHREG are used to set the base addresses for the DMA channel used for audio input (recording). The addresses set to this register become DMA start addresses. The DMA channel used for audio input is retained in DRAM as a 2-Kbyte buffer that starts at the address which is generated by masking the low-order 10 bits of the DMA start address. 274 CHAPTER 11 DMAAU (DMA ADDRESS UNIT) 11.2.2 AIU IN DMA Address Registers (1) AIUIALREG (0x0B00 0024) Bit Name R/W RTCRST Other resets D15 AIUIA[15] R/W 1 1 D14 AIUIA[14] R/W 1 1 D13 AIUIA[13] R/W 1 1 D12 AIUIA[12] R/W 1 1 D11 AIUIA[11] R/W 1 1 D10 AIUIA[10] R/W 0 0 D9 AIUIA[9] R/W 0 0 D8 AIUIA[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 AIUIA[7] R/W 0 0 D6 AIUIA[6] R/W 0 0 D5 AIUIA[5] R/W 0 0 D4 AIUIA[4] R/W 0 0 D3 AIUIA[3] R/W 0 0 D2 AIUIA[2] R/W 0 0 D1 AIUIA[1] R/W 0 0 D0 AIUIA[0] R/W 0 0 Bit D[15:0] Name AIUIA[15:0] Function Next DMA address [15:0] to be accessed for AIU input channel (2) AIUIAHREG (0x0B00 0026) Bit Name R/W RTCRST Other resets D15 AIUIA[31] R 0 0 D14 AIUIA[30] R 0 0 D13 AIUIA[29] R 0 0 D12 AIUIA[28] R 0 0 D11 AIUIA[27] R 0 0 D10 AIUIA[26] R 0 0 D9 AIUIA[25] R 0 0 D8 AIUIA[24] R/W 1 1 Bit Name R/W RTCRST Other resets D7 AIUIA[23] R/W 1 1 D6 AIUIA[22] R/W 1 1 D5 AIUIA[21] R/W 1 1 D4 AIUIA[20] R/W 1 1 D3 AIUIA[19] R/W 1 1 D2 AIUIA[18] R/W 1 1 D1 AIUIA[17] R/W 1 1 D0 AIUIA[16] R/W 1 1 Bit D[15:0] Name AIUIA[31:16] Function Next DMA address [31:16] to be accessed for AIU input channel 275 CHAPTER 11 DMAAU (DMA ADDRESS UNIT) 11.2.3 AIU OUT DMA Base Address Registers (1) AIUOBALREG (0x0B00 0028) Bit Name R/W RTCRST Other resets D15 AIUOBA[15] R/W 1 1 D14 AIUOBA[14] R/W 1 1 D13 AIUOBA[13] R/W 1 1 D12 AIUOBA[12] R/W 1 1 D11 AIUOBA[11] R/W 1 1 D10 AIUOBA[10] R/W 0 0 D9 AIUOBA[9] R/W 0 0 D8 AIUOBA[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 AIUOBA[7] R/W 0 0 D6 AIUOBA[6] R/W 0 0 D5 AIUOBA[5] R/W 0 0 D4 AIUOBA[4] R/W 0 0 D3 AIUOBA[3] R/W 0 0 D2 AIUOBA[2] R/W 0 0 D1 AIUOBA[1] R/W 0 0 D0 AIUOBA[0] R 0 0 Bit D[15:1] D[0] Name AIUOBA[15:1] AIUOBA[0] Function DMA base address [15:1] for AIU output DMA base address [0] for AIU output Write 0 when writing. 0 is returned after a read. (2) AIUOBAHREG (0x0B00 002A) Bit Name R/W RTCRST Other resets D15 AIUOBA[31] R 0 0 D14 AIUOBA[30] R 0 0 D13 AIUOBA[29] R 0 0 D12 AIUOBA[28] R 0 0 D11 AIUOBA[27] R 0 0 D10 AIUOBA[26] R 0 0 D9 AIUOBA[25] R 0 0 D8 AIUOBA[24] R/W 1 1 Bit Name R/W RTCRST Other resets D7 AIUOBA[23] R/W 1 1 D6 AIUOBA[22] R/W 1 1 D5 AIUOBA[21] R/W 1 1 D4 AIUOBA[20] R/W 1 1 D3 AIUOBA[19] R/W 1 1 D2 AIUOBA[18] R/W 1 1 D1 AIUOBA[17] R/W 1 1 D0 AIUOBA[16] R/W 1 1 Bit D[15:9] Name AIUOBA[31:25] Function DMA base address [31:25] for AIU output Write 0 when writing. 0 is returned after a read. DMA base address [24:16] for AIU output D[8:0] AIUOBA[24:16] 276 CHAPTER 11 DMAAU (DMA ADDRESS UNIT) AIUOBALREG and AIUOBAHREG are used to set the base addresses for the DMA channel used for audio output (playback). The addresses set to this register become DMA start addresses. The DMA channel used for audio output is retained in DRAM as a 2-Kbyte buffer that starts at the address which is generated by masking the low-order 10 bits of the DMA start address. 277 CHAPTER 11 DMAAU (DMA ADDRESS UNIT) 11.2.4 AIU OUT DMA Address Registers (1) AIUOALREG (0x0B00 002C) Bit Name R/W RTCRST Other resets D15 AIUOA[15] R/W 1 1 D14 AIUOA[14] R/W 1 1 D13 AIUOA[13] R/W 1 1 D12 AIUOA[12] R/W 1 1 D11 AIUOA[11] R/W 1 1 D10 AIUOA[10] R/W 0 0 D9 AIUOA[9] R/W 0 0 D8 AIUOA[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 AIUOA[7] R/W 0 0 D6 AIUOA[6] R/W 0 0 D5 AIUOA[5] R/W 0 0 D4 AIUOA[4] R/W 0 0 D3 AIUOA[3] R/W 0 0 D2 AIUOA[2] R/W 0 0 D1 AIUOA[1] R/W 0 0 D0 AIUOA[0] R/W 0 0 Bit D[15:0] Name AIUOA[15:0] Function Next DMA address [15:0] to be accessed for AIU output channel (2) AIUOAHREG (0x0B00 002E) Bit Name R/W RTCRST Other resets D15 AIUOA[31] R 0 0 D14 AIUOA[30] R 0 0 D13 AIUOA[29] R 0 0 D12 AIUOA[28] R 0 0 D11 AIUOA[27] R 0 0 D10 AIUOA[26] R 0 0 D9 AIUOA[25] R 0 0 D8 AIUOA[24] R/W 1 1 Bit Name R/W RTCRST Other resets D7 AIUOA[23] R/W 1 1 D6 AIUOA[22] R/W 1 1 D5 AIUOA[21] R/W 1 1 D4 AIUOA[20] R/W 1 1 D3 AIUOA[19] R/W 1 1 D2 AIUOA[18] R/W 1 1 D1 AIUOA[17] R/W 1 1 D0 AIUOA[16] R/W 1 1 Bit D[15:0] Name AIUOA[31:16] Function Next DMA address [31:16] to be accessed for AIU output channel 278 CHAPTER 11 DMAAU (DMA ADDRESS UNIT) 11.2.5 FIR DMA Base Address Registers (1) FIRBALREG (0x0B00 0030) Bit Name R/W RTCRST Other resets D15 FIRBA[15] R/W 1 1 D14 FIRBA[14] R/W 1 1 D13 FIRBA[13] R/W 1 1 D12 FIRBA[12] R/W 1 1 D11 FIRBA[11] R/W 1 1 D10 FIRBA[10] R/W 0 0 D9 FIRBA[9] R/W 0 0 D8 FIRBA[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 FIRBA[7] R/W 0 0 D6 FIRBA[6] R/W 0 0 D5 FIRBA[5] R/W 0 0 D4 FIRBA[4] R/W 0 0 D3 FIRBA[3] R/W 0 0 D2 FIRBA[2] R/W 0 0 D1 FIRBA[1] R/W 0 0 D0 FIRBA[0] R/W 0 0 Bit D[15:0] Name FIRBA[15:0] FIR DMA base address [15:0] Function (2) FIRBAHREG (0x0B00 0032) Bit Name R/W RTCRST Other resets D15 FIRBA[31] R 0 0 D14 FIRBA[30] R 0 0 D13 FIRBA[29] R 0 0 D12 FIRBA[28] R 0 0 D11 FIRBA[27] R 0 0 D10 FIRBA[26] R 0 0 D9 FIRBA[25] R 0 0 D8 FIRBA[24] R/W 1 1 Bit Name R/W RTCRST Other resets D7 FIRBA[23] R/W 1 1 D6 FIRBA[22] R/W 1 1 D5 FIRBA[21] R/W 1 1 D4 FIRBA[20] R/W 1 1 D3 FIRBA[19] R/W 1 1 D2 FIRBA[18] R/W 1 1 D1 FIRBA[17] R/W 1 1 D0 FIRBA[16] R/W 1 1 Bit D[15:9] Name FIRBA[31:25] Function FIR DMA base address [31:25] Write 0 when writing. 0 is returned after a read. FIR DMA base address [24:16] D[8:0] FIRBA[24:16] FIRBALREG and FIRBAHREG are used to set the base addresses for the FIR DMA channel. The addresses set to this register become DMA start addresses. The FIR DMA channel is retained in DRAM as a 2-Kbyte buffer that starts at the address that is generated by masking the low-order 10 bits of the DMA start address. 279 CHAPTER 11 DMAAU (DMA ADDRESS UNIT) 11.2.6 FIR DMA Address Registers (1) FIRALREG (0x0B00 0034) Bit Name R/W RTCRST Other resets D15 FIRA[15] R/W 1 1 D14 FIRA[14] R/W 1 1 D13 FIRA[13] R/W 1 1 D12 FIRA[12] R/W 1 1 D11 FIRA[11] R/W 1 1 D10 FIRA[10] R/W 0 0 D9 FIRA[9] R/W 0 0 D8 FIRA[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 FIRA[7] R/W 0 0 D6 FIRA[6] R/W 0 0 D5 FIRA[5] R/W 0 0 D4 FIRA[4] R/W 0 0 D3 FIRA[3] R/W 0 0 D2 FIRA[2] R/W 0 0 D1 FIRA[1] R/W 0 0 D0 FIRA[0] R/W 0 0 Bit D[15:0] Name FIRA[15:0] Function Next DMA address [15:0] to be accessed by FIR channel (2) FIRAHREG (0x0B00 0036) Bit Name R/W RTCRST Other resets D15 FIRA[31] R 0 0 D14 FIRA[30] R 0 0 D13 FIRA[29] R 0 0 D12 FIRA[28] R 0 0 D11 FIRA[27] R 0 0 D10 FIRA[26] R 0 0 D9 FIRA[25] R 0 0 D8 FIRA[24] R/W 1 1 Bit Name R/W RTCRST Other resets D7 FIRA[23] R/W 1 1 D6 FIRA[22] R/W 1 1 D5 FIRA[21] R/W 1 1 D4 FIRA[20] R/W 1 1 D3 FIRA[19] R/W 1 1 D2 FIRA[18] R/W 1 1 D1 FIRA[17] R/W 1 1 D0 FIRA[16] R/W 1 1 Bit D[15:0] Name FIRA[31:16] Function Next DMA address [31:16] to be accessed by FIR channel 280 CHAPTER 12 DCU (DMA CONTROL UNIT) This chapter describes the DCU register's operations and settings. 12.1 GENERAL The DCU register is used for DMA control. Specifically, it controls acknowledgment from the BCU that handles bus arbitration and DMA requests from the on-chip peripheral I/O units (AIU and FIR). enable/prohibit settings. It also controls DMA 12.2 DMA PRIORITY CONTROL When a conflict occurs between DMA requests sent from on-chip peripheral I/O units, the following priority levels are used to resolve the conflict. These priority levels cannot be changed. Table 12-1. DMA Priority Levels Priority level High n Low Type of DMA operation Audio input (recording) Audio output (playback) FIR transmission/reception 12.3 REGISTER SET The DCU register set is described below. Table 12-2. DCU Registers Address 0x0B00 0040 0x0B00 0042 0x0B00 0044 0x0B00 0046 0x0B00 0048 0x0B00 004A R/W R/W R R/W R/W R/W R/W Register symbols DMARSTREG DMAIDLEREG DMASENREG DMAMSKREG DMAREQREG TDREG Function DMA Reset Register DMA Idle Register DMA Sequencer Enable Register DMA Mask Register DMA Request Register Transfer Direction Register These registers are described in detail below. 281 CHAPTER 12 DCU (DMA CONTROL UNIT) 12.3.1 DMARSTREG (0x0B00 0040) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 Reserved R 0 0 D0 DMARST R/W 0 0 Bit D[15..1] D[0] Reserved DMARST Name Function Write 0 when writing. 0 is returned after a read. Reset DMA controller 0 : Reset 1 : Normal This register is used to reset the DMA controller. 282 CHAPTER 12 DCU (DMA CONTROL UNIT) 12.3.2 DMAIDLEREG (0x0B00 0042) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 Reserved R 0 0 D0 DMAISTAT R 0 0 Bit D[15..1] D[0] Reserved Name Function Write 0 when writing. 0 is returned after a read. Display DMA sequencer status 1 : D_IDLE status 0 : DMA busy DMAISTAT This register is used to display the DMA sequencer status. 283 CHAPTER 12 DCU (DMA CONTROL UNIT) 12.3.3 DMASENREG (0x0B00 0044) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 Reserved R 0 0 D0 DMASEN R/W 0 0 Bit D[15..1] D[0] Reserved DMASEN Name Function Write 0 when writing. 0 is returned after a read. Enable DMA sequencer 1 : Enable 0 : Prohibit This register is used to enable/prohibit the DMA sequencer. 284 CHAPTER 12 DCU (DMA CONTROL UNIT) 12.3.4 DMAMSKREG (0x0B00 0046) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name D7 Reserved D6 Reserved D5 Reserved D4 Reserved D3 DMAMSKAIN D2 DMAMSK AOUT D1 Reserved D0 DMAMSK FOUT R/W RTCRST Other resets R 0 0 R 0 0 R 0 0 R 0 0 R/W 0 0 R/W 0 0 R 0 0 R/W 0 0 Bit D[15..4] D[3] Reserved Name Function Write 0 when writing. 0 is returned after a read. Audio input DMA transfer enable/prohibit 1 : Enable 0 : Prohibit Audio output DMA transfer enable/prohibit 1 : Enable 0 : Prohibit Write 0 when writing. 0 is returned after a read. FIR transmission DMA transfer enable/prohibit 1 : Enable 0 : Prohibit DMAMSKAIN D[2] DMAMSKAOUT D[1] D[0] Reserved DMAMSKFOUT This register is used to enable/prohibit various types of DMA transfers. The DMA transfer enable bits should be set when the units that receive DMA service have been stopped or when there are no pending DMA requests. If any of the above bits are set to a unit while a DMA request is pending for that unit, the CPU's operation will be undefined. 285 CHAPTER 12 DCU (DMA CONTROL UNIT) 12.3.5 DMAREQREG (0x0B00 0048) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 DRQAIN R 0 0 D2 DRQAOUT R 0 0 D1 Reserved R 0 0 D0 DRQFOUT R 0 0 Bit D[15..4] D[3] Reserved DRQAIN Name Function Write 0 when writing. 0 is returned after a read. Audio input DMA transfer request 1 : Request pending 0 : No request Audio output DMA transfer request 1 : Request pending 0 : No request Write 0 when writing. 0 is returned after a read. FIR transmission DMA transfer request 1 : Request pending 0 : No request D[2] DRQAOUT D[1] D[0] Reserved DRQFOUT This register is used to indicate whether or not there are any DMA transfer requests. 286 CHAPTER 12 DCU (DMA CONTROL UNIT) 12.3.6 TDREG (0x0B00 004A) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 Reserved R 0 0 D0 FIR R/W 0 0 Bit D[15..1] D[0] Reserved FIR Name Function Write 0 when writing. 0 is returned after a read. Transfer direction of DMA channel for FIR transmission 1 : I/O o MEM 0 : MEM o I/O This register is used to set the transfer direction of DMA channel for FIR transmission. 287 [MEMO] 288 CHAPTER 13 CMU (CLOCK MASK UNIT) This chapter describes the CMU register's operations and settings. 13.1 GENERAL As various input clocks (ctclock, i_seclk, firclock) are supplied from the CPU to each unit, a masking method enables power consumption to be curtailed in units that are not used. The units for which this masking method are used are the KIU, PIU, AIU, SIU, DSIU, FIR, and HSP (software modem interface) units. The basic functions are described below. 1. 2. 3. Control of TClock supplied to PIU, AIU, SIU, KIU, DSIU, and FIR Control of internal clock (18.432 MHz) supplied to SIU and HSP Control of internal clock (48 MHz) supplied to FIR The initial value is "0", which specifies masking. No clock is supplied unless the CPU writes "1" to CMUCLKMSK register. Figure 13-1. Block Diagram of CMU and Peripheral Blocks cscmub cmuout(15:0) tclk_siu tclk_kiu tclk_piu tclk_aiu BCU piad(3:0) piastbb PMU rst_gab CMU ctclock i_seclk tclk_dsiu i_tclk tclk_fir seclk_siu firclock fclk seclk_hsp 13.2 REGISTER SET The CMU register is listed below. Table 13-1. CMU Register Address 0x0B00 0060 R/W R/W Register symbol CMUCLKMSK CMU Clock Mask Register Function This register is described in detail below. 289 CHAPTER 13 CMU (CLOCK MASK UNIT) 13.2.1 CMUCLKMSK (0x0B00 0060) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 MSKFFIR R/W 0 0 D9 MSKSHSP R/W 0 0 D8 MSKSSIU R/W 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 MSKDSIU R/W 0 0 D4 MSKFIR R/W 0 0 D3 MSKKIU R/W 0 0 D2 MSKAIU R/W 0 0 D1 MSKSIU R/W 0 0 D0 MSKPIU R/W 0 0 Bit D[15:11] D[10] Reserved MSKFFIR Name Function Write 0 when writing. 0 is returned after a read. Supply/mask 48-MHz clock to FIR unit 1 : Supply 0 : Mask Supply/mask 18.432-MHz clock to HSP unit 1 : Supply 0 : Mask Supply/mask 18.432-MHz clock to SIU unit 1 : Supply 0 : Mask Write 0 when writing. 0 is returned after a read. Supply/mask TClock to DSIU unit 1 : Supply 0 : Mask Supply/mask TClock to FIR unit 1 : Supply 0 : Mask Supply/mask TClock to KIU unit 1 : Supply 0 : Mask Supply/mask TClock to AIU unit 1 : Supply 0 : Mask Supply/mask TClock to SIU unit 1 : Supply 0 : Mask Supply/mask TClock to PIU unit 1 : Supply 0 : Mask D[9] MSKSHSP D[8] MSKSSIU D[7:6] D[5] Reserved MSKDSIU D[4] MSKFIR D[3] MSKKIU D[2] MSKAIU D[1] MSKSIU D[0] MSKPIU This register is used to mask the clocks that are supplied to the KIU, PIU, AIU, SIU, DSIU, FIR, and HSP units. 290 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) This chapter describes the ICU register's operations and settings. 14.1 GENERAL The ICU collects interrupt signals from the various on-chip peripheral units and transfers these interrupt signals (Int0, Int1, Int2, Int3, and NMI) to the CPU core. The functions of the ICU's internal blocks are briefly described below. * ADDECICU ... Decodes read/write addresses from the CPU that are used for ICU registers. * REGICU ... This includes a register for interrupt masking. The initial value is "0", which specifies masking. No interrupt signal is supplied to CPU core unless the CPU writes "1" to this register. * OUTICU ... This is the general ICU output that follows masking of interrupts (all output is at the rising edge of I_mclkin). It also controls the interrupt masking signal (doze_mskint) used for settings during Suspend mode, assertion of the general interrupt source signal (int_all), and the memdrv assertion timing signal (doze_memdrv) that is used when resetting from Suspend mode. The signals used to notice interrupt request to the CPU are as below. NMI : battint_intr only Switching between NMI and Int0 is enabled according to this register's settings. Because NMI's interrupt masking cannot be controlled by means of software, switch to Int0 to mask battint_Intr. Int3 Int2 Int1 : hsp_intr only : rtc_long2_intr only : rtc_long1_intr only The IT (interval timer) and HSP interrupts require more responsiveness than do other interrupt sources. Int0 : All other interrupts For details of the interrupt sources, see the register set. 291 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) How an interrupt request is notified to the CPU core is shown below. If an interrupt request occurs in the peripheral units, the corresponding bit in the interrupt indication register of Level 2 (xxxINTREG) is set to 1. The interrupt indication register is ANDed bit-wise with the corresponding interrupt mask register of Level 2 (MxxxINTREG). If the occurred interrupt request is enabled (set to 1) in the mask register, the interrupt request is notified to the interrupt indication register of Level 1 (SYSINTREG) and the corresponding bit is set to 1. At this time, the interrupt requests from the same register of Level 2 are notified to the SYSINTREG as a single interrupt request. Interrupt requests from some units directly set their corresponding bits in the SYSINTREG. The SYSINTREG is ANDed bit-wise with the interrupt mask register of Level 1 (MSYSINTREG). If the interrupt request is enabled by MSYSINTREG (set to 1), a corresponding interrupt request signal is output from the ICU to the CPU core. battint is connected to the NMI or Int0 signal of the CPU core (selected by setting of NMIREG). rtc_long signals are connected to the Int3 signal of the CPU core. The other interrupt requests are connected to the Int0 signal of the CPU core as a one interrupt request. The following figure shows an outline of interrupt control in the ICU. 292 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) Figure 14-1. Interrupt Control Outline Level 2 siuint hspint ledint dozepiuint buserrint SOFTINTREG 5 FIRINTREG 5 MFIRINTREG 4 DSIUINTREG 4 MDSIUINTREG 16 GIUINTLREG MGIUINTLREG GIUINTHREG MGIUINTHREG KIUINTREG 3 MKIUINTREG 7 AIUINTREG MAIUINTREG PIUINTREG MPIUINTREG 6 AND/OR MSYSINT1REG MSYSINT2REG etimerint rtclong1int rtclong2int powerint battint tclkint Note Which of NMI or Int0 is used for battint is selected by setting of NMIREG. Interrupt indication registers Interrupt mask registers AND/OR logic (Checking masks bit by bit and summarizing interrupt requests from the registers) 7 6 AND/OR Int0 (all interrupts except for battintNote and rtclongint) AND/OR Int1 17 (rtclong1int) 16 3 AND/OR 16 16 AND/OR 6 17 AND/OR Int3 (hspint) Int2 (rtclong2int) AND/OR NMI (battintNote) AND/OR 7 SYSINT1REG SYSINT2REG Level 1 293 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.2 REGISTER SET The ICU registers are listed below. Table 14-1. ICU Registers Address 0x0B00 0080 0x0B00 0082 0x0B00 0084 0x0B00 0086 0x0B00 0088 0x0B00 008A 0x0B00 008C 0x0B00 008E 0x0B00 0090 0x0B00 0092 0x0B00 0094 0x0B00 0096 0x0B00 0098 0x0B00 009A 0x0B00 0200 0x0B00 0202 0x0B00 0204 0x0B00 0206 0x0B00 0208 0x0B00 020A R/W R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R/W R/W Register symbols SYSINT1REG PIUINTREG AIUINTREG KIUINTREG GIUINTLREG DSIUINTREG MSYSINT1REG MPIUINTREG MAIUINTREG MKIUINTREG MGIUINTLREG MDSIUINTREG NMIREG SOFTINTREG SYSINT2REG GIUINTHREG FIRINTREG MSYSINT2REG MGIUINTHREG MFIRINTREG Function Level 1 System interrupt register 1 Level 2 PIU interrupt register Level 2 AIU interrupt register Level 2 KIU interrupt register Level 2 GIU interrupt register Low Level 2 DSIU interrupt register Level 1 mask system interrupt register 1 Level 2 mask PIU interrupt register Level 2 mask AIU interrupt register Level 2 mask KIU interrupt register Level 2 mask GIU interrupt register Low Level 2 mask DSIU interrupt register NMI register Software interrupt register Level 1 System interrupt register 2 Level 2 GIU interrupt register High Level 2 FIR interrupt register Level 1 mask system interrupt register 2 Level 2 mask GIU interrupt register High Level 2 mask FIR interrupt register These registers are described in detail below. 294 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.2.1 SYSINT1REG (0x0B00 0080) (1/2) Bit Name D15 Reserved D14 Reserved D13 DOZE PIUINTR R 0 0 D12 Reserved D11 SOFTINTR D10 WRBER RINTR R 0 0 D9 SIUINTR D8 GIUINTR R/W RTCRST Other resets R 0 0 R 0 0 R 0 0 R 0 0 R 0 0 R 0 0 Bit Name D7 KIUINTR D6 AIUINTR D5 PIUINTR D4 Reserved D3 ETIMER INTR R 0 0 D2 RTCL1INTR D1 POWER INTR R 0 0 D0 BATINTR R/W RTCRST Other resets R 0 0 R 0 0 R 0 0 R 0 0 R 0 0 R 0 0 Bit D[15..14] D[13] Reserved Name Function Write 0 when writing. 0 is returned after a read. PIU interrupt during Suspend mode 1 : Occurred 0 : Normal Write 0 when writing. 0 is returned after a read. Software interrupt (occurs by setting the SOFTINTREG) 1 : Occurred 0 : Normal Bus error interrupt 1 : Occurred 0 : Normal SIU interrupt 1 : Occurred 0 : Normal GIU interrupt 1 : Occurred 0 : Normal KIU interrupt 1 : Occurred 0 : Normal AIU interrupt 1 : Occurred 0 : Normal DOZEPIUINTR D[12] D[11] Reserved SOFTINTR D[10] WRBERRINTR D[9] SIUINTR D[8] GIUINTR D[7] KIUINTR D[6] AIUINTR 295 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) (2/2) Bit D[5] PIUINTR Name PIU interrupt 1 : Occurred 0 : Normal Write 0 when writing. 0 is returned after a read. ETIMER interrupt 1 : Occurred 0 : Normal RTCLong1 interrupt 1 : Occurred 0 : Normal PowerSW interrupt 1 : Occurred 0 : Normal Battery interrupt 1 : Occurred 0 : Normal Function D[4] D[3] Reserved ETIMERINTR D[2] RTCL1INTR D[1] POWERINTR D[0] BATINTR This register indicates when various interrupts occur in the VR4102 system. 296 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.2.2 PIUINTREG (0x0B00 0082) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name D7 Reserved D6 PADCMD INTR R 0 0 D5 PADADP INTR R 0 0 D4 PADPAGE1 INTR R 0 0 D3 PADPAGE0 INTR R 0 0 D2 PADDLOST INTR R 0 0 D1 Reserved D0 PENCHG INTR R 0 0 R/W RTCRST Other resets R 0 0 R 0 0 Bit D[15..7] D[6] Reserved Name Function Write 0 when writing. 0 is returned after a read. PIU command scan interrupt. This interrupt occurs when command scan found valid data. 1 : Occurred 0 : Normal PIU AD port scan interrupt. This interrupt occurs when AD port scan found a set of valid data. 1 : Occurred 0 : Normal PIU data buffer page 1 interrupt. This interrupt occurs when a set of valid data is stored in page 1 of data buffer. 1 : Occurred 0 : Normal PIU data buffer page 0 interrupt. This interrupt occurs when a set of valid data is stored in page 0 of data buffer. 1 : Occurred 0 : Normal A/D data timeout interrupt. This interrupt occurs when a set of data did not found within specified time. 1 : Occurred 0 : Normal Write 0 when writing. 0 is returned after a read. Touch panel contact status change interrupt 1: Change has occurred 0: No change PADCMDINTR D[5] PADADPINTR D[4] PADPAGE1INTR D[3] PADPAGE0INTR D[2] PADDLOSTINTR D[1] D[0] Reserved PENCHGINTR This register indicates when various PIU-related interrupts occur. 297 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.2.3 AIUINTREG (0x0B00 0084) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 INTMEND R 0 0 D10 INTM R 0 0 D9 INTMIDLE R 0 0 D8 INTMST R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 INTSEND R 0 0 D2 INTS R 0 0 D1 INTSIDLE R 0 0 D0 Reserved R 0 0 Bit D[15:12] D[11] Reserved INTMEND Name Function Write 0 when writing. 0 is returned after a read. Audio input (MIC) DMA buffer 2 page interrupt 1 : Occurred 0 : Normal Audio input (MIC) DMA buffer 1 page interrupt 1 : Occurred 0 : Normal Audio input (MIC) idle interrupt (received data is lost). This interrupt occurs if valid data exists in MIDATREG when data was received from A/D converter. 1 : Occurred 0 : Normal Audio input (MIC) receive completion interrupt. This interrupt occurs when 10-bit converted data was received from the A/D converter. 1 : Occurred 0 : Normal Write 0 when writing. 0 is returned after a read Audio output (speaker) DMA buffer 2 page interrupt 1 : Occurred 0 : Normal Audio output (speaker) DMA buffer 1 page interrupt 1 : Occurred 0 : Normal Audio output (speaker) idle interrupt (mute). This interrupt occurs if there is no valid data in SODATREG when data was transferred to D/A. 1 : Occurred 0 : Normal Write 0 when writing. 0 is returned after a read D[10] INTM D[9] INTMIDLE D[8] INTMST D[7:4] D[3] Reserved INTSEND D[2] INTS D[1] INTSIDLE D[0] Reserved This register indicates when various AIU-related interrupts occur. 298 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.2.4 KIUINTREG (0x0B00 0086) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 KDATLOST R 0 0 D1 KDATRDY R 0 0 D0 SCANINT R 0 0 Bit D[15..3] D[2] Reserved Name Function Write 0 when writing. 0 is returned after a read. Key scan data lost interrupt 1 : Occurred 0 : Normal Key scan data complete interrupt 1 : Occurred 0 : Normal Key input detect interrupt 1 : Occurred 0 : Normal KDATLOST D[1] KDATRDY D[0] SCANINT This register indicates when various KIU-related interrupts occur. 299 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.2.5 GIUINTLREG (0x0B00 0088) Bit Name R/W RTCRST Other resets D15 INTS[15] R 0 0 D14 INTS[14] R 0 0 D13 INTS[13] R 0 0 D12 INTS[12] R 0 0 D11 INTS[11] R 0 0 D10 INTS[10] R 0 0 D9 INTS[9] R 0 0 D8 INTS[8] R 0 0 Bit Name R/W RTCRST Other resets D7 INTS[7] R 0 0 D6 INTS[6] R 0 0 D5 INTS[5] R 0 0 D4 INTS[4] R 0 0 D3 INTS[3] R 0 0 D2 INTS[2] R 0 0 D1 INTS[1] R 0 0 D0 INTS[0] R 0 0 Bit D[15..0] Name INTS[15..0] Interrupt to GPIO[15..0] pin 1 : Occurred 0 : Normal Function This register indicates when various GIU-related interrupts occur. 300 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.2.6 DSIUINTREG (0x0B00 008A) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 INTDCTS R 0 0 D10 INTSER0 R 0 0 D9 INTSR0 R 0 0 D8 INTST0 R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 Reserved R 0 0 D0 Reserved R 1 1 Bit D[15..12] D[11] Reserved INTDCTS Name Function Write 0 when writing. 0 is returned after a read. DCTS# change interrupt 1 : Occurred 0 : Normal Debug serial receive error interrupt 1 : Occurred 0 : Normal Debug serial receive complete interrupt 1 : Occurred 0 : Normal Debug serial transmit complete interrupt 1 : Occurred 0 : Normal Write 0 when writing. 0 is returned after a read. Write 1 when writing. 1 is returned after a read. D[10] INTSER0 D[9] INTSR0 D[8] INTST0 D[7..1] D[0] Reserved Reserved This register indicates when various DSIU-related interrupts occur. 301 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.2.7 MSYSINT1REG (0x0B00 008C) (1/2) Bit Name D15 Reserved D14 Reserved D13 DOZE PIUINTR R/W 0 0 D12 Reserved D11 SOFTINTR D10 WRBERR INTR R/W 0 0 D9 SIUINTR D8 GIUINTR R/W RTCRST Other resets R 0 0 R 0 0 R 0 0 R/W 0 0 R/W 0 0 R/W 0 0 Bit Name D7 KIUINTR D6 AIUINTR D5 PIUINTR D4 Reserved D3 ETIMER INTR R/W 0 0 D2 RTCL1INTR D1 POWER INTR R/W 0 0 D0 BATINTR R/W RTCRST Other resets R/W 0 0 R/W 0 0 R/W 0 0 R 0 0 R/W 0 0 R/W 0 0 Bit D[15..14] D[13] Reserved Name Function Write 0 when writing. 0 is returned after a read. PIU interrupt enable during suspend mode 1 : Enable 0 : Prohibit Write 0 when writing. 0 is returned after a read. Software interrupt (occurs by setting the SOFTINTREG) enable 1 : Enable 0 : Prohibit Bus error interrupt enable 1 : Enable 0 : Prohibit SIU interrupt enable 1 : Enable 0 : Prohibit GIU interrupt enable 1 : Enable 0 : Prohibit KIU interrupt enable 1 : Enable 0 : Prohibit AIU interrupt enable 1 : Enable 0 : Prohibit DOZEPIUINTR D[12] D[11] Reserved SOFTINTR D[10] WRBERRINTR D[9] SIUINTR D[8] GIUINTR D[7] KIUINTR D[6] AIUINTR 302 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) (2/2) Bit D[5] PIUINTR Name PIU interrupt enable 1 : Enable 0 : Prohibit Write 0 when writing. 0 is returned after a read. ETIMER interrupt enable 1 : Enable 0 : Prohibit RTCLong1 timer interrupt enable 1 : Enable 0 : Prohibit PowerSW interrupt enable 1 : Enable 0 : Prohibit Battery interrupt enable 1 : Enable 0 : Prohibit Function D[4] D[3] Reserved ETIMERINTR D[2] RTCL1INTR D[1] POWERINTR D[0] BATINTR This register is used to mask various interrupts that occur in the VR4102 system. 303 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.2.8 MPIUINTREG (0x0B00 008E) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name D7 Reserved D6 PADCMD INTR R/W 0 0 D5 PADADP INTR R/W 0 0 D4 PADPAGE1 INTR R/W 0 0 D3 PADPAGE0 INTR R/W 0 0 D2 PADDLOST INTR R/W 0 0 D1 Reserved D0 PENCHG INTR R/W 0 0 R/W RTCRST Other resets R 0 0 R 0 0 Bit D[15..7] D[6] Reserved Name Function Write 0 when writing. 0 is returned after a read. PIU command scan interrupt enable 1 : Enable 0 : Prohibit PIU A/D port scan interrupt enable 1 : Enable 0 : Prohibit PIU data buffer page 1 interrupt enable 1 : Enable 0 : Prohibit PIU data buffer page 0 interrupt enable 1 : Enable 0 : Prohibit A/D data timeout interrupt enable 1 : Enable 0 : Prohibit Write 0 when writing. 0 is returned after a read. Touch panel contact status change interrupt enable 1 : Enable 0 : Prohibit PADCMDINTR D[5] PADADPINTR D[4] PADPAGE1INTR D[3] PADPAGE0INTR D[2] PADDLOSTINTR D[1] D[0] Reserved PENCHGINTR This register is used to mask various PIU-related interrupts. 304 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.2.9 MAIUINTREG (0x0B00 0090) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 INTMEND R/W 0 0 D10 INTM R/W 0 0 D9 INTMIDLE R/W 0 0 D8 INTMST R/W 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 INTSEND R/W 0 0 D2 INTS R/W 0 0 D1 INTSIDLE R/W 0 0 D0 Reserved R 0 0 Bit D[15:12] D[11] Reserved INTMEND Name Function Write 0 when writing. 0 is returned after a read. Audio input (MIC) DMA buffer 2 page interrupt enable 1 : Enable 0 : Prohibit Audio input (MIC) DMA buffer 1 page interrupt enable 1 : Enable 0 : Prohibit Audio input (MIC) idle interrupt (received data is lost) enable 1 : Enable 0 : Prohibit Audio input (MIC) receive complete interrupt 1 : Enable 0 : Prohibit Write 0 when writing. 0 is returned after a read. Audio output (speaker) DMA buffer 2 page interrupt enable 1 : Enable 0 : Prohibit Audio output (speaker) DMA buffer 1 page interrupt enable 1 : Enable 0 : Prohibit Audio output (speaker) idle interrupt (mute) enable 1 : Enable 0 : Prohibit Write 0 when writing. 0 is returned after a read. D[10] INTM D[9] INTMIDLE D[8] INTMST D[7:4] D[3] Reserved INTSEND D[2] INTS D[1] INTSIDLE D[0] Reserved This register is used to mask various AIU-related interrupts. 305 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.2.10 MKIUINTREG (0x0B00 0092) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 KDATLOST R/W 0 0 D1 KDATRDY R/W 0 0 D0 SCANINT R/W 0 0 Bit D[15..3] D[2] Reserved Name Function Write 0 when writing. 0 is returned after a read. Key data scan lost interrupt enable 1 : Enable 0 : Prohibit Key scan data complete interrupt enable 1 : Enable 0 : Prohibit Key input detect interrupt enable 1 : Enable 0 : Prohibit KDATLOST D[1] KDATRDY D[0] SCANINT This register is used to mask various KIU-related interrupts. 306 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.2.11 MGIUINTLREG (0x0B00 0094) Bit Name R/W RTCRST Other resets D15 INTS[15] R/W 0 0 D14 INTS[14] R/W 0 0 D13 INTS[13] R/W 0 0 D12 INTS[12] R/W 0 0 D11 INTS[11] R/W 0 0 D10 INTS[10] R/W 0 0 D9 INTS[9] R/W 0 0 D8 INTS[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 INTS[7] R/W 0 0 D6 INTS[6] R/W 0 0 D5 INTS[5] R/W 0 0 D4 INTS[4] R/W 0 0 D3 INTS[3] R/W 0 0 D2 INTS[2] R/W 0 0 D1 INTS[1] R/W 0 0 D0 INTS[0] R/W 0 0 Bit D[15..0] Name INTS[15..0] GPIO[15..0] pin interrupt enable 1 : Enable 0 : Prohibit Function This register is used to mask various GIU-related interrupts. 307 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.2.12 MDSIUINTREG (0x0B00 0096) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 INTDCTS R/W 0 0 D10 INTSER0 R/W 0 0 D9 INTSR0 R/W 0 0 D8 INTST0 R/W 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 Reserved R 0 0 D0 Reserved R 0 0 Bit D[15..12] D[11] Reserved INTDCTS Name Function Write 0 when writing. 0 is returned after a read. DCTS# change interrupt enable 1 : Enable 0 : Prohibit Debug serial data receive error interrupt enable 1 : Enable 0 : Prohibit Debug serial data receive complete interrupt enable 1 : Enable 0 : Prohibit Debug serial data transmit complete interrupt enable 1 : Enable 0 : Prohibit Write 0 when writing. 0 is returned after a read. D[10] INTSER0 D[9] INTSR0 D[8] INTST0 D[7..0] Reserved This register is used to mask various DSIU-related interrupts. 308 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.2.13 NMIREG (0x0B00 0098) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 Reserved R 0 0 D0 NMIORINT R/W 0 0 Bit D[15..1] D[0] Reserved Name Function Write 0 when writing. 0 is returned after a read. Low battery detect interrupt type setting 1 : Int0 0 : NMI NMIORINT This register is used to set the type of interrupt used to notify the VR4100 CPU core when a low battery detect interrupt has occurred. 309 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.2.14 SOFTINTREG (0x0B00 009A) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 SOFTINTR[3] D2 SOFTINTR[2] D1 SOFTINTR[1] D0 SOFTINTR[0] R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 Bit D[15..4] D[3..0] Reserved Name Function Write 0 when writing. 0 is returned after a read. Set/clear software interrupt 1 : Set 0 : Clear SOFTINTR[3..0] This register is used to set software interrupts. Each bit can be set separately, and can cause four types of interrupts. 310 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.2.15 SYSINT2REG (0x0B00 0200) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 DSIUINTR R 0 0 D4 FIRINTR R 0 0 D3 TCLKINTR R 0 0 D2 HSPINTR R 0 0 D1 LEDINTR R 0 0 D0 RTCL2INTR R 0 0 Bit D[15..6] D[5] Reserved DSIUINTR Name Function Write 0 when writing. 0 is returned after a read. DSIU interrupt 1 : Occurred 0 : Normal FIR interrupt 1 : Occurred 0 : Normal TClock counter interrupt 1 : Occurred 0 : Normal HSP interrupt 1 : Occurred 0 : Normal LED interrupt 1 : Occurred 0 : Normal RTCLong2 timer interrupt 1 : Occurred 0 : Normal D[4] FIRINTR D[3] TCLKINTR D[2] HSPINTR D[1] LEDINTR D[0] RTCL2INTR This register indicates when various interrupts occur in the VR4102 system. 311 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.2.16 GIUINTHREG (0x0B00 0202) Bit Name R/W RTCRST Other resets D15 INTS[31] R 0 0 D14 INTS[30] R 0 0 D13 INTS[29] R 0 0 D12 INTS[28] R 0 0 D11 INTS[27] R 0 0 D10 INTS[26] R 0 0 D9 INTS[25] R 0 0 D8 INTS[24] R 0 0 Bit Name R/W RTCRST Other resets D7 INTS[23] R 0 0 D6 INTS[22] R 0 0 D5 INTS[21] R 0 0 D4 INTS[20] R 0 0 D3 INTS[19] R 0 0 D2 INTS[18] R 0 0 D1 INTS[17] R 0 0 D0 INTS[16] R 0 0 Bit D[15..0] Name INTS[31..16] GPIO[31..16] pin interrupt 1 : Occurred 0 : Normal Function This register indicates when various GIU-related interrupts occur. 312 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.2.17 FIRINTREG (0x0B00 0204) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 FIRINT R 0 0 D3 FDPINT[4] R 0 0 D2 FDPINT[3] R 0 0 D1 FDPINT[2] R 0 0 D0 FDPINT[1] R 0 0 Bit D[15..5] D[4] Reserved FIRINT Name Function Write 0 when writing. 0 is returned after a read. Interrupt from FIR unit 1 : Occurred 0 : Normal FIR DMA buffer (receive side) 2 page interrupt 1 : Occurred 0 : Normal FIR DMA buffer (transmit side) 2 page interrupt 1 : Occurred 0 : Normal FIR DMA buffer (receive side) 1 page interrupt 1 : Occurred 0 : Normal FIR DMA buffer (transmit side) 1 page interrupt 1 : Occurred 0 : Normal D[3] FDPINT[4] D[2] FDPINT[3] D[1] FDPINT[2] D[0] FDPINT[1] This register indicates when various FIR-related interrupts occur. When FDPINT[4] or FDPINT[3] is set to 1, the VR4102 stops the DMA requests. When FDPINT[2] or FDPINT[1] is set to 1 during the FDPCNT bit of the DPCNTR register (0x0C00 004C) is set to 1 (DMA buffer 1 page interrupt is enabled), the VR4102 stops the DMA requests. 313 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.2.18 MSYSINT2REG (0x0B00 0206) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 DSIUINTR R/W 0 0 D4 FIRINTR R/W 0 0 D3 TCLKINTR R/W 0 0 D2 HSPINTR R/W 0 0 D1 LEDINTR R/W 0 0 D0 RTCL2INTR R/W 0 0 Bit D[15..6] D[5] Reserved DSIUINTR Name Function Write 0 when writing. 0 is returned after a read. DSIU interrupt enable 1 : Enable 0 : Prohibit FIR interrupt enable 1 : Enable 0 : Prohibit TClock counter interrupt enable 1 : Enable 0 : Prohibit HSP interrupt enable 1 : Enable 0 : Prohibit LED interrupt enable 1 : Enable 0 : Prohibit RTCLong2 timer interrupt enable 1 : Enable 0 : Prohibit D[4] FIRINTR D[3] TCLKINTR D[2] HSPINTR D[1] LEDINTR D[0] RTCL2INTR This register is used to mask various interrupts in the VR4102 system. 314 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.2.19 MGIUINTHREG (0x0B00 0208) Bit Name R/W RTCRST Other resets D15 INTS[31] R/W 0 0 D14 INTS[30] R/W 0 0 D13 INTS[29] R/W 0 0 D12 INTS[28] R/W 0 0 D11 INTS[27] R/W 0 0 D10 INTS[26] R/W 0 0 D9 INTS[25] R/W 0 0 D8 INTS[24] R/W 0 0 Bit Name R/W RTCRST Other resets D7 INTS[23] R/W 0 0 D6 INTS[22] R/W 0 0 D5 INTS[21] R/W 0 0 D4 INTS[20] R/W 0 0 D3 INTS[19] R/W 0 0 D2 INTS[18] R/W 0 0 D1 INTS[17] R/W 0 0 D0 INTS[16] R/W 0 0 Bit D[15..0] Name INTS[31..16] Enable GPIO[31..16] pin interrupt 1 : Enable 0 : Prohibit Function This register is used to mask various GIU-related interrupts. 315 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.2.20 MFIRINTREG (0x0B00 020A) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 FIRINT R/W 0 0 D3 FDPINT[4] R/W 0 0 D2 FDPINT[3] R/W 0 0 D1 FDPINT[2] R/W 0 0 D0 FDPINT[1] R/W 0 0 Bit D[15..5] D4 Reserved FIRINT Name Function Write 0 when writing. 0 is returned after a read. FIR unit interrupt enable 1 : Enable 0 : Prohibit FIR DMA buffer 2 page interrupt (receive side) enable 1 : Enable 0 : Prohibit FIR DMA buffer 2 page interrupt (transmit side) enable 1 : Enable 0 : Prohibit FIR DMA buffer 1 page interrupt (receive side) enable 1 : Enable 0 : Prohibit FIR DMA buffer 1 page interrupt (transmit side) enable 1 : Enable 0 : Prohibit D[3] FDPINT[4] D[2] FDPINT[3] D[1] FDPINT[2] D[0] FDPINT[1] This register is used to mask various FIR-related interrupts. 316 CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 14.3 NOTES FOR REGISTER SETTING There is no register setting flow in relation to the ICU. With regard to the interrupt mask registers, the initial setting is "initial = 0= mask" after start up. Therefore, enough masks must be cleared to provide sufficient interrupts for the CPU's start-up processing. This is always necessary when battint_intr = NMI. The initial setting for battint_intr is "initial = 0 = NMI". A "1" must be written to the register to switch this setting to Int0. soft_intr is a software interrupt that is output to Int0 by setting 1 to the SOFTINTREG register. Writing a "0" clears the interrupt. 317 [MEMO] 318 CHAPTER 15 PMU (POWER MANAGEMENT UNIT) This chapter describes the PMU's operation and register settings. 15.1 GENERAL The PMU performs power management within the VR4102 and controls the power supply throughout the system which includes the VR4102. * Reset control * Shutdown control * Power-on control * Low-power mode control The PMU also performs settings to use the GPIO[12:9], GPIO[3:0] signals as a start-up factor. 15.1.1 Reset Control The operations of the RTC, peripheral units, CPU core, and PMUINTREG bit settings during a reset are listed below. Table 15-1. Bit Operations during Reset Reset type RTC reset RSTSW reset RTC Reset Active Peripheral units Reset Reset CPU core Cold reset Cold reset PMUINTREG RTCRST=1 RSTSW=1 (1) RTC reset When the RTCRST# signal is asserted, the PMU resets all peripheral units including the RTC unit. It also asserts the ccoldresetb and creset signals (internal) and resets the CPU core. In addition, the RTCRST bit in PMUINTREG is set (to "1"). After the CPU is restarted, the RTCRST bit must be checked and cleared (to "0") by software. (2) RSTSW reset When the RSTSW# signal is asserted, the PMU resets all peripheral units except for RTC and PMU. Next, it asserts the ccoldresetb and creset signals (internal) and resets the CPU core. In addition, the RSTSW bit in PMUINTREG is set (to "1"). After the CPU is restarted, the RSTSW bit must be checked and cleared (to "0") by software. 319 CHAPTER 15 PMU (POWER MANAGEMENT UNIT) 15.1.2 Shutdown Control The operations of the RTC, peripheral units, CPU core, and PMUINTREG bit settings during a reset are listed below. Table 15-2. Bit Operations during Shutdown Shutdown type HAL timer shutdown Deadman's SW shutdown Software shutdown Battery low shutdown Battery lock cancel shutdown RTC Active Active Active Active Active Peripheral units Reset Reset Reset Reset Reset CPU core Cold reset Cold reset Cold reset Cold reset Cold reset PMUINTREG HALTIMERRST=1 TIMOUTRST=1 BATTINH=1 - (1) HAL Timer Shutdown After the CPU is activated (following the mode change from Shutdown or Hibernate mode to Fullspeed mode), the software must write "1" to PMUCNTREG's HALTIMERRST bit within about four seconds to clear the HAL timer. If the HAL timer is not reset within about four seconds after the CPU is activated, the PMU resets all peripheral units except for RTC and PMU. Next, it asserts the ccoldresetb and creset signals (internal) and resets the CPU core. In addition, the TIMOUTRST bit in PMUINTREG is set (to "1"). After the CPU is restarted, the TIMOUTRST bit must be checked and cleared (to "0") by software. (2) Deadman's SW Shutdown When the Deadman's SW function is enabled, the software must write "1" to DSUCLRREG's DSWCLR bit each time a Deadman's SW setting is made, to clear the Deadman's SW counter (for details, see Chapter 17). If the Deadman's SW counter is not cleared during a Deadman's SW setting, the PMU resets all peripheral units except for RTC and PMU. Next, it asserts the ccoldresetb and creset signals (internal) and resets the CPU core. In addition, the DMSRST bit in PMUINTREG is set (to "1"). After the CPU is restarted, the DMSRST bit must be checked and cleared (to "0") by software. (3) Software Shutdown When the HIBERNATE instruction is executed, the PMU checks for currently pending interrupts. If there are no pending interrupts, it stops the CPU clock. It then resets all peripheral units except for RTC and PMU. The PMU register contents do not change. 320 CHAPTER 15 PMU (POWER MANAGEMENT UNIT) 15.1.3 Power-on Control The causes of CPU activation (mode change from shutdown mode or Hibernate mode to Fullspeed mode) are called power-on factors. There are twelve power-on factors: a power switch interrupt (POWER), eight types of GPIO activation interrupts (GPIO[12:9], GPIO[3..0]), a DCD interrupt (DCD#), a touch panel interrupt, and an alarm interrupt. Battery low detection is a factor that prevents CPU activation. (1) Activation via Power Switch Interrupt When the POWER signal is asserted, the PMU asserts the POWERON signal and provides external notification that the CPU is being activated. After asserting the POWERON signal, the PMU checks the BATTINH signal and then de-asserts the POWERON signal. If the BATTINH/BATTINT# signal is high ("1"), the PMU cancels peripheral unit reset, then starts the Cold Reset sequence to activate the CPU core. If the BATTINH/BATTINT# signal is low ("0"), the PMU sets "1" to PMUINTREG's BATTINH bit and then performs another shutdown. After the CPU is restarted, the BATTINH bit must be checked and cleared (to "0") by software. Figure 15-1. Activation via Power Switch Interrupt (BATTINH/BATTINT# = 1) RTC(Internal) POWER(i) POWERON(o) MPOWER(o) BATTINH/ BATTINT# (i) H Figure 15-2. Activation via Power Switch Interrupt (BATTINH/BATTINT# = 0) RTC(Internal) POWER(i) POWERON(o) MPOWER(o) L L BATTINH/ BATTINT# (i) 321 CHAPTER 15 PMU (POWER MANAGEMENT UNIT) (2) Activation via GPIO Activation Interrupt When the GPIO[12:9], GPIO[3..0] signal is asserted, the PMU checks the GPIO[12:9], GPIO[3..0]'s activation interrupt enable bit. If GPIO[12:9], GPIO[3..0] activation interrupts are enabled, the PMU asserts the POWERON signal and provides external notification that the CPU is being activated (since the GPIO[12:9], GPIO[2..0] activation enable interrupt bit is cleared after an RTC is reset, the GPIO[12:9], GPIO[2..0] signal cannot be used for activation immediately after an RTC reset. However, activation can occur at the falling edge of the GPIO[3] signal immediately after an RTC reset for GPIO[3] only). The PMU asserts the POWERON signal, then checks the BATTINH/ BATTINT# signal and de-asserts the POWERON signal. When the BATTINH/BATTINT# signal is high ("1"), the PMU cancels peripheral unit reset, then starts the Cold Reset sequence to activate the CPU core. When the BATTINH/BATTINT# signal is low ("0"), the PMU sets "1" to PMUINTREG's BATTINH bit and then performs another shutdown. After the CPU is restarted, the BATTINH bit must be checked and cleared (to "0") by software. The CPU sets "1" to the corresponding GPIOINTR bit in the PMUINTREG regardless of whether activation succeeds or fails. Figure 15-3. Activation via GPIO Activation Interrupt (BATTINH/BATTINT# = 1) RTC(Internal) GPIO[12:9]/ GPIO[3..0](i/o) POWERON(o) MPOWER(o) BATTINH/ BATTINT#(i) Figure 15-4. Activation via GPIO Activation Interrupt (BATTINH/BATTINT# = 0) H RTC(Internal) GPIO[12:9]/ GPIO[3..0](i/o) POWERON(o) MPOWER(o) BATTINH/ BATTINT#(i) L L 322 CHAPTER 15 PMU (POWER MANAGEMENT UNIT) (3) Activation via DCD Interrupt When the DCD# signal is asserted, the PMU asserts the POWERON signal and provides external notification that the CPU is being activated. After asserting the POWERON signal, the PMU checks the BATTINH/BATTINT# signal and then de-asserts the POWERON signal. If the BATTINH/BATTINT# signal is high ("1"), the PMU cancels peripheral unit reset, then starts the Cold Reset sequence to activate the CPU core. If the BATTINH/BATTINT# signal is low ("0"), the PMU sets "1" to PMUINTREG's BATTINH bit and then performs another shutdown. After the CPU is restarted, the BATTINH bit must be checked and cleared (to "0") by software. The PMUINTREG's DCDST bit does not indicate whether a DCD interrupt has occurred but instead reflects the current status of the DCD# pin. Caution While POWERON is active, the PMU cannot recognize changes in the DCD# signal. If the DCD# state when POWERON is active is different from the DCD# state when POWERON is inactive, the change in the DCD# signal is detected only after POWERON is inactive. However, if the DCD# state when POWERON is active is the same as the DCD# state when POWERON is inactive, any changes in the DCD# signal that occur while POWERON is active are not detected. Figure 15-5. Activation via DCD Interrupt (BATTINH/BATTINT# = 1) RTC(Internal) DCD#(i) POWERON(o) MPOWER(o) BATTINH/ BATTINT#(i) H Figure 15-6. Activation via DCD Interrupt (BATTINH/BATTINT# = 0) RTC(Internal) DCD#(i) POWERON(o) MPOWER(o) BATTINH/ BATTINT#(i) L L 323 CHAPTER 15 PMU (POWER MANAGEMENT UNIT) (4) Activation via Alarm Interrupt When the alarm interrupt (alarm_intr) signal is asserted, the PMU asserts the POWERON signal and provides external notification that the CPU is being activated. After asserting the POWERON signal, the PMU checks the BATTINH/BATTINT# signal and then de-asserts the POWERON signal. If the BATTINH/BATTINT# signal is high ("1"), the PMU cancels peripheral unit reset, then starts the Cold Reset sequence to activate the CPU core. If the BATTINH/BATTINT# signal is low ("0"), the PMU sets "1" to PMUINTREG's BATTINH bit and then performs another shutdown. After the CPU is restarted, the BATTINH bit must be checked and cleared (to "0") by software. Figure 15-7. Activation via Alarm Interrupt (BATTINH/BATTINT# = 1) RTC(Internal) alarm_intr(Internal) POWERON(o) MPOWER(o) BATTINH/ BATTINT#(i) H Figure 15-8. Activation via Alarm Interrupt (BATTINH/BATTINT# = 0) RTC(Internal) alarm_intr(Internal) POWERON(o) MPOWER(o) BATTINH/ BATTINT#(i) 15.1.4 Power Mode The VR4102 supports the following four power modes. -- Fullspeed mode -- Standby mode -- Suspend mode -- Hibernate mode Figure 15-9 illustrates the transition between the different power modes. L L 324 CHAPTER 15 PMU (POWER MANAGEMENT UNIT) To set Standby, Suspend, or Hibernate mode from Fullspeed mode, execute a STANDBY, SUSPEND, or HIBERNATE instruction respectively. To set Fullspeed mode from Standby, Suspend, or Hibernate mode, generate an interrupt or perform any reset. Table 15-3 outlines the power modes. Figure 15-9. Power Mode State Transition Standby mode (2) (3) Suspend mode (1) Fullspeed mode (4) (6) (5) Hibernate mode (1) STANDBY instruction & pipeline flash & SysAD idle & PClock high (2) All interrupts (3) SUSPEND instruction & pipeline flash & SysAD idle & PClock high & TClock high & DRAM self refresh (4) BatteryInt POWERON RTCRST Alarm KeyTouch PenTouch GPIO[3..0] GPIO[14..9] DCD# RTCLong (5) HIBERNATE instruction & pipeline flash & SysAD idle & PClock high & TClock high & MasterOut high & DRAM self refresh (6) POWERON Alarm DCD# GPIO[3..0] GPIO[12:9] 325 CHAPTER 15 PMU (POWER MANAGEMENT UNIT) Table 15-3. Power Mode Mode RTC Fullspeed Standby Suspend Hibernate Off On On On On Off Internal peripheral unit ICU On On On Off Off DCU On On Off Off Off others Selectable Note Selectable Off Off Off Note CPU core On Off Off Off Off Note See Chapter 13 for details. (1) Fullspeed Mode In Fullspeed mode, all internal clocks and the bus clock operate. In this mode, all the functions of the VR4102 can be executed. (2) Standby Mode In Standby mode, all internal clocks, other than those provided to the internal peripheral units and the internal timer/interrupt unit of the CPU core, are fixed to high level. To switch to Standby mode from Fullspeed mode, first execute the STANDBY instruction. The VR4102 waits until the SysAD bus (internal) enters idle status after the completion of the WB stage of the STANDBY instruction. Then, the internal clock is shut down, and the pipeline stops. PLL, timer/interrupt clock, internal bus clocks (TClock, MasterOut), and RTC continue to operate. In Standby mode, the processor returns to Fullspeed mode when an interrupt occurs. At this time, the contents of bits indicating the states of pins in the peripheral unit's registers are undefined. The contents of other fields are retained. (3) Suspend Mode In Suspend mode, all internal clocks (including TClock) other than those supplied to the RTC/ICU/PMU internal peripheral units and the internal timer/interrupt unit of the CPU core are fixed to high level. To switch to Suspend mode from Fullspeed mode, first execute the SUSPEND instruction. The VR4102 waits until the SysAD bus (internal) enters idle status after the completion of the WB stage of the SUSPEND instruction, DRAM has entered self-refresh mode, and the MPOWER pin has been made inactive. Then, the internal clocks (including TClock) are shut down, and the pipeline stops. PLL, timer interrupt clock, MasterOut, and RTC continue to operate. If the SUSPEND instruction is executed during DMA transfer, the DRAM transfer is suspended, and operation is undefined. In Suspend mode, the processor returns to Fullspeed mode when an interrupt request from the peripheral units or any resets occur. At this time, the contents of bits indicating the states of pins in the peripheral unit's registers are undefined. The contents of other fields are retained. 326 CHAPTER 15 PMU (POWER MANAGEMENT UNIT) (4) Hibernate Mode In Hibernate mode, all the clocks supplied to internal peripheral units other than RTC/ICU/PMU and to the CPU core are fixed to high level. To switch to Hibernate mode from Fullspeed mode, first execute the HIBERNATE instruction. The VR4102 waits until the SysAD bus (internal) enters idle status after the completion of the WB stage of the HIBERNATE instruction, DRAM has entered self-refresh mode, and the MPOWER pin has been made inactive. Then, the internal clocks (including TClock and MasterOut) are shut down, and the pipeline stops. PLL also stops, but RTC continue to operate. In Hibernate mode, the processor returns to Fullspeed mode when it is alarmed from the RTC, the power-on switch is pressed, or DCD# pin is asserted. At this time, the contents of bits indicating the states of pins in the peripheral unit's registers and caches in the CPU core are undefined. The contents of other fields are retained. 15.2 REGISTER SET The PMU registers are listed below. Table 15-4. PMU Registers Address 0x0B00 00A0 0x0B00 00A2 0x0B00 00A4 0x0B00 00A6 R/W R/W R/W R/W R/W Register symbols PMUINTREG PMUCNTREG PMUINT2REG PMUCNT2REG Function PMU Interrupt/Status Register PMU Control Register PMU Interrupt Register 2 PMU Control Register 2 Each register is described in detail below. 327 CHAPTER 15 PMU (POWER MANAGEMENT UNIT) 15.2.1 PMUINTREG (0x0B00 00A0) (1/2) Bit Name R/W RTCRST Other resets D15 GPIO3INTR R/W 0 0 D14 GPIO2INTR R/W 0 0 D13 GPIO1INTR R/W 0 0 D12 GPIO0INTR R/W 0 0 D11 Reserved R 0 0 D10 DCDST R 0 0 D9 RTCINTR R/W 0 0 D8 BATTINH R/W 0 0 Bit Name D7 BATTLOCK D6 CARDLOCK D5 TIMOUTRST D4 RTCRST D3 RSTSW D2 DMSRST D1 BATTINTR D0 POWERSW INTR R/W 0 0 R/W RTCRST Other resets R/W 0 0 R/W 0 0 R/W 0 0 R/W 1 0 R/W 0 0 R/W 0 0 R/W 0 0 Bit D[15] Name GPIO3INTR Function GPIO[3] activation interrupt detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected GPIO[2] activation interrupt detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected GPIO[1] activation interrupt detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected GPIO[0] activation interrupt detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected Write 0 when writing. 0 is returned after a read. DCD# pin state. 1 : High 0 : Low RTC alarm interrupt detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected Battery low detection during activation. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected D[14] GPIO2INTR D[13] GPIO1INTR D[12] GPIO0INTR D[11] D[10] Reserved DCDST D[9] RTCINTR D[8] BATTINH 328 CHAPTER 15 PMU (POWER MANAGEMENT UNIT) (2/2) Bit D[7] Name BATTLOCK Battery lock interrupt detection 1 : Detected 0 : Not detected D[6] CARDLOCK PCMCIA card lock interrupt detection 1 : Detected 0 : Not detected D[5] TIMOUTRST HAL timer reset detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected RTC reset detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected RESET switch interrupt detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected Deadman's switch interrupt detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected Battery low detection during normal operation. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected POWER switch interrupt detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected Note Note Function D[4] RTCRST D[3] RSTSW D[2] DMSRST D[1] BATTINTR D[0] POWERSWINTR Note These bits are used by software. hardware. These are never set by hardware, and their settings never affect This register is used to set whether the CPU detects a power-on factor and reset. It also indicates the status of the DCD# pin. 329 CHAPTER 15 PMU (POWER MANAGEMENT UNIT) 15.2.2 PMUCNTREG (0x0B00 00A2) (1/2) Bit Name R/W RTCRST Other resets D15 GPIO3MSK R/W 1 Note D14 GPIO2MSK R/W 0 Note D13 GPIO1MSK R/W 0 Note D12 GPIO0MSK R/W 0 Note D11 GPIO3TRG R/W 1 Note D10 GPIO2TRG R/W 0 Note D9 GPIO1TRG R/W 0 Note D8 GPIO0TRG R/W 0 Note Bit Name D7 STANDBY D6 Reserved D5 Reserved D4 Reserved D3 Reserved D2 HALTIMER RST R/W 0 0 D1 Reserved D0 Reserved R/W RTCRST Other resets R/W 0 0 R 0 0 R 0 0 R 0 0 R 0 0 R 1 1 R 0 0 Bit D[15] Name GPIO3MSK GPIO[3] activation enable 1 : Enable 0 : Prohibit GPIO[2] activation enable 1 : Enable 0 : Prohibit GPIO[1] activation enable 1 : Enable 0 : Prohibit GPIO[0] activation enable 1 : Enable 0 : Prohibit GPIO[3] activation interrupt type 1 : Falling edge detection 0 : Rising edge detection GPIO[2] activation interrupt type 1 : Falling edge detection 0 : Rising edge detection GPIO[1] activation interrupt type 1 : Falling edge detection 0 : Rising edge detection GPIO[0] activation interrupt type 1 : Falling edge detection 0 : Rising edge detection Function D[14] GPIO2MSK D[13] GPIO1MSK D[12] GPIO0MSK D[11] GPIO3TRG D[10] GPIO2TRG D[9] GPIO1TRG D[8] GPIO0TRG D[7] STANDBY Standby mode setting. This setting is performed only for software, and does not affect hardware in any way. 1 : Standby mode 0 : Normal mode Note Holds the value before reset 330 CHAPTER 15 PMU (POWER MANAGEMENT UNIT) (2/2) Bit D[6..3] D[2] Reserved HALTIMERRST Name Function Write 0 when writing. 0 is returned after a read. HAL timer reset 1 : Reset 0 : Set Write 1 when writing. 1 is returned after a read. Write 0 when writing. 0 is returned after a read. D[1] D[0] Reserved Reserved This register is used to set CPU shutdown and overall system management operations. The HALTIMERRST bit must be reset within about four seconds of activation. Resetting of the HALTIMERRST bit indicates that the VR4102 itself has been activated normally. If the HALTIMERRST bit is not reset within about four seconds of activation, program execution is regarded as abnormal (possibly due to a runaway) and an automatic shutdown is performed. The GPIO[3..0]MSK bits are used to set enable/prohibit for activation from Hibernate mode when the corresponding interrupt (GPIO[3..0]) occurs. The GPIO3MSK bit is set to 1 by RTCRST, and the other bits are cleared to "0" (prohibit). Accordingly, the GPIO[2..0] cannot be used for activation immediately after an RTCRST reset. The GPIO activation interrupt is valid only when the CPU's operation mode is Hibernate mode. 331 CHAPTER 15 PMU (POWER MANAGEMENT UNIT) 15.2.3 PMUINT2REG (0x0B00 00A4) Bit Name R/W RTCRST Other resets D15 D14 D13 D12 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 GPIO12INTR GPIO11INTR GPIO10INTR GPIO9INTR R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 Reserved R 0 0 D0 Reserved R 0 0 Bit D[15] Name GPIO12INTR Function GPIO[12] activation interrupt request detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected GPIO[11] activation interrupt request detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected GPIO[10] activation interrupt request detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected GPIO[9] activation interrupt request detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected Write 0 when writing. 0 is returned after a read. D[14] GPIO11INTR D[13] GPIO10INTR D[12] GPIO9INTR D[11:0] Reserved This register is used to specify whether the GPIO[12:9] interrupt is detected as a power-on factor. 332 CHAPTER 15 PMU (POWER MANAGEMENT UNIT) 15.2.4 PMUCNT2REG (0x0B00 00A6) Bit Name R/W RTCRST Other resets D15 D14 D13 D12 GPIO9MSK R/W 0 0 D11 D10 D9 D8 GPIO9TRG R/W 0 0 GPIO12MSK GPIO11MSK GPIO10MSK R/W 0 0 R/W 0 0 R/W 0 0 GPIO12TRG GPIO11TRG GPIO10TRG R/W 0 0 R/W 0 0 R/W 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 Reserved R 0 0 D0 Reserved R 0 0 Bit D[15] Name GPIO12MSK GPIO[12] activation enable 1 : Enable 0 : Prohibit GPIO[11] activation enable 1 : Enable 0 : Prohibit GPIO[10] activation enable 1 : Enable 0 : Prohibit GPIO[9] activation enable 1 : Enable 0 : Prohibit GPIO[12] activation interrupt type 1 : Falling edge detection 0 : Rising edge detection GPIO[11] activation interrupt type 1 : Falling edge detection 0 : Rising edge detection GPIO[11] activation interrupt type 1 : Falling edge detection 0 : Rising edge detection GPIO[9] activation interrupt type 1 : Falling edge detection 0 : Rising edge detection Function D[14] GPIO11MSK D[13] GPIO10MSK D[12] GPIO9MSK D[11] GPIO12TRG D[10] GPIO11TRG D[9] GPIO10TRG D[8] GPIO9TRG D[7:0] Reserved Write 0 when writing. 0 is returned after a read. This register is used to specify the settings for activation via GPIO [12:9] interrupts. The GPIO activation interrupt is valid only when the CPU's operation mode is Hibernate mode. 333 [MEMO] 334 CHAPTER 16 RTC (REALTIME CLOCK UNIT) This chapter describes the RTC unit's operations and register settings. 16.1 GENERAL The RTC unit has a total of four timers, including the following three types. * RTCLong ... This is a 24-bit programmable counter that counts down using 32.768-kHz cycles. Cycle interrupts occur for up to 512 seconds. The RTC unit includes two RTCLong timers. * TClockCount ... This is a 25-bit programmable counter that counts down using TClock cycles. Cycle interrupts occur for up to 1 to 2 seconds. This counter is used for performance evaluation. * ElapsedTime ... This is a 48-bit up counter that counts up using 32.768-kHz cycles. It counts up to 272 years before returning to zero. It includes 48-bit comparators (ECMPHREG, ECMPLREG, and ECMPMREG) and 48-bit alarm time registers (ETIMELREG, ETIMEMREG, and ETIMEHREG) to enable interrupts to occur at specified times. 335 CHAPTER 16 RTC (REALTIME CLOCK UNIT) 16.2 REGISTER SET The RTC registers are listed below. Table 16-1. RTC Registers Address 0x0B00 00C0 0x0B00 00C2 0x0B00 00C4 0x0B00 00C8 0x0B00 00CA 0X0B00 00CC 0x0B00 00D0 0x0B00 00D2 0x0B00 00D4 0x0B00 00D6 0x0B00 00D8 0x0B00 00DA 0x0B00 00DC 0x0B00 00DE 0x0B00 01C0 0x0B00 01C2 0x0B00 01C4 0x0B00 01C6 0x0B00 01DE R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R R R/W R/W R R R/W Register Symbols ETIMELREG ETIMEMREG ETIMEHREG ECMPLREG ECMPMREG ECMPHREG RTCL1LREG RTCL1HREG RTCL1CNTLREG RTCL1CNTHREG RTCL2LREG RTCL2HREG RTCL2CNTLREG RTCL2CNTHREG TCLKLREG TCLKHREG TCLKCNTLREG TCLKCNTHREG RTCINTREG Elapsed Time L Register Elapsed Time M Register Elapsed Time H Register Elapsed Compare L Register Elapsed Compare M Register Elapsed Compare H Register RTC Long 1 L Register RTC Long 1 H Register RTC Long 1 Count L Register RTC Long 1 Count H Register RTC Long 2 L Register RTC Long 2 H Register RTC Long 2 Count L Register RTC Long 2 Count H Register TCLK L Register TCLK H Register TCLK Count L Register TCLK Count H Register RTC Interrupt Register Function Each register is described in detail below. 336 CHAPTER 16 RTC (REALTIME CLOCK UNIT) 16.2.1 Elapsed Time Registers (1) ETIMELREG (0x0B00 00C0) Bit Name R/W RTCRST Other resets D15 ETIME[15] R/W 0 Note D14 ETIME[14] R/W 0 Note D13 ETIME[13] R/W 0 Note D12 ETIME[12] R/W 0 Note D11 ETIME[11] R/W 0 Note D10 ETIME[10] R/W 0 Note D9 ETIME[9] R/W 0 Note D8 ETIME[8] R/W 0 Note Bit Name R/W RTCRST Other resets D7 ETIME[7] R/W 0 Note D6 ETIME[6] R/W 0 Note D5 ETIME[5] R/W 0 Note D4 ETIME[4] R/W 0 Note D3 ETIME[3] R/W 0 Note D2 ETIME[2] R/W 0 Note D1 ETIME[1] R/W 0 Note D0 ETIME[0] R/W 0 Note Bit D[15:0] Name ETIME[15:0] ElapsedTime bit [15:0] Function Note Continues counting (2) ETIMEMREG (0x0B00 00C2) Bit Name R/W RTCRST Other resets D15 ETIME[31] R/W 0 Note D14 ETIME[30] R/W 0 Note D13 ETIME[29] R/W 0 Note D12 ETIME[28] R/W 0 Note D11 ETIME[27] R/W 0 Note D10 ETIME[26] R/W 0 Note D9 ETIME[25] R/W 0 Note D8 ETIME[24] R/W 0 Note Bit Name R/W RTCRST Other resets D7 ETIME[23] R/W 0 Note D6 ETIME[22] R/W 0 Note D5 ETIME[21] R/W 0 Note D4 ETIME[20] R/W 0 Note D3 ETIME[19] R/W 0 Note D2 ETIME[18] R/W 0 Note D1 ETIME[17] R/W 0 Note D0 ETIME[16] R/W 0 Note Bit D[15:0] Name ETIME[31:16] ElapsedTime bit [31:16] Function Note Continues counting 337 CHAPTER 16 RTC (REALTIME CLOCK UNIT) (3) ETIMEHREG (0x0B00 00C4) Bit Name R/W RTCRST Other resets D15 ETIME[47] R/W 0 Note D14 ETIME[46] R/W 0 Note D13 ETIME[45] R/W 0 Note D12 ETIME[44] R/W 0 Note D11 ETIME[43] R/W 0 Note D10 ETIME[42] R/W 0 Note D9 ETIME[41] R/W 0 Note D8 ETIME[40] R/W 0 Note Bit Name R/W RTCRST Other resets D7 ETIME[39] R/W 0 Note D6 ETIME[38] R/W 0 Note D5 ETIME[37] R/W 0 Note D4 ETIME[36] R/W 0 Note D3 ETIME[35] R/W 0 Note D2 ETIME[34] R/W 0 Note D1 ETIME[33] R/W 0 Note D0 ETIME[32] R/W 0 Note Bit D[15:0] Name ETIME[47:32] ElapsedTime bit [47:32] Function Note Continues counting These registers indicate the elapsed timer's value. They count up using a 32.768-kHz cycle and when a match occurs with the elapsed compare registers, an alarm (elapsed time interrupt) occurs (and the count-up continues). A write operation is valid once values have been written to all registers (ETIMELREG, ETIMEMREG, and ETIMEHREG). 338 CHAPTER 16 RTC (REALTIME CLOCK UNIT) 16.2.2 Elapsed Time Compare Registers (1) ECMPLREG (0x0B00 00C8) Bit Name R/W RTCRST Other resets D15 ECMP[15] R/W 0 Note D14 ECMP[14] R/W 0 Note D13 ECMP[13] R/W 0 Note D12 ECMP[12] R/W 0 Note D11 ECMP[11] R/W 0 Note D10 ECMP[10] R/W 0 Note D9 ECMP[9] R/W 0 Note D8 ECMP[8] R/W 0 Note Bit Name R/W RTCRST Other resets D7 ECMP[7] R/W 0 Note D6 ECMP[6] R/W 0 Note D5 ECMP[5] R/W 0 Note D4 ECMP[4] R/W 0 Note D3 ECMP[3] R/W 0 Note D2 ECMP[2] R/W 0 Note D1 ECMP[1] R/W 0 Note D0 ECMP[0] R/W 0 Note Bit D[15:0] Name ECMP[15:0] Function Value to be compared with ElapsedTime bit [15:0] Note Previous value is retained (2) ECMPMREG (0x0B00 00CA) Bit Name R/W RTCRST Other resets D15 ECMP[31] R/W 0 Note D14 ECMP[30] R/W 0 Note D13 ECMP[29] R/W 0 Note D12 ECMP[28] R/W 0 Note D11 ECMP[27] R/W 0 Note D10 ECMP[26] R/W 0 Note D9 ECMP[25] R/W 0 Note D8 ECMP[24] R/W 0 Note Bit Name R/W RTCRST Other resets D7 ECMP[23] R/W 0 Note D6 ECMP[22] R/W 0 Note D5 ECMP[21] R/W 0 Note D4 ECMP[20] R/W 0 Note D3 ECMP[19] R/W 0 Note D2 ECMP[18] R/W 0 Note D1 ECMP[17] R/W 0 Note D0 ECMP[16] R/W 0 Note Bit D[15:0] Name ECMP[31:16] Function Value to be compared with ElapsedTime bit [31:16] Note Previous value is retained 339 CHAPTER 16 RTC (REALTIME CLOCK UNIT) (3) ECMPHREG (0x0B00 00CC) Bit Name R/W RTCRST Other resets D15 ECMP[47] R/W 0 Note D14 ECMP[46] R/W 0 Note D13 ECMP[45] R/W 0 Note D12 ECMP[44] R/W 0 Note D11 ECMP[43] R/W 0 Note D10 ECMP[42] R/W 0 Note D9 ECMP[41] R/W 0 Note D8 ECMP[40] R/W 0 Note Bit Name R/W RTCRST Other resets D7 ECMP[39] R/W 0 Note D6 ECMP[38] R/W 0 Note D5 ECMP[37] R/W 0 Note D4 ECMP[36] R/W 0 Note D3 ECMP[35] R/W 0 Note D2 ECMP[34] R/W 0 Note D1 ECMP[33] R/W 0 Note D0 ECMP[32] R/W 0 Note Bit D[15:0] Name ECMP[47:32] Function Value to be compared with ElapsedTime bit [47:32] Note Previous value is retained Use these registers to set the values to be compared with values in the elapsed time registers. 340 CHAPTER 16 RTC (REALTIME CLOCK UNIT) 16.2.3 RTC Long 1 Registers (1) RTCL1LREG (0x0B00 00D0) Bit Name R/W RTCRST Other resets D15 RTCL1P[15] R/W 0 Note D14 RTCL1P[14] R/W 0 Note D13 RTCL1P[13] R/W 0 Note D12 RTCL1P[12] R/W 0 Note D11 RTCL1P[11] R/W 0 Note D10 RTCL1P[10] R/W 0 Note D9 RTCL1P[9] R/W 0 Note D8 RTCL1P[8] R/W 0 Note Bit Name R/W RTCRST Other resets D7 RTCL1P[7] R/W 0 Note D6 RTCL1P[6] R/W 0 Note D5 RTCL1P[5] R/W 0 Note D4 RTCL1P[4] R/W 0 Note D3 RTCL1P[3] R/W 0 Note D2 RTCL1P[2] R/W 0 Note D1 RTCL1P[1] R/W 0 Note D0 RTCL1P[0] R/W 0 Note Bit D[15:0] Name RTCL1P[15:0] [15:0] for RTCLong1 counter cycle Function Note Previous value is retained 341 CHAPTER 16 RTC (REALTIME CLOCK UNIT) (2) RTCL1HREG (0x0B00 00D2) Bit Name R/W RTCRST Other resets D15 Reserved R 0 Note D14 Reserved R 0 Note D13 Reserved R 0 Note D12 Reserved R 0 Note D11 Reserved R 0 Note D10 Reserved R 0 Note D9 Reserved R 0 Note D8 Reserved R 0 Note Bit Name R/W RTCRST Other resets D7 RTCL1P[23] R/W 0 Note D6 RTCL1P[22] R/W 0 Note D5 RTCL1P[21] R/W 0 Note D4 RTCL1P[20] R/W 0 Note D3 RTCL1P[19] R/W 0 Note D2 RTCL1P[18] R/W 0 Note D1 D0 RTCL1P[17] RTCL1P[16] R/W 0 Note R/W 0 Note Bit D[15:8] D[7:0] Reserved Name Function Write 0 when writing. 0 is returned after a read. [23:16] for RTCLong1 counter cycle RTCL1P[23:16] Note Previous value is retained Use these registers to set the RTCLong1 counter cycle. The RTCLong1 counter begins its countdown at the value written to these registers. A write operation is valid once values have been written to both registers (RTCL1LREG and RTCL1HREG). Cautions 1. The RTC unit is stopped when all zeros are written. 2. Any combined setting of "RTCL1HREG = 0x0000" and 0x0003, 0x0004" is prohibited. "RTCL1LREG = 0x0001, 0x0002, 342 CHAPTER 16 RTC (REALTIME CLOCK UNIT) 16.2.4 RTC Long 1 Count Registers (1) RTCL1CNTLREG (0x0B00 00D4) Bit Name R/W RTCRST Other resets D15 D14 D13 D12 D11 D10 D9 RTCL1C[9] R 0 Note D8 RTCL1C[8] R 0 Note RTCL1C[15] RTCL1C[14] RTCL1C[13] RTCL1C[12] RTCL1C[11] RTCL1C[10] R 0 Note R 0 Note R 0 Note R 0 Note R 0 Note R 0 Note Bit Name R/W RTCRST Other resets D7 RTCL1C[7] R 0 Note D6 RTCL1C[6] R 0 Note D5 RTCL1C[5] R 0 Note D4 RTCL1C[4] R 0 Note D3 RTCL1C[3] R 0 Note D2 RTCL1C[2] R 0 Note D1 RTCL1C[1] R 0 Note D0 RTCL1C[0] R 0 Note Bit D[15:0] Name RTCL1C[15:0] RTCLong1 counter bit [15:0] Function Note Continues counting 343 CHAPTER 16 RTC (REALTIME CLOCK UNIT) (2) RTCL1CNTHREG (0x0B00 00D6) Bit Name R/W RTCRST Other resets D15 Reserved R 0 Note D14 Reserved R 0 Note D13 Reserved R 0 Note D12 Reserved R 0 Note D11 Reserved R 0 Note D10 Reserved R 0 Note D9 Reserved R 0 Note D8 Reserved R 0 Note Bit Name R/W RTCRST Other resets D7 D6 D5 D4 D3 D2 D1 D0 RTCL1C[23] RTCL1C[22] RTCL1C[21] RTCL1C[20] RTCL1C[19] RTCL1C[18] RTCL1C[17] RTCL1C[16] R 0 Note R 0 Note R 0 Note R 0 Note R 0 Note R 0 Note R 0 Note R 0 Note Bit D[15:8] D[7:0] Reserved Name Function Write 0 when writing. 0 is returned after a read. RTCLong1 counter bit [23:16] RTCL1C[23:16] Note Continues counting These registers indicate the RTCLong1 counter's values. The countdown uses a 32.768-kHz cycle and begins at the value set to the RTCLong1 registers. An RTCLong1 interrupt occurs when the counter reaches 0x00 0001 (at which point the counter returns to the start value and continues counting). 344 CHAPTER 16 RTC (REALTIME CLOCK UNIT) 16.2.5 RTC Long 2 Registers (1) RTCL2LREG (0x0B00 00D8) Bit Name R/W RTCRST Other resets D15 RTCL2P[15] R/W 0 Note D14 RTCL2P[14] R/W 0 Note D13 RTCL2P[13] R/W 0 Note D12 RTCL2P[12] R/W 0 Note D11 RTCL2P[11] R/W 0 Note D10 RTCL2P[10] R/W 0 Note D9 RTCL2P[9] R/W 0 Note D8 RTCL2P[8] R/W 0 Note Bit Name R/W RTCRST Other resets D7 RTCL2P[7] R/W 0 Note D6 RTCL2P[6] R/W 0 Note D5 RTCL2P[5] R/W 0 Note D4 RTCL2P[4] R/W 0 Note D3 RTCL2P[3] R/W 0 Note D2 RTCL2P[2] R/W 0 Note D1 RTCL2P[1] R/W 0 Note D0 RTCL2P[0] R/W 0 Note Bit D[15:0] Name RTCL2P[15:0] [15:0] for RTCLong2 counter cycle Function Note Previous value is retained 345 CHAPTER 16 RTC (REALTIME CLOCK UNIT) (2) RTCL2HREG (0x0B00 00DA) Bit Name R/W RTCRST Other resets D15 Reserved R 0 Note D14 Reserved R 0 Note D13 Reserved R 0 Note D12 Reserved R 0 Note D11 Reserved R 0 Note D10 Reserved R 0 Note D9 Reserved R 0 Note D8 Reserved R 0 Note Bit Name R/W RTCRST Other resets D7 RTCL2P[23] R/W 0 Note D6 RTCL2P[22] R/W 0 Note D5 RTCL2P[21] R/W 0 Note D4 RTCL2P[20] R/W 0 Note D3 RTCL2P[19] R/W 0 Note D2 RTCL2P[18] R/W 0 Note D1 D0 RTCL2P[17] RTCL2P[16] R/W 0 Note R/W 0 Note Bit D[15:8] D[7:0] Reserved Name Function Write 0 when writing. 0 is returned after a read. [23:16] for RTCLong2 counter cycle RTCL2P[23:16] Note Previous value is retained Use these registers to set the RTCLong2 counter cycle. The RTCLong2 counter begins its countdown at the value written to these registers. A write operation is valid once values have been written to both registers (RTCL2LREG and RTCL2HREG). Cautions 1. The RTC unit is stopped when all zeros are written. 2. Any combined setting of "RTCL2HREG = 0x0000" and 0x0003, 0x0004" is prohibited. "RTCL2LREG = 0x0001, 0x0002, 346 CHAPTER 16 RTC (REALTIME CLOCK UNIT) 16.2.6 RTC Long 2 Count Registers (1) RTCL2CNTLREG (0x0B00 00DC) Bit Name R/W RTCRST Other resets D15 D14 D13 D12 D11 D10 D9 RTCL2C[9] R 0 Note D8 RTCL2C[8] R 0 Note RTCL2C[15] RTCL2C[14] RTCL2C[13] RTCL2C[12] RTCL2C[11] RTCL2C[10] R 0 Note R 0 Note R 0 Note R 0 Note R 0 Note R 0 Note Bit Name R/W RTCRST Other resets D7 RTCL2C[7] R 0 Note D6 RTCL2C[6] R 0 Note D5 RTCL2C[5] R 0 Note D4 RTCL2C[4] R 0 Note D3 RTCL2C[3] R 0 Note D2 RTCL2C[2] R 0 Note D1 RTCL2C[1] R 0 Note D0 RTCL2C[0] R 0 Note Bit D[15:0] Name RTCL2C[15:0] RTCLong2 counter bit [15:0] Function Note Continues counting 347 CHAPTER 16 RTC (REALTIME CLOCK UNIT) (2) RTCL2CNTHREG (0x0B00 00DE) Bit Name R/W RTCRST Other resets D15 Reserved R 0 Note D14 Reserved R 0 Note D13 Reserved R 0 Note D12 Reserved R 0 Note D11 Reserved R 0 Note D10 Reserved R 0 Note D9 Reserved R 0 Note D8 Reserved R 0 Note Bit Name R/W RTCRST Other resets D7 D6 D5 D4 D3 D2 D1 D0 RTCL2C[23] RTCL2C[22] RTCL2C[21] RTCL2C[20] RTCL2C[19] RTCL2C[18] RTCL2C[17] RTCL2C[16] R 0 Note R 0 Note R 0 Note R 0 Note R 0 Note R 0 Note R 0 Note R 0 Note Bit D[15:8] D[7:0] Reserved Name Function Write 0 when writing. 0 is returned after a read. RTCLong2 counter bit [23:16] RTCL2C[23:16] Note Continues counting These registers indicate the RTCLong2 counter's values. The countdown uses a 32.768-kHz cycle and begins at the value set to the RTCLong2 registers. An RTCLong2 interrupt occurs when the counter reaches 0x00 0001 (at which point the counter returns to the start value and continues counting). 348 CHAPTER 16 RTC (REALTIME CLOCK UNIT) 16.2.7 TClock Counter Registers (1) TCLKLREG (0x0B00 01C0) Bit Name R/W RTCRST Other resets D15 TCLKP[15] R/W 0 0 D14 TCLKP[14] R/W 0 0 D13 TCLKP[13] R/W 0 0 D12 TCLKP[12] R/W 0 0 D11 TCLKP[11] R/W 0 0 D10 TCLKP[10] R/W 0 0 D9 TCLKP[9] R/W 0 0 D8 TCLKP[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 TCLKP[7] R/W 0 0 D6 TCLKP[6] R/W 0 0 D5 TCLKP[5] R/W 0 0 D4 TCLKP[4] R/W 0 0 D3 TCLKP[3] R/W 0 0 D2 TCLKP[2] R/W 0 0 D1 TCLKP[1] R/W 0 0 D0 TCLKP[0] R/W 0 0 Bit D[15:0] Name TCLKP[15:0] [15:0] for TClock counter cycle Function 349 CHAPTER 16 RTC (REALTIME CLOCK UNIT) (2) TCLKHREG (0x0B00 01C2) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 TCLKP[24] R/W 0 0 Bit Name R/W RTCRST Other resets D7 TCLKP[23] R/W 0 0 D6 TCLKP[22] R/W 0 0 D5 TCLKP[21] R/W 0 0 D4 TCLKP[20] R/W 0 0 D3 TCLKP[19] R/W 0 0 D2 TCLKP[18] R/W 0 0 D1 TCLKP[17] R/W 0 0 D0 TCLKP[16] R/W 0 0 Bit D[15:9] D[8:0] Reserved Name Function Write 0 when writing. 0 is returned after a read. [24:16] for TClock counter cycle TCLKP[24:16] Use these registers to set the TCLK counter cycle. The TCLK counter begins its countdown at the value written to these registers. A write operation is valid once values have been written to both registers (TCLKLREG and TCLKHREG). Caution The TCLK unit is stopped when all zeros are written. 350 CHAPTER 16 RTC (REALTIME CLOCK UNIT) 16.2.8 TClock Counter Count Registers (1) TCLKCNTLREG (0x0B00 01C4) Bit Name R/W RTCRST Other resets D15 TCLKC[15] R 0 0 D14 TCLKC[14] R 0 0 D13 TCLKC[13] R 0 0 D12 TCLKC[12] R 0 0 D11 TCLKC[11] R 0 0 D10 TCLKC[10] R 0 0 D9 TCLKC[9] R 0 0 D8 TCLKC[8] R 0 0 Bit Name R/W RTCRST Other resets D7 TCLKC[7] R 0 0 D6 TCLKC[6] R 0 0 D5 TCLKC[5] R 0 0 D4 TCLKC[4] R 0 0 D3 TCLKC[3] R 0 0 D2 TCLKC[2] R 0 0 D1 TCLKC[1] R 0 0 D0 TCLKC[0] R 0 0 Bit D[15:0] Name TCLKC[15:0] TClock counter [15:0] Function 351 CHAPTER 16 RTC (REALTIME CLOCK UNIT) (2) TCLKCNTHREG (0x0B00 01C6) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 TCLKC[24] R 0 0 Bit Name R/W RTCRST Other resets D7 TCLKC[23] R 0 0 D6 TCLKC[22] R 0 0 D5 TCLKC[21] R 0 0 D4 TCLKC[20] R 0 0 D3 TCLKC[19] R 0 0 D2 TCLKC[18] R 0 0 D1 TCLKC[17] R 0 0 D0 TCLKC[16] R 0 0 Bit D[15:9] D[8:0] Reserved Name Function Write 0 when writing. 0 is returned after a read. TClock counter [24:16] TCLKC[24:16] Use these registers to set the TCLK counter value. The TCLKCNT counter begins its countdown at the value written to the TCLK counter registers. A TCLK counter interrupt occurs when the counter reaches 0x000 0001 (at which point the counter returns to the start value and continues counting). 352 CHAPTER 16 RTC (REALTIME CLOCK UNIT) 16.2.9 RTC Interrupt Register (1) RTCINTREG (0x0B00 01DE) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 RTCINTR3 R/W 0 0 D2 RTCINTR2 R/W 0 Note D1 RTCINTR1 R/W 0 Note D0 RTCINTR0 R/W 0 Note Bit D[15:4] D[3] Reserved Name Function Write 0 when writing. 0 is returned after a read. TClock counter interrupt. Cleared to 0 when 1 is written. 1 : Occurred 0 : Normal RTCLong2 interrupt. Cleared to 0 when 1 is written. 1 : Occurred 0 : Normal RTCLong1 interrupt. Cleared to 0 when 1 is written. 1 : Occurred 0 : Normal Status bit for elapsed time interrupt. Cleared to 0 when 1 is written. 1 : Occurred 0 : Normal RTCINTR3 D[2] RTCINTR2 D[1] RTCINTR1 D[0] RTCINTR0 Note Previous value is retained This register is used to monitor interrupts. 353 [MEMO] 354 CHAPTER 17 DSU (DEADMAN'S SWITCH UNIT) This chapter describes the DSU (Deadman's Switch Unit)'s operations and register settings. 17.1 GENERAL The DSU detects when the VR4102 is in runaway (endless loop) state and resets the VR4102 to minimize runaway time. The use of the DSU to minimize runaway time effectively minimizes data loss that can occur due to software-related runaway states. 17.2 REGISTER SET The DSU registers are listed below. Table 17-1. DSU Registers Address 0x0B00 00E0 0x0B00 00E2 0x0B00 00E4 0x0B00 00E6 R/W R/W R/W W R/W Symbol DSUCNTREG DSUSETREG DSUCLRREG DSUTIMREG DSU Control Register DSU Dead Time Set Register DSU Clear Register DSU Elapsed Time Register Function Each register is described in detail below. 355 CHAPTER 17 DSU (DEADMAN'S SWITCH UNIT) 17.2.1 DSUCNTREG (0x0B00 00E0) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 Reserved R 0 0 D0 DSWEN R/W 0 0 Bit D[15..1] D[0] Reserved DSWEN Name Function Write 0 when writing. 0 is returned after a read. Deadman's Switch function enable 1 : Enable 0 : Prohibit This register is used to enable use of the Deadman's Switch functions. 356 CHAPTER 17 DSU (DEADMAN'S SWITCH UNIT) 17.2.2 DSUSETREG (0x0B00 00E2) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 D2 D1 D0 DEDTIME[3] DEDTIME[2] DEDTIME[1] DEDTIME[0] R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 Bit D[15..4] D[3..0] Reserved Name Function Write 0 when writing. 0 is returned after a read. Deadman's Switch cycle setting 1111 15 sec 1110 14 sec : 0010 2 sec 0001 1 sec 0000 RFU DEDTIME[3..0] This register sets the cycle for Deadman's Switch functions. The Deadman's Switch cycle can be set in 1-second increments in a range from 1 to 15 seconds. However, the VR4102's operation is undefined when 0x0 has been set to DEDTIME[3..0]. The DSUCLRREG's DSWCLR bit must be set by software within the specified cycle time. 357 CHAPTER 17 DSU (DEADMAN'S SWITCH UNIT) 17.2.3 DSUCLRREG (0x0B00 00E4) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 Reserved R 0 0 D0 DSWCLR W 0 0 Bit D[15..1] D[0] Reserved DSWCLR Name Function Write 0 when writing. 0 is returned after a read. Deadman's Switch counter clear. Cleared to 0 when 1 is written. 1 : Clear 0 : Don't clear This register clears the Deadman's Switch counter. The VR4102 automatically shuts down if 1 is not written to this register within the period set in DSUSETREG. 358 CHAPTER 17 DSU (DEADMAN'S SWITCH UNIT) 17.2.4 DSUTIMREG (0x0B00 00E6) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 D2 D1 D0 CRTTIME[3] CRTTIME[2] CRTTIME[1] CRTTIME[0] R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 Bit D[15..4] D[3..0] Reserved Name Function Write 0 when writing. 0 is returned after a read. Current Deadman's Switch timer value (elapsed time) 1111 15 sec 1110 14 sec : 0010 2 sec 0001 1 sec 0000 RFU CRTTIME[3..0] This register indicates the elapsed time for the current Deadman's Switch timer. 359 CHAPTER 17 DSU (DEADMAN'S SWITCH UNIT) 17.3 REGISTER SETTING FLOW The DSU register setting flow is described below. 1. Set the DSU's count-up value (From 1 to 15 seconds). The CPU will be reset if it does not clear (1 is not written to DSUCLRREG) the timer within this time period. DSUDTMREG 2. Enable the DSU. DSUCNTREG 3. address : 0x0B00 00E0 data : 0x0001 address : 0x0B00 00E2 data : 0x000x Clear the timer within the time period mentioned in step 1 above. DSUCLRREG address : 0x0B00 00E4 data : 0x0001 For normal use, repeat step 3. To obtain the current elapsed time: DSITIMREG address : 0x0B00 00E6 4. read (4 bits) Disable the DSU for Suspend mode or a shutdown. DSUCNTREG address : 0x0B00 00E0 data : 0x0000 360 CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) This chapter describes the GIU's operations and register settings. 18.1 GENERAL The GIU controls GPIO and DCD# pins. GPIO pins are ports that support output functions and input functions (including three types of interrupt trigger detection functions). The interrupts occur in response to an input signal change (rising edge or falling edge of signal), low level, or high level. The clocks and input buffer types used for interrupt detection at a GPIO pin are listed below. When not used for an interrupt, the registers corresponding to these pins can be written to output a low-level or high-level signal. Each register can be read to check the state of the signal currently being input to the corresponding pin. Table 18-1. GPIO Pin Functions Pin Interrupt detection clock (internal) TClock MasterOut MasterOut TClock TClock RTC Input buffer type Output clock (internal) TClock TClock MasterOut MasterOut TClock RTC GPIO[49..32] GPIO[31..16] GPIO[15](DCD#) GPIO[14..9] GPIO[8..5] GPIO[4] GPIO[3..0] Normal Normal Normal Normal Schmitt Schmitt Cautions The function of GPIO[15] is fixed as DCD# input signal. This pin cannot be used as a general-purpose input/output pin. 361 CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) 18.2 REGISTER SET The GIU registers are listed below. Table 18-2. GIU Registers Address 0x0B00 0100 0x0B00 0102 0x0B00 0104 0x0B00 0106 0x0B00 0108 0x0B00 010A 0x0B00 010C 0x0B00 010E 0x0B00 0110 0x0B00 0112 0x0B00 0114 0x0B00 0116 0x0B00 0118 0x0B00 011A 0x0B00 011C 0x0B00 011E R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register Symbols GIUIOSELL GIUIOSELH GIUPIODL GIUPIODH GIUINTSTATL GIUINTSTATH GIUINTENL GIUINTENH GIUINTTYPL GIUINTTYPH GIUINTALSELL GIUINTALSELH GIUINTHTSELL GIUINTHTSELH GIUPODATL GIUPODATH Function GPIO Input/Output Select Register L GPIO Input/Output Select Register H GPIO Port Input/Output Data Register L GPIO Port Input/Output Data Register H GPIO Interrupt Status Register L GPIO Interrupt Status Register H GPIO Interrupt Enable Register L GPIO Interrupt Enable Register H GPIO Interrupt Type (Edge or Level) Select Register L GPIO Interrupt Type (Edge or Level) Select Register H GPIO Interrupt Active Level Select Register L GPIO Interrupt Active Level Select Register H GPIO Interrupt Hold/Through Select Register L GPIO Interrupt Hold/Through Select Register H GPIO Port Output Data Register L GPIO Port Output Data Register H 362 CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) 18.2.1 GIUIOSELL (0x0B00 0100) Bit Name R/W RTCRST Other resets D15 IOS[15] R 0 0 D14 IOS[14] R/W 0 0 D13 IOS[13] R/W 0 0 D12 IOS[12] R/W 0 0 D11 IOS[11] R/W 0 0 D10 IOS[10] R/W 0 0 D9 IOS[9] R/W 0 0 D8 IOS[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 IOS[7] R/W 0 0 D6 IOS[6] R/W 0 0 D5 IOS[5] R/W 0 0 D4 IOS[4] R/W 0 0 D3 IOS[3] R/W 0 0 D2 IOS[2] R/W 0 0 D1 IOS[1] R/W 0 0 D0 IOS[0] R/W 0 0 Bit D[15..0] IOS[15..0] Name GPIO pin input/output select 1 : Output 0 : Input Function This register is used to set input/output values for GPIO[15..0] pins. When the IOS bit is set to "1", the corresponding GPIO pin is set for output and the value that has been written to the corresponding PIOD bit in the GIUPIODL (GPIO Port Input/Output Data Register) is output. When this bit is set to "0", the corresponding GPIO pin is set for input. Caution Since IOS[15] (GPIO[15] (DCD#)) is fixed as input, it cannot be set for output. 363 CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) 18.2.2 GIUIOSELH (0x0B00 0102) Bit Name R/W RTCRST Other resets D15 IOS[31] R/W 0 0 D14 IOS[30] R/W 0 0 D13 IOS[29] R/W 0 0 D12 IOS[28] R/W 0 0 D11 IOS[27] R/W 0 0 D10 IOS[26] R/W 0 0 D9 IOS[25] R/W 0 0 D8 IOS[24] R/W 0 0 Bit Name R/W RTCRST Other resets D7 IOS[23] R/W 0 0 D6 IOS[22] R/W 0 0 D5 IOS[21] R/W 0 0 D4 IOS[20] R/W 0 0 D3 IOS[19] R/W 0 0 D2 IOS[18] R/W 0 0 D1 IOS[17] R/W 0 0 D0 IOS[16] R/W 0 0 Bit D[15..0] Name IOS[31..16] GPIO pin input/output select 1 : Output 0 : Input Function This register is used to set input/output settings for GPIO[31..16] pins. When the IOS bit is set to "1", the corresponding GPIO pin is set for output and the value that has been written to the corresponding PIOD bit in the GIUPIODH (GPIO Port Input/Output Data Register) is output. When this bit is set to "0", the corresponding GPIO pin is set for input. 364 CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) 18.2.3 GIUPIODL (0x0B00 0104) Bit Name R/W RTCRST Other resets D15 PIOD[15] R 0 0 D14 PIOD[14] R/W 0 0 D13 PIOD[13] R/W 0 0 D12 PIOD[12] R/W 0 0 D11 PIOD[11] R/W 0 0 D10 PIOD[10] R/W 0 0 D9 PIOD[9] R/W 0 0 D8 PIOD[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 PIOD[7] R/W 0 0 D6 PIOD[6] R/W 0 0 D5 PIOD[5] R/W 0 0 D4 PIOD[4] R/W 0 0 D3 PIOD[3] R/W 0 0 D2 PIOD[2] R/W 0 0 D1 PIOD[1] R/W 0 0 D0 PIOD[0] R/W 0 0 Bit D[15..0] Name PIOD[15..0] GPIO pin output data specification 1 : High 0 : Low Function This register is used to read GPIO pins and write data. The PIOD[15..0] bits correspond to the GPIO[15..0] pins. When "1" is set to the corresponding IOS bit in the GIUIOSELL register (GPIO Input/Output Select Register), the data written to the PIOD bit is output via the corresponding GPIO pin. When the value of the corresponding IOS bit in the GIUIOSELL register (GPIO Input/Output Select Register) is "0", writing a value to the PIOD bit does not affect the GPIO pin (the write data is ignored). When the value of the IOS bit in the GIUIOSELL register (GPIO Input/Output Select Register) is "0", reading the PIOD bit enables the corresponding GPIO pin's state to be read. Caution Since PIOD[15] (GPIO[15] (DCD#)) is fixed as input, write data cannot be output via this pin. 365 CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) 18.2.4 GIUPIODH (0x0B00 0106) Bit Name R/W RTCRST Other resets D15 PIOD[31] R/W 0 0 D14 PIOD[30] R/W 0 0 D13 PIOD[29] R/W 0 0 D12 PIOD[28] R/W 0 0 D11 PIOD[27] R/W 0 0 D10 PIOD[26] R/W 0 0 D9 PIOD[25] R/W 0 0 D8 PIOD[24] R/W 0 0 Bit Name R/W RTCRST Other resets D7 PIOD[23] R/W 0 0 D6 PIOD[22] R/W 0 0 D5 PIOD[21] R/W 0 0 D4 PIOD[20] R/W 0 0 D3 PIOD[19] R/W 0 0 D2 PIOD[18] R/W 0 0 D1 PIOD[17] R/W 0 0 D0 PIOD[16] R/W 0 0 Bit D[15..0] Name PIOD[31..16] GPIO pin output data specification 1 : High 0 : Low Function This register is used to read GPIO pins and write data. The PIOD[31..16] bits correspond to the GPIO[31..16] pins. When "1" is set to the corresponding IOS bit in the GIUIOSELH register (GPIO Input/Output Select Register), the data written to the PIOD bit is output via the corresponding GPIO pin. When the value of the corresponding IOS bit in the GIUIOSELH register (GPIO Input/Output Select Register) is "0", writing a value to the PIOD bit does not affect the GPIO pin (the write data is ignored). When the value of the IOS bit in the GIUIOSELH register (GPIO Input/Output Select Register) is "0", reading the PIOD bit enables the corresponding GPIO pin's state to be read. 366 CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) 18.2.5 GIUINTSTATL (0x0B00 0108) Bit Name R/W RTCRST Other resets D15 INTS[15] R/W 0 0 D14 INTS[14] R/W 0 0 D13 INTS[13] R/W 0 0 D12 INTS[12] R/W 0 0 D11 INTS[11] R/W 0 0 D10 INTS[10] R/W 0 0 D9 INTS[9] R/W 0 0 D8 INTS[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 INTS[7] R/W 0 0 D6 INTS[6] R/W 0 0 D5 INTS[5] R/W 0 0 D4 INTS[4] R/W 0 0 D3 INTS[3] R/W 0 0 D2 INTS[2] R/W 0 0 D1 INTS[1] R/W 0 0 D0 INTS[0] R/W 0 0 Bit D[15..0] Name INTS[15..0] Function Interrupt to GPIO pin. Cleared to 0 when 1 is written. 1 : Interrupt occurred 0 : No interrupt This register indicates the interrupt status of GPIO pins. The INTS[15..0] bits correspond to the GPIO[15..0] pins. "1" is set to the corresponding INTS bit when "1" is set to the corresponding INTE bit in the GIUINTENL register (GPIO Interrupt Enable Register) and when the signal input to an interrupt-enabled GPIO pin meets the conditions set via the GIUNTTYPL register (GPIO Interrupt Type (Edge or Level) Select Register) and the GIUINTALSELL register (GPIO Interrupt Active Level Select Register). Caution The function of GPIO[15] is fixed as DCD# signal input. 367 CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) 18.2.6 GIUINTSTATH (0x0B00 010A) Bit Name R/W RTCRST Other resets D15 INTS[31] R/W 0 0 D14 INTS[30] R/W 0 0 D13 INTS[29] R/W 0 0 D12 INTS[28] R/W 0 0 D11 INTS[27] R/W 0 0 D10 INTS[26] R/W 0 0 D9 INTS[25] R/W 0 0 D8 INTS[24] R/W 0 0 Bit Name R/W RTCRST Other resets D7 INTS[23] R/W 0 0 D6 INTS[22] R/W 0 0 D5 INTS[21] R/W 0 0 D4 INTS[20] R/W 0 0 D3 INTS[19] R/W 0 0 D2 INTS[18] R/W 0 0 D1 INTS[17] R/W 0 0 D0 INTS[16] R/W 0 0 Bit D[15..0] Name INTS[31..16] Function Interrupt to GPIO pin. Cleared to 0 when 1 is written. 1 : Interrupt occurred 0 : No interrupt This register indicates the interrupt status of GPIO pins. The INTS[31..16] bits correspond to the GPIO[31..16] pins. "1" is set to the corresponding INTS bit when "1" is set to the corresponding INTE bit in the GIUINTENH register (GPIO Interrupt Enable Register) and when the signal input to an interrupt-enabled GPIO pin meets the conditions set via the GIUINTTYPH register (GPIO Interrupt Type (Edge or Level) Select Register) and the GIUINTALSELH register (GPIO Interrupt Active Level Select Register). 368 CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) 18.2.7 GIUINTENL (0x0B00 010C) Bit Name R/W RTCRST Other resets D15 INTE[15] R/W 0 0 D14 INTE[14] R/W 0 0 D13 INTE[13] R/W 0 0 D12 INTE[12] R/W 0 0 D11 INTE[11] R/W 0 0 D10 INTE[10] R/W 0 0 D9 INTE[9] R/W 0 0 D8 INTE[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 INTE[7] R/W 0 0 D6 INTE[6] R/W 0 0 D5 INTE[5] R/W 0 0 D4 INTE[4] R/W 0 0 D3 INTE[3] R/W 0 0 D2 INTE[2] R/W 0 0 D1 INTE[1] R/W 0 0 D0 INTE[0] R/W 0 0 Bit D[15..0] Name INTE[15..0] Interrupt enable to GPIO pin 1 : Interrupt enable 0 : Interrupt prohibit Function This register is used to set interrupt enable status for GPIO pins. GPIO[15..0] pins. The INTE[15..0] bits correspond to the When "1" is set to the corresponding INTE bit, interrupts are enabled for the corresponding GPIO pins. Caution The function of GPIO[15] is fixed as DCD# signal input. 369 CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) 18.2.8 GIUINTENH (0x0B00 010E) Bit Name R/W RTCRST Other resets D15 INTE[31] R/W 0 0 D14 INTE[30] R/W 0 0 D13 INTE[29] R/W 0 0 D12 INTE[28] R/W 0 0 D11 INTE[27] R/W 0 0 D10 INTE[26] R/W 0 0 D9 INTE[25] R/W 0 0 D8 INTE[24] R/W 0 0 Bit Name R/W RTCRST Other resets D7 INTE[23] R/W 0 0 D6 INTE[22] R/W 0 0 D5 INTE[21] R/W 0 0 D4 INTE[20] R/W 0 0 D3 INTE[19] R/W 0 0 D2 INTE[18] R/W 0 0 D1 INTE[17] R/W 0 0 D0 INTE[16] R/W 0 0 Bit D[15..0] Name INTE[31..16] Interrupt enable to GPIO pin 1 : Interrupt enable 0 : Interrupt prohibit Function This register is used to set interrupt enable status for GPIO pins. The INTE[31..16] bits correspond to the GPIO[31..16] pins. When "1" is set to the corresponding INTE bit, interrupts are enabled for the corresponding GPIO pins. 370 CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) 18.2.9 GIUINTTYPL (0x0B00 0110) Bit Name R/W RTCRST Other resets D15 INTT[15] R/W 0 0 D14 INTT[14] R/W 0 0 D13 INTT[13] R/W 0 0 D12 INTT[12] R/W 0 0 D11 INTT[11] R/W 0 0 D10 INTT[10] R/W 0 0 D9 INTT[9] R/W 0 0 D8 INTT[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 INTT[7] R/W 0 0 D6 INTT[6] R/W 0 0 D5 INTT[5] R/W 0 0 D4 INTT[4] R/W 0 0 D3 INTT[3] R/W 0 0 D2 INTT[2] R/W 0 0 D1 INTT[1] R/W 0 0 D0 INTT[0] R/W 0 0 Bit D[15..0] Name INTT[15..0] Interrupt detection method 1 : Edge 0 : Level Function This register is used to set the detection method (trigger) for interrupts to GPIO pins. The INTT[15..0] bits correspond to the GPIO[15..0] pins. When "1" is set to the corresponding INTT bit, the edge detection method is used for the interrupt signal at the corresponding GPIO pin (an interrupt is triggered when the signal state changes from low to high or from high to low). The level detection method is used when "0" is set, in which case the level set to corresponding bit in the GIUINTALSELL register (GPIO Interrupt Active Level Select Register) is detected. Caution The function of GPIO[15] is fixed as DCD# signal input. 371 CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) 18.2.10 GIUINTTYPH (0x0B00 0112) Bit Name R/W RTCRST Other resets D15 INTT[31] R/W 0 0 D14 INTT[30] R/W 0 0 D13 INTT[29] R/W 0 0 D12 INTT[28] R/W 0 0 D11 INTT[27] R/W 0 0 D10 INTT[26] R/W 0 0 D9 INTT[25] R/W 0 0 D8 INTT[24] R/W 0 0 Bit Name R/W RTCRST Other resets D7 INTT[23] R/W 0 0 D6 INTT[22] R/W 0 0 D5 INTT[21] R/W 0 0 D4 INTT[20] R/W 0 0 D3 INTT[19] R/W 0 0 D2 INTT[18] R/W 0 0 D1 INTT[17] R/W 0 0 D0 INTT[16] R/W 0 0 Bit D[15..0] Name INTT[31..16] Interrupt detection method 1 : Edge 0 : Level Function This register is used to set the detection method for interrupts to GPIO pins. The INTT[31..16] bits correspond to the GPIO[31..16] pins. When "1" is set to the corresponding INTT bit, the edge detection method is used for the interrupt signal at the corresponding GPIO pin (an interrupt is triggered when the signal state changes from low to high or from high to low). The level detection method is used when "0" is set, in which case the level set to corresponding bit in the GIUINTALSELH register (GPIO Interrupt Active Level Select Register) is detected. 372 CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) 18.2.11 GIUINTALSELL (0x0B00 0114) Bit Name R/W RTCRST Other resets D15 INTL[15] R/W 0 0 D14 INTL[14] R/W 0 0 D13 INTL[13] R/W 0 0 D12 INTL[12] R/W 0 0 D11 INTL[11] R/W 0 0 D10 INTL[10] R/W 0 0 D9 INTL[9] R/W 0 0 D8 INTL[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 INTL[7] R/W 0 0 D6 INTL[6] R/W 0 0 D5 INTL[5] R/W 0 0 D4 INTL[4] R/W 0 0 D3 INTL[3] R/W 0 0 D2 INTL[2] R/W 0 0 D1 INTL[1] R/W 0 0 D0 INTL[0] R/W 0 0 Bit D[15..0] Name INTL[15..0] Function Interrupt setting during level detection method 1 : High active 0 : Low active This register is used to set the active level when using the level detection method for interrupts to GPIO pins. The INTL[15..0] bits correspond to the GPIO[15..0] pins. When "1" is set to the corresponding INTL bit, the high-active level detection method is used for interrupts at the corresponding GPIO pin. The low-active level detection method is used when "0" is set to this bit. The contents of this register are not reflected when the edge detection method is selected via the GIUINTTYPL register (GPIO Interrupt Type (Edge or Level) Select Register). When using this register, be sure to set the level detection method via the GIUINTTYPL register (GPIO Interrupt Type (Edge or Level) Select Register). Caution The function of GPIO[15] is fixed as DCD# signal input. 373 CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) 18.2.12 GIUINTALSELH (0x0B00 0116) Bit Name R/W RTCRST Other resets D15 INTL[31] R/W 0 0 D14 INTL[30] R/W 0 0 D13 INTL[29] R/W 0 0 D12 INTL[28] R/W 0 0 D11 INTL[27] R/W 0 0 D10 INTL[26] R/W 0 0 D9 INTL[25] R/W 0 0 D8 INTL[24] R/W 0 0 Bit Name R/W RTCRST Other resets D7 INTL[23] R/W 0 0 D6 INTL[22] R/W 0 0 D5 INTL[21] R/W 0 0 D4 INTL[20] R/W 0 0 D3 INTL[19] R/W 0 0 D2 INTL[18] R/W 0 0 D1 INTL[17] R/W 0 0 D0 INTL[16] R/W 0 0 Bit D[15..0] Name INTL[31..16] Function Interrupt setting during level detection method 1 : High active 0 : Low active This register is used to set the active level when using the level detection method for interrupts to GPIO pins. The INTL[31..16] bits correspond to the GPIO[31..16] pins. When "1" is set to the corresponding INTL bit, the high-active level detection method is used for interrupts at the corresponding GPIO pin. The low-active level detection method is used when "0" is set to this bit. The contents of this register are not reflected when the edge detection method is selected via the GIUINTTYPH register (GPIO Interrupt Type (Edge or Level) Select Register). When using this register, be sure to set the level detection method via the GIUINTTYPH register (GPIO Interrupt Type (Edge or Level) Select Register). 374 CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) 18.2.13 GIUINTHTSELL (0x0B00 0118) Bit Name R/W RTCRST Other resets D15 INTH[15] R/W 0 0 D14 INTH[14] R/W 0 0 D13 INTH[13] R/W 0 0 D12 INTH[12] R/W 0 0 D11 INTH[11] R/W 0 0 D10 INTH[10] R/W 0 0 D9 INTH[9] R/W 0 0 D8 INTH[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 INTH[7] R/W 0 0 D6 INTH[6] R/W 0 0 D5 INTH[5] R/W 0 0 D4 INTH[4] R/W 0 0 D3 INTH[3] R/W 0 0 D2 INTH[2] R/W 0 0 D1 INTH[1] R/W 0 0 D0 INTH[0] R/W 0 0 Bit D[15..0] Name INTH[15..0] GPIO pin interrupt signal hold/through 1 : Hold 0 : Through Function This register is used to set whether or not interrupt signals to the GPIO pins should be held. The INTH[15..0] bits correspond to the GPIO[15..0] pins. When "1" is set to the corresponding INTH bit, any interrupt signal input to the corresponding GPIO pin is held. When "0" is set to this bit, any interrupt signal input to the corresponding GPIO pin is not held and is instead allowed to pass through. Any held interrupt signal is cleared when "1" is set to the corresponding bit in the GIUINTSTATL register (GPIO Interrupt Status Register). INTH[15..0] are not affected by GIUINTENL (interrupt enable register). If "1" (hold) is set to the INTH bit while the interrupt enable bit is set to prohibit interrupts, any change in the pin state is retained as change data. Therefore, an interrupt still occurs when the interrupt enable bit is again set to enable interrupts. Caution The function of GPIO[15] is fixed as DCD# signal input. 375 CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) 18.2.14 GIUINTHTSELH (0x0B00 011A) Bit Name R/W RTCRST Other resets D15 INTH[31] R/W 0 0 D14 INTH[30] R/W 0 0 D13 INTH[29] R/W 0 0 D12 INTH[28] R/W 0 0 D11 INTH[27] R/W 0 0 D10 INTH[26] R/W 0 0 D9 INTH[25] R/W 0 0 D8 INTH[24] R/W 0 0 Bit Name R/W RTCRST Other resets D7 INTH[23] R/W 0 0 D6 INTH[22] R/W 0 0 D5 INTH[21] R/W 0 0 D4 INTH[20] R/W 0 0 D3 INTH[19] R/W 0 0 D2 INTH[18] R/W 0 0 D1 INTH[17] R/W 0 0 D0 INTH[16] R/W 0 0 Bit D[15..0] Name INTH[31..16] GPIO pin interrupt signal hold/through 1 : Hold 0 : Through Function This register is used to set whether or not interrupt signals to the GPIO pins should be held. The INTH[31..16] bits correspond to the GPIO[31..16] pins. When "1" is set to the corresponding INTH bit, any interrupt signal input to the corresponding GPIO pin is held. When "0" is set to this bit, any interrupt signal input to the corresponding GPIO pin is not held and is instead allowed to pass through. Any held interrupt signal is cleared when "1" is set to the corresponding bit in the GIUINTSTATH register (GPIO Interrupt Status Register). INTH[31..16] are not affected by GIUINTENH (interrupt enable register). If "1" (hold) is set to the INTH bit while the interrupt enable bit is set to prohibit interrupts, any change in the pin state is retained as change data. Therefore, an interrupt still occurs when the interrupt enable bit is again set to enable interrupts. 376 CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) The relationship between settings of GPIO interrupts enable/prohibit and hold/through is as below. Interrupt trigger Level Setting of GIUINTHSEL Setting of GIUINTEN Hold in GIU Notation to ICU Hold Masked Not masked Masked o canceled Held Held Held Through Through Through Held Held Held Through Prohibited Through Not noticed Noticed Noticed Not noticed Noticed Not noticed Not noticed Noticed Noticed Not noticed Prohibited Not noticed Through Masked Not masked Masked o canceled Edge Hold Masked Not masked Masked o canceled Through Masked Not masked Masked o canceled 377 CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) 18.2.15 GIUPODATL (0x0B00 011C) Bit Name R/W RTCRST Other resets D15 PIOD[47] R/W 1 1 D14 PIOD[46] R/W 1 1 D13 PIOD[45] R/W 1 1 D12 PIOD[44] R/W 1 1 D11 PIOD[43] R/W 1 1 D10 PIOD[42] R/W 1 1 D9 PIOD[41] R/W 1 1 D8 PIOD[40] R/W 1 1 Bit Name R/W RTCRST Other resets D7 PIOD[39] R/W 1 1 D6 PIOD[38] R/W 1 1 D5 PIOD[37] R/W 1 1 D4 PIOD[36] R/W 1 1 D3 PIOD[35] R/W 1 1 D2 PIOD[34] R/W 1 1 D1 PIOD[33] R/W 1 1 D0 PIOD[32] R/W 1 1 Bit D[15..0] Name PIOD[47..32] GPIO pin output data specification 1 : High 0 : Low Function This register is used to set the output level for GPIO pins. The PIOD[47..32] bits correspond to the GPIO[47..32] pins. The data written to the PIOD bit is output via the corresponding GPIO pin. The set value can be read by reading the PIOD bit. Pins set by this register are output-only. Pins set by this register are used exclusively from other function pins. Therefore, when using this register, set the enable bit to prohibit in the corresponding unit. The correspondences between PIOD bits and function pins are listed in the table on the next page. 378 CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) Table 18-3. Table of Correspondences between GPIO[47..32] and Function Pins PIOD Bit PIOD[47] PIOD[46] PIOD[45] PIOD[44] PIOD[43] PIOD[42] PIOD[41] PIOD[40] PIOD[39] PIOD[38] PIOD[37] PIOD[36] PIOD[35] PIOD[34] PIOD[33] PIOD[32] GPIO pin GPIO[47] GPIO[46] GPIO[45] GPIO[44] GPIO[43] GPIO[42] GPIO[41] GPIO[40] GPIO[39] GPIO[38] GPIO[37] GPIO[36] GPIO[35] GPIO[34] GPIO[33] GPIO[32] Function pin DCTS# DRTS# DDIN DDOUT KSCAN[11] KSCAN[10] KSCAN[9] KSCAN[8] KSCAN[7] KSCAN[6] KSCAN[5] KSCAN[4] KSCAN[3] KSCAN[2] KSCAN[1] KSCAN[0] 379 CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) 18.2.16 GIUPODATH (0x0B00 011E) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 PIOEN[1] R/W 0 0 D8 PIOEN[0] R/W 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 PIOD[49] R/W 0 0 D0 PIOD[48] R/W 0 0 Bit D[15..0] D[9] Reserved PIOEN[1] Name Reserved GPIO[49] pin output control 1 : Enable 0 : Disable GPIO[48]/DBUS32 pin output control 1 : Enable 0 : Disable Reserved GPIO pin output data specification 1 : High 0 : Low Function D[8] PIOEN[0] D[7..2] D[1..0] Reserved PIOD[49..48] This register is used to set the output level for GPIO pins. correspond to the GPIO[49..48]. The PIOEN[1..0] bits or the PIOD[49..48] bits The data written to the PIOD bit is output via the corresponding GPIO pin. The set value can be read by reading the PIOD bit. Pins set by this register are output-only. Pins set by this register are used exclusively from other function pins. Therefore, when using this register, set the enable bit to prohibit in the corresponding unit. The correspondence between PIOD bit and function pin is listed below. Table 18-4. Table of Correspondence between GPIO[48] and Function Pin PIOD Bit PIOD[48] GPIO pin GPIO[48] Function pin DBUS32 380 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) This chapter describes the PIU's operations and register settings. 19.1 GENERAL The PIU uses an on-chip A/D converter and detects the X and Y coordinates of pen contact locations on the touch panel and scans the general-purpose A/D input port. Since the touch panel control circuit and the A/D converter (conversion precision: 10 bits) are both on-chip, the touch panel is connected directly to the VR4102. The PIU's function, namely the detection of X and Y coordinates, is performed partly by hardware and partly by software. Hardware tasks : * Touch panel applied voltage control * Reception of coordinate data Software task : * Processing of coordinate data based on data sampled by hardware Features of the PIU's hardware tasks are described below. * Can be directly connected to touch panel with four-pin resistance layers (on-chip touch panel driver) * Interface for on-chip A/D converter * Voltage detection at three general-purpose AD ports and one audio input port * Operation of A/D converter based on various settings and control of voltage applied to touch panel * Sampling of X-coordinate and Y-coordinate data * Variable coordinate data sampling interval * Interrupt is triggered if pen touch occurs regardless of CPU operation mode (interrupts do not occur when in CPU hibernate mode) * Four dedicated buffers for up to two pages each of coordinate data * Four buffers for A/D port scan * Auto/manual options for coordinate data sampling start/stop control 381 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) 19.1.1 Block Diagrams Figure 19-1. PIU Peripheral Block Diagram VR4102 4 I/O buffer AUDIOIN Battery, etc. ADIN2 ADIN1 ADIN0 Touch panel TPY1 TPY0 TPX1 TPX0 I/O buffer Selector 1 ADC AIU 4 PIU * Touch panel A set of four pins are located at the edges of the X-axis and Y-axis resistance layers, and the two layers have high resistance when there is no pen contact and low resistance when there is pen contact. The resistance between the two edges of the resistance layers is about 1 k:. When a voltage is applied to both edges of the Y-axis resistance layer, the voltage (VY1 and VY2 in the figure below) is measures at the X-axis resistance layer's pins to determine the Y coordinate. Similarly, when a voltage is applied to both edges of the X-axis resistance layer, the voltage (VX1 and VX2 in the figure below) is measures at the Y-axis resistance layer's pins to determine the X coordinate. For greater precision, voltage applied to individual resistance-layer pins can be measured to obtain X and Y coordinate data based on four voltage measurements. The obtained coordinate data are stored to PIUPBnmREG register (n = 0, 1, m = 0 to 3). Figure 19-2. Equivalent Circuit of Coordinate Detection (a) Y-coordinate detection TPY1: 3V TPY1: 0V VY2 TPX0 VY1 TPY0: 0V TPY0: 3V TPX0 (b) X-coordinate detection TPY0 VX1 TPX0: 3V TPX1: 0V TPX0: 0V TPY0 VX2 TPX1: 3V 382 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) Figure 19-3. Internal Block Diagram of PIU Inside the VR4102 PIU Internal bus Scan sequencer Touch panel Internal bus controller TP interface controller PIU registers A/D converter General purpose A/D ports and Audio input port The PIU includes three blocks: an internal bus controller, a scan sequencer, and a TP interface controller. * Internal bus controller The internal bus controller controls the internal bus, DMA, the PIU registers, and interrupts and performs serial/parallel conversion of data from the A/D converter. * Scan sequencer The scan sequencer is used for PIU state management. * TP interface controller The TP interface controller is used to control the touch panel. 383 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) 19.2 SCAN SEQUENCER STATE TRANSITION Figure 19-4. Scan Sequencer State Transition Diagram Disable PIUPWR=0 PIUPWR=1 Reset=1 PIUSeqEn=0 ADPSStart= PIUSeqEN=1 & ADPortScan Release & AutoStop=1 ADPSStart=1 Interval auto TimeOut PIUSeqEn=0 PIUSeqEn= 1 PIUSeqEn=1 & ScanStart=1 PIUSeqEN=1 & PIUmode=01 Touch Standby WaitPenTouch Release ScanStart=1 DataScan PIUSeqEn=0 PIUSeqEn=0 or ScanStop=1 CMDScan * Disable state In this state, the A/D converter is in standby mode, the output pins are in touch detection mode (no PIU interrupt), and the input pins are in mask mode (to prevent misoperation when an undefined input is applied). * Standby state In this state, the unit is in scan idle mode. The touch panel is in low-power mode (0-V voltage is applied to the touch panel and the A/D converter is in disable mode). Normally, this is the state from which various mode settings are made. Caution State transitions occur when the PIUSEQEN bit is active, so the PIUSEQEN bit must be set as active after each mode setting has been completed. * ADPortScan state This is the state in which voltage is measured at the three A/D converter's general-purpose ports and one audio input port. After the A/D converter is activated and voltage data is obtained, the data is stored in the PIU's internal data buffer (PIUABxREG). After the four ports are scanned, a PadCMDIntr interrupt occurs. After this interrupt occurs, the ADPSSTART bit is automatically set as inactive and the state changes to the state in which the ADPSSTART bit was active. 384 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) * CMDScan state When in this state, the A/D converter operates using various settings. Voltage data from one port only is fetched based on a combination of the touch panel pin setting (TPX[1:0], TPY[1:0]) and the selection of an input port (TPX[1:0], TPY[1:0], AUDIOIN, ADIN[2:0]) to the A/D converter. Use PIUCMDREG to make the touch panel pin setting and to select the input port. * WaitPenTouch state This is the standby state that waits for a touch panel "touch" state. When the PIU detects a touch panel "touch" state, PenChgIntr (an internal interrupt in the PIU) occurs. At this point, if the PADAUTOSCAN bit is active, the state changes to the PenDataScan state. During the WaitPenTouch state, it is possible to change to Suspend mode because the panel state can be detected even when TClock has been stopped. * PenDataScan state This is the state in which touch panel coordinates are detected. The A/D converter is activated and the four sets of data for each coordinate are sampled. Caution If one complete pair of coordinates is not obtained during the interval between one pair of coordinates and the next coordinate data, a PadDataLostIntr interrupt occurs. * IntervalNextScan state This is the standby state that waits for the next coordinate sampling period or a touch panel "release" state. After the touch panel state is detected, the time period specified via PIUSIVLREG elapses before the transition to the PenDataScan state. If the PIU detects a "release" state within the specified time period, PenChgIntr (an internal interrupt in the PIU) occurs. At this point, the state changes to the WaitPenTouch state if the PADATSTOP bit is active. If the PADATSTOP bit is inactive, it changes to the PenDataScan state after the specified time period has elapsed. 385 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) 19.3 REGISTER SET The PIU registers are listed below. Table 19-1. PIU Registers Address 0x0B00 0122 0x0B00 0124 0x0B00 0126 0x0B00 0128 0x0B00 012A 0x0B00 0130 0x0B00 0132 0x0B00 013E 0x0B00 02A0 0x0B00 02A2 0x0B00 02A4 0x0B00 02A6 0x0B00 02A8 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W Register symbols PIUCNTREG PIUINTREG PIUSIVLREG PIUSTBLREG PIUCMDREG PIUASCNREG PIUAMSKREG PIUCIVLREG PIUPB00REG PIUPB01REG PIUPB02REG PIUPB03REG PIUPB10REG PIUPB11REG PIUPB12REG PIUPB13REG PIUAB0REG PIUAB1REG PIUAB2REG PIUAB3REG PIUPB04REG PIUPB14REG Function PIU Control register PIU Interrupt cause register PIU Data sampling interval register PIU A/D converter start delay register PIU A/D command register PIU A/D port scan register PIU A/D scan mask register PIU Check interval register PIU Page 0 Buffer 0 register PIU Page 0 Buffer 1 register PIU Page 0 Buffer 2 register PIU Page 0 Buffer 3 register PIU Page 1 Buffer 0 register PIU Page 1 Buffer 1 register PIU Page 1 Buffer 2 register PIU Page 1 Buffer 3 register PIU A/D scan Buffer 0 register PIU A/D scan Buffer 1 register PIU A/D scan Buffer 2 register PIU A/D scan Buffer 3 register PIU Page 0 Buffer 4 register PIU Page 1 Buffer 4 register 0x0B00 02AA R/W 0x0B00 02AC R/W 0x0B00 02AE R/W 0x0B00 02B0 0x0B00 02B2 0x0B00 02B4 0x0B00 02B6 R/W R/W R/W R/W 0x0B00 02BC R/W 0x0B00 02BE R/W These registers are described in detail below. 386 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) 19.3.1 PIUCNTREG (0x0B00 0122) (1/2) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 PENSTP R/W 0 0 D13 PENSTC R 0 0 D12 PADSTATE[2] D11 PADSTATE[1] D10 PADSTATE[0] D9 PADATSTOP D8 PADATSTART R 0 0 R 0 0 R 0 0 R/W 0 0 R/W 0 0 Bit Name D7 PADSCAN STOP R/W 0 0 D6 PADSCAN START R/W 0 0 D5 PADSCAN TYPE R/W 0 0 D4 D3 D2 PIUSEQEN D1 PIUPWR D0 PADRST PIUMODE[1] PIUMODE[0] R/W RTCRST Other resets R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 W 0 0 Bit D[15] D[14] Reserved PENSTP Name Function Write 0 when writing. 0 is returned after a read. Previous touch panel contact state 1 : Touch 0 : Release Current touch panel contact state 1 : Touch 0 : Release Scan sequencer status 111 : CmdScan 110 : IntervalNextScan 101 : PenDataScan 100 : WaitPenTouch 011 : RFU 010 : ADPortScan 001 : Standby 000 : Disable Sequencer auto stop setting during touch panel release state 1 : Auto stop after sampling data for one set of coordinates during release state 0 : No auto stop (even during release state) Sequencer auto start setting during touch panel touch state 1 : Auto start during touch state 0 : No auto start during touch state Forced stop setting for touch panel sequencer 1 : Forced stop after sampling data for one set of coordinates 0 : Do not stop D[13] PENSTC D[12..10] PADSTATE[2:0] D[9] PADATSTOP D[8] PADATSTART D[7] PADSCANSTOP 387 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) (2/2) Bit D[6] Name PADSCANSTART Function Start setting for touch panel sequencer 1 : Forced start 0 : Do not start Touch pressure sampling enable 1: Enable 0: Prohibit PIU mode setting 11 : RFU 10 : RFU 01 : Operate A/D converter using any command 00 : Sample coordinate data Scan sequencer operation enable 1 : Enable 0 : Prohibit PIU power mode setting 1 : Set PIU output as active and change to standby mode 0 : Set panel to touch detection state and set PIU operation stop enabled mode PIU reset. Once the PADRST bit is set to "1", it is automatically cleared to 0 after four TClock cycles. 1 : Reset 0 : Normal D[5] PADSCANTYPE D[4..3] PIUMODE[1..0] D[2] PIUSEQEN D[1] PIUPWR D[0] PADRST This register is used to make various settings for the PIU. Some bits in this register cannot be set in a specific state of scan sequencer. The combination of the setting of this register and the sequencer state is as follows. 388 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) Table 19-2. PIUCNTREG Bit Manipulation and States PIUCNTREG bit manipulation Disable PADRST PIUPWR Note 1 Scan sequencer's state Standby Disable ? Disable WaitPenTouch ? Note 3 WaitPenTouch Disable u u ? Standby Note 2 PenData Scan Disable u u ? Standby u u u u u u Note 4 0o1 0o1 1o0 Standby ? u ? u u u u u u u u PIUSEQEN 0o1 1o0 PADATSTART 0o1 1o0 PenDataScan u u u u u u PADATSTOP 0o1 1o0 PADSCANSTART 0o1 1o0 PenDataScan PADSCANSTOP 0o1 1o0 Standby PIUCNTREG bit manipulation IntervalNextScan PADRST PIUPWR Note 1 Scan sequencer's state ADPortScan Disable ? u ? Standby u u u u u u Note 4 CmdScan Disable ? u ? Standby u u u u u u Note 4 0o1 0o1 1o0 Disable ? u ? Standby u u u u u u Standby ? PIUSEQEN 0o1 1o0 PADATSTART 0o1 1o0 PADATSTOP 0o1 1o0 PADSCANSTART 0o1 1o0 PADSCANSTOP 0o1 1o0 Standby Standby Notes 1. 2. 3. 4. After "1" is written, the bit is automatically cleared to 0 after four TClock cycles. State transition occurs during touch state State transition occurs when PIUSEQEN = 1 State transition occurs after one set of data is sampled. transition occurs. This bit is cleared to 0 after the state Remarks : The bit change is retained but there is no state transition. u : Setting prohibited (operation not guaranteed) ? : Combination of state and bit status before setting does not exist 389 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) 19.3.2 PIUINTREG (0x0B00 0124) Bit Name R/W RTCRST Other resets D15 OVP R/W 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name D7 Reserved D6 PADCMD INTR R/W 0 0 D5 PADADP INTR R/W 0 0 D4 PADPAGE1 INTR R/W 0 0 D3 PADPAGE0 INTR R/W 0 0 D2 PADDLOST INTR R/W 0 0 D1 Reserved D0 PENCHG INTR R/W 0 0 R/W RTCRST Other resets R 0 0 R 0 0 Bit D[15] OVP Name Function Valid page ID bit (older valid page) 1 : Valid data older than page 1 buffer data is retained 0 : Valid data older than page 0 buffer data is retained Write 0 when writing. 0 is returned after a read. PIU command scan interrupt. Cleared to 0 when 1 is written. 1 : Indicates that command scan found valid data 0 : Indicates that command scan did not find valid data in buffer PIU A/D port scan interrupt . Cleared to 0 when 1 is written. 1 : Indicates that A/D port scan found valid data with "1" value in buffer 0 : Indicates that A/D port scan did not find valid data with "1" value in buffer PIU data buffer page 1 interrupt. Cleared to 0 when 1 is written. 1 : Valid data with "1" value is stored in page 1 of data buffer 0 : No valid data with "1" value in page 1 of data buffer PIU data buffer page 0 interrupt. Cleared to 0 when 1 is written. 1 : Valid data with "1" value is stored in page 0 of data buffer 0 : No valid data with "1" value in page 0 of data buffer A/D data timeout. Cleared to 0 when 1 is written. 1 : Not data with "1" value found within specified time 0 : No timeout Write 0 when writing. 0 is returned after a read. Change in touch panel contact state. Cleared to 0 when 1 is written. 1 : Change has occurred 0 : No change D[14..7] D[6] Reserved PADCMDINTR D[5] PADADPINTR D[4] PADPAGE1INTR D[3] PADPAGE0INTR D[2] PADDLOSTINTR D[1] D[0] Reserved PENCHGINTR This register is used to set or indicate an occurrence of PIU's various interrupt requests. 390 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) 19.3.3 PIUSIVLREG (0x0B00 0126) Bit Name D15 Reserved D14 Reserved D13 Reserved D12 Reserved D11 Reserved D10 SCANINT VAL[10] R/W 0 0 D9 SCANINT VAL[9] R/W 0 0 D8 SCANINT VAL[8] R/W 0 0 R/W RTCRST Other resets R 0 0 R 0 0 R 0 0 R 0 0 R 0 0 Bit Name D7 SCANINT VAL[7] R/W 0 0 D6 SCANINT VAL[6] R/W 0 0 D5 SCANINT VAL[5] R/W 0 0 D4 SCANINT VAL[4] R/W 0 0 D3 SCANINT VAL[3] R/W 0 0 D2 SCANINT VAL[2] R/W 1 1 D1 SCANINT VAL[1] R/W 1 1 D0 SCANINT VAL[0] R/W 1 1 R/W RTCRST Other resets Bit D[15..11] D[10..0] Reserved Name Function Write 0 when writing. 0 is returned after a read. Coordinate data scan sampling interval setting Interval = SCANINTVAL[10..0] x 30 Ps SCANINTVAL[10..0] This register sets the sampling interval for coordinate data sampling. The sampling interval for one pair of coordinate data is the value set via SCANINTVAL[10..0] multiplied by 30 Ps. Accordingly, the logical range of sampling intervals that can be set in 30-Ps units is from 0 Ps to 60,810 Ps (about 60 ms). Actually, if the sampling interval setting is shorter than the time required for obtaining a pair of coordinate data or ADPortScan data, a PIULostIntr interrupt will occur. If PIULostIntr interrupts occur frequently, set a longer interval time. Figure 19-5. Interval Times and States State Operation DataScan SASASASA Interval ADPortScan ST AAAA Interval T DataScan SASASASA Interval time Remarks S : Voltage stabilization standby time (STABLE(5:0) in PIUSTBLREG) A : A/D converter's conversion time (about 10Ps) T : Touch/release detection 391 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) 19.3.4 PIUSTBLREG (0x0B00 0128) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 STABLE[5] R/W 0 0 D4 STABLE[4] R/W 0 0 D3 STABLE[3] R/W 0 0 D2 STABLE[2] R/W 1 1 D1 STABLE[1] R/W 1 1 D0 STABLE[0] R/W 1 1 Bit D[15..6] D[5..0] Reserved Name Function Write 0 when writing. 0 is returned after a read. Panel applied voltage stabilization standby time Standby time = STABLE[5..0] u 30 Ps During A/D scan, this can be used as a timeout counter. STABLE[5..0] The voltage stabilization standby time for the voltage applied to the touch panel can be set via STABLE[5..0] in 30-Ps units between 0 Ps and 1,890 Ps. The setting of this register is also used as a timeout period during A/D scan. 392 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) 19.3.5 PIUCMDREG (0x0B00 012A) (1/2) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 STABLEON R/W 0 0 D11 TPYEN1 R/W 0 0 D10 TPYEN0 R/W 0 0 D9 TPXEN1 R/W 0 0 D8 TPXEN0 R/W 0 0 Bit Name R/W RTCRST Other resets D7 TPYD1 R/W 0 0 D6 TPYD0 R/W 0 0 D5 TPXD1 R/W 0 0 D4 TPXD0 R/W 0 0 D3 ADCMD[3] R/W 1 1 D2 ADCMD[2] R/W 1 1 D1 ADCMD[1] R/W 1 1 D0 ADCMD[0] R/W 1 1 Bit D[15..13] D[12] Reserved Name Function Write 0 when writing. 0 is returned after a read. Touch panel applied voltage stabilization time set (STABLE[5..0] of PIUSTBLREG) enable 1 : Retain panel voltage stabilization time 0 : Ignore panel voltage stabilization time (voltage stabilization standby time = 0) TPY port input/output switching during command scan 00 : TPY1 input, TPY0 input 01 : TPY1 input, TPY0 output 10 : TPY1 output, TPY0 input 11 : TPY1 output, TPY0 output TPX port input/output switching during command scan 00 : TPX1 input, TPX0 input 01 : TPX1 input, TPX0 output 10 : TPX1 output, TPX0 input 11 : TPX1 output, TPX0 output TPY output level during command scan 00 : TPY1 = "L", TPY0 = "L" 01 : TPY1 = "L", TPY0 = "H" 10 : TPY1 = "H", TPY0 = "L" 11 : TPY1 = "H", TPY0 = "H" TPYD value is ignored when TPYEN is set for input. TPX output level during command scan 00 : TPX1 = "L", TPX0 = "L" 01 : TPX1 = "L", TPX0 = "H" 10 : TPX1 = "H", TPX0 = "L" 11 : TPX1 = "H", TPX0 = "H" TPXD value is ignored when TPXEN is set for input. STABLEON D[11..10] TPYEN[1..0] D[9..8] TPXEN[1..0] D[7..6] TPYD[1..0] D[5..4] TPXD[1..0] 393 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) (2/2) Bit D[3..0] Name ADCMD[3..0] Function A/D converter input port selection for command scan 1111 : A/D converter standby mode request 1110 : RFU : 1000 : 0111 : 0110 : 0101 : 0100 : 0011 : 0010 : 0001 : 0000 : RFU AUDIOIN port ADIN2 port ADIN1 port ADIN0 port TPY1 port TPY0 port TPX1 port TPX0 port This register sets the switching or output level of ports during command scan operation. 394 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) 19.3.6 PIUASCNREG (0x0B00 0130) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name D7 Reserved D6 Reserved D5 Reserved D4 Reserved D3 Reserved D2 Reserved D1 TPPSCAN D0 ADPS START R/W 0 0 R/W RTCRST Other resets R 0 0 R 0 0 R 0 0 R 0 0 R 0 0 R 0 0 R/W 0 0 Bit D[15..2] D[1] Reserved TPPSCAN Name Function Write 0 when writing. 0 is returned after a read. Port selection for ADPortScan 1 : Select TPX[1:0], TPY[1:0] (for touch panel) as A/D port 0 : Select ADIN[3:0] (general-purpose) as A/D port ADPorScan start 1 : Start ADPortScan 0 : Do not perform ADPortScan D[0] ADPSSTART The ADPortScan begins when the ADPSSTART bit is set. After the ADPortScan is completed, the state returns to the state when ADPortScan was started. Automatically ADPSSTART bit is reset (to "0") after ADPortScan is completed. If the ADPortScan is not completed within the time period set via PIUSTBLREG's STABLE bits, a PIULostIntr interrupt occurs as a timeout interrupt. Some bits in this register cannot be set in a specific state of scan sequencer. The combination of the setting of this register and the sequencer state is as follows. 395 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) Table 19-3. PIUASCNREG Bit Manipulation and States PIUASCNREG bit manipulation Disable ADDSTART 0o1 1o0 TPPSCAN 0o1 1o0 u u Scan sequencer's state Standby Note WaitPenTouch u u PenData Scan u u ADPortScan Disable PIUCNTREG bit manipulation IntervalNextScan ADDSTART 0o1 1o0 TPPSCAN 0o1 1o0 u u u ? Scan sequencer's state ADPortScan Note CmdScan u u ? Standby ADPortScan Disable WaitPenTouch ? Note After ADPortScan is completed, the bit is automatically cleared to 0. Remarks : The bit change is retained but there is no state transition. u : Setting prohibited (operation not guaranteed) ? : Combination of state and bit status before setting does not exist 396 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) 19.3.7 PIUAMSKREG (0x0B00 0132) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 ADINM3 R/W 0 0 D6 ADINM2 R/W 0 0 D5 ADINM1 R/W 0 0 D4 ADINM0 R/W 0 0 D3 TPYM1 R/W 0 0 D2 TPYM0 R/W 0 0 D1 TPXM1 R/W 0 0 D0 TPXM0 R/W 0 0 Bit D[15..8] D[7] Reserved ADINM[3] Name Function Write 0 when writing. 0 is returned after a read. Audio input port mask Valid only during A/D scan. If masked, A/D conversions are not performed for the corresponding port. General-purpose A/D port mask Valid only during A/D scan. If masked, A/D conversions are not performed for the corresponding port. 1 : Mask 0 : Normal Touch panel A/D port TPY mask Valid only during A/D scan. If masked, A/D conversions are not performed for the corresponding port. 1 : Mask 0 : Normal Touch panel A/D port TPX mask Valid only during A/D scan. If masked, A/D conversions are not performed for the corresponding port. 1 : Mask 0 : Normal D[6..4] ADINM[2..0] D[3..2] TPYM[1..0] D[1..0] TPXM[1..0] This register is used to set masking of each A/D port. Its setting is valid only during A/D Port scanning operation. 397 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) 19.3.8 PIUCIVLREG (0x0B00 013E) Bit Name D15 Reserved D14 Reserved D13 Reserved D12 Reserved D11 Reserved D10 CHECKIN TVAL[10] R 0 0 D9 CHECKIN TVAL[9] R 0 0 D8 CHECKIN TVAL[8] R 0 0 R/W RTCRST Other resets R 0 0 R 0 0 R 0 0 R 0 0 R 0 0 Bit Name D7 CHECKIN TVAL[7] R 0 0 D6 CHECKIN TVAL[6] R 0 0 D5 CHECKIN TVAL[5] R 0 0 D4 CHECKIN TVAL[4] R 0 0 D3 CHECKIN TVAL[3] R 0 0 D2 CHECKIN TVAL[2] R 0 0 D1 CHECKIN TVAL[1] R 0 0 D0 CHECKIN TVAL[0] R 0 0 R/W RTCRST Other resets Bit D[15..11] D[10..0] Reserved Name Function Write 0 when writing. 0 is returned after a read. Interval count value CHKINTVAL[10..0] This register is used for real-time reading of internal register values being counted down based on the PIUSIVLREG setting. 398 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) 19.3.9 PIUPBnmREG (0x0B00 02A0 to 0x0B00 02AE, 0x0B00 02BC to 0x0B00 02BE) Remark n = 0, 1, m = 0 to 4 PIUPB04REG PIUPB10REG PIUPB11REG PIUPB12REG D13 Reserved R 0 0 PIUPB00REG (0x0B00 02A0) PIUPB01REG (0x0B00 02A2) PIUPB02REG (0x0B00 02A4) PIUPB03REG (0x0B00 02A6) Bit Name R/W RTCRST Other resets D15 VALID R/W 0 0 D14 Reserved R 0 0 (0x0B00 02BC) (0x0B00 02A8) (0x0B00 02AA) (0x0B00 02AC) D12 Reserved R 0 0 D11 Reserved R 0 0 PIUPB13REG PIUPB14REG (0x0B00 02AE) (0x0B00 02BE) D10 Reserved R 0 0 D9 D8 PADDATA[9] PADDATA[8] R/W 0 0 R/W 0 0 Bit Name R/W RTCRST Other resets D7 D6 D5 D4 D3 D2 D1 D0 PADDATA[7] PADDATA[6] PADDATA[5] PADDATA[4] PADDATA[3] PADDATA[2] PADDATA[1] PADDATA[0] R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 Bit D[15] VALID Name Indicates validity of data in PADDATA 1 : Valid 0 : Invalid Function D[14..10] D[9..0] Reserved PADDATA[9..0] Write 0 when writing. 0 is returned after a read. A/D converter's sampling data This register is used to store coordinate data and touch pressure data. There are four coordinate data buffers and one pair of touch pressure data buffer, each of which holds two pages of coordinate data or pressure data, and the addresses (register addresses) where the coordinate data or the pressure data is stored are fixed. coordinate data from the corresponding register in a valid page. The VALID bit, which indicates when the data is valid, is automatically rendered invalid when the page buffer interrupt cause (PIUPAGE0INTR or PIUPAGE1INTR in PIUINTREG) is cleared. Table 19-4. Detected Coordinates and Page Buffers Detected data X+ X Y+ Y Z (Touch pressure) Page0 Buffer PIUPB00REG PIUPB01REG PIUPB02REG PIUPB03REG PIUPB04REG Page1 Buffer PIUPB10REG PIUPB11REG PIUPB12REG PIUPB13REG PIUPB14REG Read 399 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) 19.3.10 PIUABnREG (0x0B00 02B0 to 0x0B00 02B6) Remark n = 0 to 3 PIUAB0REG PIUAB1REG PIUAB2REG PIUAB3REG Bit Name R/W RTCRST Other resets D15 VALID R/W 0 0 (0x0B00 02B0) (0x0B00 02B2) (0x0B00 02B4) (0x0B00 02B6) D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 PADDATA[9] R/W 0 0 D8 PADDATA[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 D6 D5 D4 D3 D2 D1 D0 PADDATA[7] PADDATA[6] PADDATA[5] PADDATA[4] PADDATA[3] PADDATA[2] PADDATA[1] PADDATA[0] R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 Bit D[15] VALID Name Indicates validity of data in PADDATA 1 : Valid 0 : Invalid Function D[14..10] D[9..0] Reserved PADDATA[9..0] Write 0 when writing. 0 is returned after a read. A/D converter's sampling data This register is used to store general-purpose A/D port sampling data, audio input port sampling data, and command scan data. There are four data buffers and the addresses (register address) where the data is stored are fixed. The VALID bit, which indicates when the data is valid, is automatically rendered invalid when the page buffer interrupt cause (PIUADPINTR in PIUINTREG) is cleared. Table 19-5. A/D Ports and Data Buffers Register During ADPortScan TPPScan = 0 PIUAB0REG PIUAB1REG PIUAB2REG PIUAB3REG ADIN0 ADIN1 ADIN2 AUDIOIN TPPScan = 1 TPX0 TPX1 TPY0 TPY1 CMDScanDATA During CMDScan 400 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) 19.4 REGISTER SETTING FLOW Be sure to reset the PIU before operating the scan sequencer. Setting initial values via a reset sets particular values for the sequence interval, etc., that are required. The registers for which these initial settings are necessary are listed below. PIUSITVLREG PIUSTBLREG ScanIntval [10:0] Stable [3:0] Interrupt mask cancellation settings are required for registers other than the PIU registers. Setting Interrupt mask clear Unit ICU ICU Clock mask clear CMU Register MSYSINTREG MPIUINTREG CMUCLKMSK Bit PIUINTR bit 6:0 MSKPIU 1 0x7F 1 Value (1) Register setting flow for voltage detection at A/D general-purpose ports and audio input port Standby, WaitPenTouch, or Interval state <1> PIUAMSKREG <2> PIUASCNREG p ADPortScan state <3> PIUASCNREG p Standby, WaitPenTouch, or Interval state (2) Register setting flow for auto scan coordinate detection Standby state <1> PIUCNTREG PIUMode [1:0] = 00 PADATSCAN = 1 PADATSTOP = 1 <2> PIUCNTREG p WaitPenTouch state PIUSEQEN = 1 ADPSSTART = 0 AD port and audio input port mask setting ADPSSTART = 1 401 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) (3) Register setting flow for manual scan coordinate detection Disable state <1> PIUCNTREG p Standby state <2> PIUCNTREG <3> PIUCNTREG p PenDataScan state (4) Register setting flow during Suspend mode transition Standby, WaitPenTouch, or Interval state <1> PIUCNTREG p Standby state <2> PIUCNTREG p Disable state (5) Register setting flow when returning from Suspend mode transition Disable state <1> PIUCNTREG p Standby state <2> PIUCNTREG PIUMODE [1:0] = 00 PADATSCAN = 1 PADATSTOP = 1 <3> PIUCNTREG p WaitPenTouch state Touch detected p PenDataScan state (6) Register setting flow for command scan Disable state <1> PIUCNTREG p Standby state <2> PIUCNTREG <3> PIUCNTREG <4> PIUCNTREG p CMDScan state PIUMODE [1:0] = 01 Set touch panel pins, select input port PIUSEQEN = 1 PIUPOWER = 1 PIUSEQEN = 1 PIUPWR = 1 PIUPWR = 1 PIUSEQEN = 0 PIUMODE[1:0] = 00 PADSCANSTART = 1 PIUSEQEN = 1 PIUPWR = 1 402 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) 19.5 RELATIONSHIPS AMONG TPX, TPY, AND ADIN PINS AND STATES State Power off (pen status detection) Low-power standby Pen status detection Voltage detection at general-purpose AD0 port Voltage detection at general-purpose AD1 port Voltage detection at general-purpose AD2 port Voltage detection at audio input port TPY1 = H, TPY0 = L, TPX0 = samp (X+) TPY1 = L, TPY0 = H, TPX0 = samp (X) TPX1 = H, TPX0 = L, TPY0 = samp (Y+) TPX1 = L, TPX0 = H, TPY0 = samp (Y) Touch pressure detection (Z) Remarks 0 1 L l d : Low level input : High level input : Low level output : A/D converter input : No touch interrupt input (via pull-down resistor) : Don't care PadState[2:0] Disable Standby WaitPenTouch/Interval ADPortScan ADPortScan ADPortScan ADPortScan PadDataScan PadDataScan PadDataScan PadDataScan PadDataScan TPX[1:0] HH 00 HH 00 00 00 00 I I HL LH HH TPY[1:0] D 00 D 00 00 00 00 HL LH I I d ADIN[2:0] AUDIOIN I I I I H : High level output D : Touch interrupt input (via pull-down resistor) 403 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) 19.6 TIMING 19.6.1 Touch/Release Detection Timing Touch/release detection does not use the A/D converter but instead uses the voltage level of the TPY1 pin to determine the panel's touch/release state. The following figure shows a touch/release detection timing diagram. Figure 19-6. Touch/Release Detection Timing State TPY,TPX (PADSCANTYPE = 0) TPY,TPX (PADSCANTYPE = 1) (TPY1) Standby WaitPenTouch DataScan Interval LowPower Touch detected X-, X+, Y-, Y+ Release detected LowPower L Touch detected 0 (Release) 1 (Touch) Z, X-, X+, Y-, Y+ Release detected 1 (Touch) 0 (Release) 19.6.2 A/D Port Scan Timing The A/D port scan function sequentially scans the A/D converter's four input channel port pins and stores the data in the data buffer used for A/D port scanning. The following figure shows an A/D port scan timing diagram. Figure 19-7. A/D Port Scan Timing State XXX ADPortScan XXX AUDIOIN, ADIN[2:0] ADPSSTART bit (PIUASCNREG) AUDIOIN, ADIN2, ADIN1, ADIN0 XXX state: Standby, WaitPenTouch, or Interval 404 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) 19.7 DATA LOSS INTERRUPT CONDITIONS The PIU issues a PIUDataLostIntr interrupt when any of the following four conditions exist. Once a PIUDataLostIntr interrupt occurs, the sequencer is forcibly changed to the Standby state. 1. 2. 3. 4. Data for one coordinate has not been obtained within the interval period The A/D port scan has not been completed within the time set via PIUSTBLREG Transfer of the next coordinate data has begun while valid data for both pages remains in the buffer The next data transfer starts while there is valid data in the ADPortScan buffer (1) When data for one coordinate has not been obtained within the interval period Cause This condition occurs when the AIU has exclusive use of the A/D converter and the PIU is therefore unable to use the A/D converter. If this data loss condition occurs frequently, implement a countermeasure that temporarily prohibits the AIU's use of the A/D converter. Response After clearing the cause of the PIUDataLostIntr interrupt, set PIUCIUCNTREG's PADATSTART bit or PADSCANSTART bit to restart the coordinate detection operation. Once the PIUDataLostIntr interrupt is cleared, the page in which the loss occurred becomes invalid. If the valid data prior to the data loss is needed, be sure to save the data that is being stored in the page buffer before clearing the PIUDataLostIntr interrupt. (2) When the A/D port scan has not been completed within the time set via PIUSTBLREG Cause Same as cause of condition 1 Response After clearing the cause of the PIUDataLostIntr interrupt, set PIUASCNREG's ADPSSTART bit to restart the A/D port scan operation. Once the PIUDataLostIntr interrupt is cleared, the page in which the loss occurred becomes invalid. If the valid data prior to the data loss is needed, be sure to save the data that is being stored in the page buffer before clearing the PIUDataLostIntr interrupt. (3) When transfer of the next coordinate data has begun while valid data for both pages remains in the buffer Cause This condition is caused when the data buffer contains two pages of valid data (both the PIUPAGE1INTR and PIUPAGE0INTR interrupts have occurred) but the valid data has not been processed. If the A/D converter is used frequently, this may shorten the time that would normally be required from when both pages become full until when the data loss occurs. 405 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) Response In condition 3, valid data contained in the pages when the PIUDataLostIntr interrupt occurs is never overwritten. After two pages of valid data are processed, clear the causes of the three interrupts (PIUDataLostIntr, PIUPAGE1INTR, and PIUPAGE0INTR). After clearing these interrupt causes, set the PADATSTART bit or PADSCANSTART bit of PIUCNTREG to restart the coordinate detection operation. (4) When the next data transfer starts while there is valid data in the ADPortScan buffer Cause This condition is caused when valid data is not processed even while the ADPortScan buffer holds valid data (PADADPINTR interrupt occurrence). Response In condition 4, valid data contained in the buffer when the PIUDataLostIntr interrupt occurs is never overwritten. After valid data in the buffer is processed, clear the causes of the two interrupts (PIUDataLostIntr, PADADPINTR). After clearing these interrupt causes, set the ADPSSTART bit of PIUASCNREG to restart the generalpurpose A/D port scan. 406 CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT) 19.8 COMPARISON OF VR4102 AND VR4101TM Table 19-6. Comparison of PIUs of VR4102 and VR4101 Item A/D converter Data transfer Data buffers On-chip (10 bits) Transfer to buffer in PIU Four buffers (two pages each) for coordinate data only Four buffers for A/D scan Coordinate data scan Command scan A/D scan VR4102 VR4101 External (10/12 bits) DMA transfer One buffer Scan types Coordinate data scan Command scan Main battery scan Sub battery scan Standby 4 bits A/D port scan activation states Panel applied voltage stabilization standby time counter Panel applied voltage during lowvoltage mode Panel state during disable state Standby, WaitPen Touch, Interval 6 bits All four touch panel pins are at low level All four touch panel pins are at Hi-Z Touch detection state (Interrupts do not occur when CPU is in Hibernate mode.) Valid data is always retained All four touch panel pins are at Hi-Z Handling of valid data when data loss occurs Data interrupt Valid data is overwritten Three types of special-purpose interrupts (two coordinate data interrupts, A/D scan interrupt, and command scan interrupt) No Two types of page boundary interrupts PIUDataRdyIntr Yes 407 [MEMO] 408 CHAPTER 20 AIU (AUDIO INTERFACE UNIT) This chapter describes the AIU's operations and register settings. 20.1 GENERAL The AIU supports speaker output and MIC input operations. It is also used to set the A/D and D/A converter operations. 20.2 REGISTER SET The AIU registers are listed below. Table 20-1. AIU Registers Address 0x0B00 0160 0x0B00 0162 0x0B00 0166 0x0B00 0168 0x0B00 016A 0x0B00 0170 0x0B00 0172 0x0B00 0174 0x0B00 0178 0x0B00 017A 0x0B00 017C R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register Symbols MDMADATREG SDMADATREG SODATREG SCNTREG SCNVRREG MIDATREG MCNTREG MCNVRREG DVALIDREG SEQREG INTREG Function Mike DMA Data Register Speaker DMA Data Register Speaker Output Data Register Speaker Output Control Register Speaker Conversion Rate Register Mike Input Data Register Mike Input Control Register Mike Conversion Rate Register Data Valid Register Sequential Register Interrupt Register These registers are described in detail below. 409 CHAPTER 20 AIU (AUDIO INTERFACE UNIT) 20.2.1 MDMADATREG (0x0B00 0160) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 MDMA[9] R/W 1 1 D8 MDMA[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 MDMA[7] R/W 0 0 D6 MDMA[6] R/W 0 0 D5 MDMA[5] R/W 0 0 D4 MDMA[4] R/W 0 0 D3 MDMA[3] R/W 0 0 D2 MDMA[2] R/W 0 0 D1 MDMA[1] R/W 0 0 D0 MDMA[0] R/W 0 0 Bit D[15:10] D[9:0] Reserved Name Function Write 0 when writing. 0 is returned after a read. MIC input DMA data (from MIDATREG to buffer) MDMA[9:0] This register is used prior to DMA transfer to store 10-bit data that has been converted by the A/D converter and stored in MIDATREG. Write is used for debugging and is enabled when AIUMEN bit of SEQREG is set to 1. This register is cleared (0x0200) by resetting AIUMEN bit of SEQREG to 0. 410 CHAPTER 20 AIU (AUDIO INTERFACE UNIT) 20.2.2 SDMADATREG (0x0B00 0162) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 SDMA[9] R/W 1 1 D8 SDMA[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 SDMA[7] R/W 0 0 D6 SDMA[6] R/W 0 0 D5 SDMA[5] R/W 0 0 D4 SDMA[4] R/W 0 0 D3 SDMA[3] R/W 0 0 D2 SDMA[2] R/W 0 0 D1 SDMA[1] R/W 0 0 D0 SDMA[0] R/W 0 0 Bit D[15:10] D[9:0] Reserved Name Function Write 0 when writing. 0 is returned after a read. Speaker output DMA data (from buffer to SODATREG) SDMA[9:0] This register is used to store 10-bit DMA data for speaker output. When SODATREG is empty, the data is transferred to SODATREG. Write is used for debugging and is enabled when AIUSEN bit of SEQREG is set to 1. This register is cleared (0x0200) by resetting AIUSEN bit of SEQREG to 0. 411 CHAPTER 20 AIU (AUDIO INTERFACE UNIT) 20.2.3 SODATREG (0x0B00 0166) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 SODAT[9] R/W 1 1 D8 SODAT[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 SODAT[7] R/W 0 0 D6 SODAT[6] R/W 0 0 D5 SODAT[5] R/W 0 0 D4 SODAT[4] R/W 0 0 D3 SODAT[3] R/W 0 0 D2 SODAT[2] R/W 0 0 D1 SODAT[1] R/W 0 0 D0 SODAT[0] R/W 0 0 Bit D[15:10] D[9:0] Reserved Name Function Write 0 when writing. 0 is returned after a read. Speaker output data (from SDMADATREG to D/A converter) SODAT[9:0] This register is used to store 10-bit DMA data for speaker output. is cleared (0x0200) by resetting AIUSEN bit of SEQREG to 0. Data is sent from the D/A converter to SDMADATREG. Write is used for debugging and is enabled when AIUSEN bit of SEQREG is set to 1. This register 412 CHAPTER 20 AIU (AUDIO INTERFACE UNIT) 20.2.4 SCNTREG (0x0B00 0168) Bit Name R/W RTCRST Other resets D15 DAENAIU R/W 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 SSTATE R 0 0 D2 Reserved R 0 0 D1 SSTOPEN R/W 0 0 D0 Reserved R 0 0 Bit D[15] DAENAIU Name Function This is the speaker D/A enable bit. It controls the ON/OFF status of the Vref input to the D/A converter's ladder resistors. 1 : Vref ON 0 : Vref OFF Write 0 when writing. 0 is returned after a read. Indicates speaker operation state 1 : In operation 0 : Stopped Write 0 when writing. 0 is returned after a read. Speaker output DMA transfer 1-page boundary interrupt stop 1 : Stop DMA request at 1-page boundary 0 : Stop DMA request at 2-page boundary Write 0 when writing. 0 is returned after a read. D[14:4] D[3] Reserved SSTATE D[2] D[1] Reserved SSTOPEN D[0] Reserved This register is used to control the AIU's speaker block. DAENAIU bit controls the connection of DVDD and Vref input to ladder type resistors in the D/A converter. Setting this bit to 0 (OFF) allows low power consumption when not using the D/A converter. When using D/A converter, this bit must be set following the sequence described in 20.3. The contents of SSTATE bit is valid only when AIUSEN bit of SEQREG is set to 1. 413 CHAPTER 20 AIU (AUDIO INTERFACE UNIT) 20.2.5 SCNVRREG (0x0B00 016A) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 SCNVR[2] R/W 0 0 D1 SCNVR[1] R/W 0 0 D0 SCNVR[0] R/W 0 0 Bit D[15:3] D[2:0] Reserved Name Function Write 0 when writing. 0 is returned after a read. D/A Conversion Rate 111 : RFU : 101 : RFU 100 : 8 ksps 011 : RFU 010 : 44.1 ksps 001 : 22.05 ksps 000 : 11.025 ksps SCNVR[2:0] This register is used to select a conversion rate for the D/A converter. 414 CHAPTER 20 AIU (AUDIO INTERFACE UNIT) 20.2.6 MIDATREG (0x0B00 0170) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 MIDAT[9] R/W 1 1 D8 MIDAT[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 MIDAT[7] R/W 0 0 D6 MIDAT[6] R/W 0 0 D5 MIDAT[5] R/W 0 0 D4 MIDAT[4] R/W 0 0 D3 MIDAT[3] R/W 0 0 D2 MIDAT[2] R/W 0 0 D1 MIDAT[1] R/W 0 0 D0 MIDAT[0] R/W 0 0 Bit D[15:10] D[9:0] Reserved Name Function Write 0 when writing. 0 is returned after a read. MIC input data (from A/D to MDMADATREG) MIDAT[9:0] This register is used to store 10-bit speaker input data that has been converted by the A/D converter. Data is sent to MDMADATREG and is received from the A/D converter. Write is used for debugging and is enabled when AIUMEN bit of SEQREG is set to 1. This register is cleared (0x0200) by resetting AIUMEN bit of SEQREG to 0. 415 CHAPTER 20 AIU (AUDIO INTERFACE UNIT) 20.2.7 MCNTREG (0x0B00 0172) Bit Name R/W RTCRST Other resets D15 ADENAIU R/W 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 MSTATE R 0 0 D2 Reserved R 0 0 D1 MSTOPEN R/W 0 0 D0 ADREQAIU R 0 0 Bit D[15] ADENAIU Name Function This is the MIC A/D enable bit. It controls the ON/OFF status of the Vref input to the D/A converter's ladder resistors in the A/D converter. 1 : Vref ON 0 : Vref OFF Write 0 when writing. 0 is returned after a read. Indicates MIC operation state (= AIUMEN) 1 : In operation 0 : Stopped Write 0 when writing. 0 is returned after a read. MIC input DMA transfer 1-page boundary interrupt stop 1 : Stop DMA request at 1-page boundary 0 : Stop DMA request at 2-page boundary A/D use request bit 1 : Request 0 : Normal D[14:4] D[3] Reserved MSTATE D[2] D[1] Reserved MSTOPEN D[0] ADREQAIU This register is used to control the AIU's MIC block. ADENAIU bit controls the connection of AVDD and Vref input to ladder type resistors in the A/D converter. Setting this bit to 0 (OFF) allows low power consumption when not using the A/D converter. When using A/D converter, this bit must be set following the sequence described in 20.3. The contents of MSTATE bit is valid only when AIUMEN bit of SEQREG is set to 1. This unit has priority when a conflict occurs with the PIU in relation to A/D requests. 416 CHAPTER 20 AIU (AUDIO INTERFACE UNIT) 20.2.8 MCNVRREG (0x0B00 0174) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 MCNVR[2] R/W 0 0 D1 MCNVR[1] R/W 0 0 D0 MCNVR[0] R/W 0 0 Bit D[15:3] D[2:0] Reserved Name Function Write 0 when writing. 0 is returned after a read. A/D Conversion Rate 111 : RFU : 101 : RFU 100 : 8 ksps 011 : RFU 010 : 44.1 ksps 001 : 22.05 ksps 000 : 11.025 ksps MCNVR[2:0] This register is used to select a conversion rate for the A/D converter. 417 CHAPTER 20 AIU (AUDIO INTERFACE UNIT) 20.2.9 DVALIDREG (0x0B00 0178) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 SODATV R/W 0 0 D2 SDMAV R/W 0 0 D1 MIDATV R/W 0 0 D0 MDMAV R/W 0 0 Bit D[15:4] D[3] Reserved SODATV Name Function Write 0 when writing. 0 is returned after a read This indicates when valid data has been stored in SODATREG. 1 : Valid data exists 0 : No valid data This indicates when valid data has been stored in SDMADATREG. 1 : Valid data exists 0 : No valid data This indicates when valid data has been stored in MIDATREG. 1 : Valid data exists 0 : No valid data This indicates when valid data has been stored in MDMAREG. 1 : Valid data exists 0 : No valid data D[2] SDMAV D[1] MIDATV D[0] MDMAV This register indicates when valid data has been stored in SODATREG, SDMADATREG, MIDATREG, or MDMAREG. If data has been written directly to SODATREG, SDMADATREG, MIDATREG, or MDMAREG via software, the bits in this register are not active, so write "1" via software. Write is used for debugging and is enabled when AIUSEN or AIUMEN bit of SEQREG is set to 1. If AIUSEN = 0 or AIUMEN = 0 in SEQREG, then SODATV = SDMAV = 0 or MIDATV = MDMAV = 0. 418 CHAPTER 20 AIU (AUDIO INTERFACE UNIT) 20.2.10 SEQREG (0x0B00 017A) Bit Name R/W RTCRST Other resets D15 AIURST R/W 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 AIUMEN R/W 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 Reserved R 0 0 D0 AIUSEN R/W 0 0 Bit D[15] AIURST Name AIU reset via software 1 : Reset 0 : Normal Function D[14:5] D[4] Reserved AIUMEN Write 0 when writing. 0 is returned after a read. MIC block operation enable, DMA enable 1 : Enable operation 0 : Disable operation Write 0 when writing. 0 is returned after a read. Speaker block operation enable, DMA enable 1 : Enable operation 0 : Disable operation D[3:1] D[0] Reserved AIUSEN This register is used to enable/disable the AIU's operation. 419 CHAPTER 20 AIU (AUDIO INTERFACE UNIT) 20.2.11 INTREG (0x0B00 017C) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 MENDINTR R/W 0 0 D10 MINTR R/W 0 0 D9 MIDLEINTR R/W 0 0 D8 MSTINTR R/W 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 SENDINTR R/W 0 0 D2 SINTR R/W 0 0 D1 SIDLEINTR R/W 0 0 D0 Reserved R 0 0 Bit D[15:12] D[11] Reserved Name Function Write 0 when writing. 0 is returned after a read. MIC DMA 2 page interrupt. Cleared to 0 when 1 is written. 1 : Occurred 0 : Normal MIC DMA 1 page interrupt. Cleared to 0 when 1 is written. 1 : Occurred 0 : Normal MIC idle interrupt (receive data loss). Cleared to 0 when 1 is written. 1 : Occurred 0 : Normal MIC receive complete interrupt. Cleared to 0 when 1 is written. 1 : Occurred 0 : Normal Write 0 when writing. 0 is returned after a read. SPEAKER DMA 2 page interrupt. Cleared to 0 when 1 is written. 1 : Occurred 0 : Normal SPEAKER DMA 1 page interrupt. Cleared to 0 when 1 is written. 1 : Occurred 0 : Normal SPEAKER idle interrupt (mute). Cleared to 0 when 1 is written. 1 : Occurred 0 : Normal Write 0 when writing. 0 is returned after a read. MENDINTR D[10] MINTR D[9] MIDLEINTR D[8] MSTINTR D[7:4] D[3] Reserved SENDINTR D[2] SINTR D[1] SIDLEINTR D[0] Reserved This register indicates the AIU's interrupt status. When data is received from the A/D converter, MIDLEINTR is set if valid data still exists in MIDATREG (MIDATV = 1). In this case, MIDATREG is overwritten. MSTINTR is set when data is received in MDMADATREG. When data is passed to the D/A converter, SIDLEINTR is set if there is no valid data in SODATREG (SODATV = 0). However, this interrupt is valid only after AIUSEN = 1, after which SODATV = 1. 420 CHAPTER 20 AIU (AUDIO INTERFACE UNIT) 20.3 OPERATION SEQUENCE 20.3.1 Output (Speaker) 1. 2. 3. 4. 5. Set conversion rate (0x0B00 016A: SCNVR = arbitrary) Set output data area to DMAAU DMA enable in DCU Set D/A converter's Vref to ON (0x0B00 0168: DAENAIU = 1) Wait for Vref resistor stabilization time (about 5 Ps) (use the RTC counter) Even if speaker power is set to ON without waiting for Vref resistor stabilization time and speaker operation is enabled, speaker output starts after the period calculated with the formula below. 5 + 1/conversion rate (44.1, 22.05, 11.025, or 8) (Ps) 6. 7. Set speaker power ON via GPIO. Speaker operation enable (0x0B00 017A: AIUSEN = 1) DMA request Receive acknowledge and DMA data from DMA 0x0B00 0178: SDMAV = SODATV = 1 Output 10-bit data (0x0B00 0166: SODAT) to D/A converter SODATV = 0, SDMAV = 1 Send SDMADATREG data to SODATREG SODATV = 1, SDMAV = 0 Output DMA request and store the second data to SDMADATREG SODATV = 1, SDMAV = 1 Refresh data at each conversion timing interval (becomes SIDLEINTR = 1 when DMA is slow and SODATV = 0 during conversion timing interval, and (mute) interrupt occurs) DMA page boundary interrupt occurs at page boundary Page interrupt is cleared when output continues 8. 9. Speaker operation to disable (0x0B00 017A: AIUSEN = 0) Set speaker power OFF via GPIO. 10. Set D/A converter's Vref to OFF (0x0B00 0168: DAENAIU = 0) 11. DMA disable in DCU 421 CHAPTER 20 AIU (AUDIO INTERFACE UNIT) 20.3.2 Input (MIC) 1. 2. 3. 4. Set conversion rate (0x0B00 0174: MCNVR = arbitrary) Set input data area in DMAAU DMA enable in DCU Set A/D converter's Vref to ON (0x0B00 0172: ADENAIU = 1) MIC power can be set ON and MIC operation can be enabled without waiting for Vref resistor stabilization time (about 5 Ps). However, in such a case, sampling starts after the period calculated with the formula below. 5 + 1/conversion rate (44.1, 22.05, 11.025, or 8) (Ps) 5. 6. Set MIC power ON via GPIO. MIC operation enable (0x0B00 017A: AIUMEN = 1) Output A/D request (ADREQAIU) to A/D converter Return acknowledge (aiuadack) and 10-bit conversion data from A/D converter Store data in MIDATREG 0x0B00 0178: MDMAV = 0, MIDATV = 1 Transfer data from MIDATREG to MDMADATREG MDMAV = 1, MIDATV = 0 The INTMST value becomes "1" and an interrupt (receive complete) occurs Issue DMA request and store MIDMADATREG data to memory. MDMAV = 0, MIDATV = 0 An A/D request is issued once per conversion timing interval and 10-bit data is received (becomes MIDLEINTR = 1 when DMA is slow and MIDATV = 1 during conversion timing interval, and (data loss) interrupt occurs) DMA page boundary interrupt occurs at page boundary (Page interrupt is cleared when output continues) 7. 8. 9. MIC operation to disable (0x0B00 017A: AIUMEN = 0) Set MIC power OFF via GPIO Set A/D converter's Vref to OFF (0x0B00 0172: AIUADEN = 0) 10. DMA disable in DCU 422 CHAPTER 21 KIU (KEYBOARD INTERFACE UNIT) This chapter describes the KIU's operations and register settings. 21.1 GENERAL The KIU includes 12 scan lines and 8 detection lines. The number of key inputs to be detected can be selected from 96/80/64, by switching the number of scan lines from 12/10/8. The register can be set to enable the 12 scan lines to be used as a general-purpose output port. 21.2 REGISTER SET The KIU registers are listed below. Table 21-1. KIU Registers Address 0x0B00 0180 0x0B00 0182 0x0B00 0184 0x0B00 0186 0x0B00 0188 0x0B00 018A 0x0B00 0190 0x0B00 0192 0x0B00 0194 0x0B00 0196 0x0B00 0198 0x0B00 019A 0x0B00 019C 0x0B00 019E R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W W R/W R/W Register Symbols KIUDAT0 KIUDAT1 KIUDAT2 KIUDAT3 KIUDAT4 KIUDAT5 KIUSCANREP KIUSCANS KIUWKS KIUWKI KIUINT KIURST KIUGPEN SCANLINE Function KIU Data0 Register KIU Data1 Register KIU Data2 Register KIU Data3 Register KIU Data4 Register KIU Data5 Register KIU Scan/Repeat Register KIU Scan Status Register KIU Wait Keyscan Stable Register KIU Wait Keyscan Interval Register KIU Interrupt Register KIU Reset Register KIU General Purpose Output Enable KIU Scan Line Register 423 CHAPTER 21 KIU (KEYBOARD INTERFACE UNIT) 21.2.1 KIUDATn (0x0B00 0180 to 0x0B00 018A) Remark n = 0 to 5 KIUDAT0 (0x0B00 0180) KIUDAT1 (0x0B00 0182) KIUDAT2 (0x0B00 0184) KIUDAT3 (0x0B00 0186) KIUDAT4 (0x0B00 0188) KIUDAT5 (0x0B00 018A) Bit Name R/W RTCRST Other resets D15 D14 D13 D12 D11 D10 D9 KEYDAT[9] R/W 0 0 D8 KEYDAT[8] R/W 0 0 KEYDAT[15] KEYDAT[14] KEYDAT[13] KEYDAT[12] KEYDAT[11] KEYDAT[10] R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 Bit Name R/W RTCRST Other resets D7 KEYDAT[7] R/W 0 0 D6 KEYDAT[6] R/W 0 0 D5 KEYDAT[5] R/W 0 0 D4 KEYDAT[4] R/W 0 0 D3 KEYDAT[3] R/W 0 0 D2 KEYDAT[2] R/W 0 0 D1 KEYDAT[1] R/W 0 0 D0 KEYDAT[0] R/W 0 0 Bit D[15..8] D[7..0] Name KEYDAT[15..8] KEYDAT[7..0] Scan data from odd-numbered scans Scan data from even-numbered scans Function These registers are used to hold key scan data. Each KIU data register is able to hold the data from one scan operation. How scan data is input to the registers is as below. Bit Register KIUDAT0 KIUDAT1 KIUDAT2 KIUDAT3 KIUDAT4 KIUDAT5 Scan[1] Scan[3] Scan[5] Scan[7] Scan[9] Scan[11] Scan[0] Scan[2] Scan[4] Scan[6] Scan[8] Scan[10] KEYDAT[15..8] KEYDAT[7..0] 424 CHAPTER 21 KIU (KEYBOARD INTERFACE UNIT) 21.2.2 KIUSCANREP (0x0B00 0190) Bit Name R/W RTCRST Other resets D15 KEYEN R/W 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 STPREP[5] R/W 0 0 D8 STPREP[4] R/W 0 0 Bit Name R/W RTCRST Other resets D7 STPREP[3] R/W 0 0 D6 STPREP[2] R/W 0 0 D5 STPREP[1] R/W 0 0 D4 STPREP[0] R/W 0 0 D3 SCANSTP R/W 0 0 D2 SCANSTART D1 ATSTP R/W 0 0 D0 ATSCAN R/W 1 1 R/W 0 0 Bit D[15] KEYEN Name Key scan 1 : Enable 0 : Prohibit Function D[14..10] D[9..4] Reserved STPREP[5..0] Write 0 when writing. 0 is returned after a read. Key scan sequencer stop count setting 111111 : 63 times : 000001 : 1 time 000000 : 64 times Key scan stop 1 : Stop 0 : Operate Key scan start 1 : Start 0 : Stop Key auto stop setting 1 : Auto stop 0 : Not auto stop Key auto scan setting 1 : Auto scan 0 : Not auto scan D[3] SCANSTP D[2] SCANSTART D[1] ATSTP D[0] ATSCAN This register is used to enable operation of the key scan unit and to make settings for key scan and the key scan sequencer. * Key scan sequencer stop count setting This sets the number of key scan sequencer stops when no keys are being pressed. 425 CHAPTER 21 KIU (KEYBOARD INTERFACE UNIT) * Key scan stop When the SCANSTP bit is set to "1", the key scan sequencer stops. However, if this bit is set to "1" during a key scan operation, the key scan sequencer stops after the current set of key data is received. * Key scan start When the SCANSTART bit is set to "1", the key scan sequencer starts regardless of key contact detection. * Key scan auto stop setting When the ATSTOP bit is set to "1", the key scan sequencer stops automatically when the data remains all zeros for the number of key scan times specified by STOPREP. * Key auto scan setting When the ATSCAN bit is set to "1", the key scan operation automatically starts after key contact is detected. 426 CHAPTER 21 KIU (KEYBOARD INTERFACE UNIT) 21.2.3 KIUSCANS (0x0B00 0192) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 SSTAT[1] R 0 0 D0 SSTAT[0] R 0 0 Bit D[15..2] D[1..0] Reserved Name Function Write 0 when writing. 0 is returned after a read. KIU sequencer status 11 : Scanning 10 : Interval Next Scan 01 : WaitKeyIn 00 : Stopped SSTAT[1..0] This register indicates the current KIU sequencer status. 427 CHAPTER 21 KIU (KEYBOARD INTERFACE UNIT) Details of the status of the KIU sequencer are described below. * Scanning: * Interval next scan: This is the state where the scan sequencer performs key scan to load key data. This is the state where the scan of a set of key data Note has completed and waiting for the start of the next key scan. The interval after the completion of the scan of a set of key data until the start of the next scan is set on the KIUWKIREG. Note The number of data bits depends on the number of KSCAN pins used as below. The number of KSCAN pins is set in SCANLINE register. KSCAN pins 8 10 12 * Wait Key in: Number of data bits 64 bits 80 bits 96 bits This is the state of waiting for key input in the key auto scan mode. When the scan sequencer is enabled while ATSCAN bit of KIUSCANREP register is set to 1, the VR4102 waits for key input in this state. In this case, all outputs of the KSCAN pins Note are in high level. When shifting the CPU to Suspend mode (or Standby mode with TClock masked), be sure to set the KIU to the auto scan mode before the shift and confirm that the sequencer in the Wait key in state. Note The number of pins is set in LINE[1..0] bits of SCANLINE register as below. LINE[1..0] 10 01 00 * Stopped: Number of KSCAN pins 8 10 12 This is the state where the sequencer is disabled. 428 CHAPTER 21 KIU (KEYBOARD INTERFACE UNIT) 21.2.4 KIUWKS (0x0B00 0194) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 T3CNT[4] R/W 1 1 D13 T3CNT[3] R/W 1 1 D12 T3CNT[2] R/W 1 1 D11 T3CNT[1] R/W 1 1 D10 T3CNT[0] R/W 1 1 D9 T2CNT[4] R/W 1 1 D8 T2CNT[3] R/W 1 1 Bit Name R/W RTCRST Other resets D7 T2CNT[2] R/W 1 1 D6 T2CNT[1] R/W 1 1 D5 T2CNT[0] R/W 1 1 D4 T1CNT[4] R/W 1 1 D3 T1CNT[3] R/W 1 1 D2 T1CNT[2] R/W 1 1 D1 T1CNT[1] R/W 1 1 D0 T1CNT[0] R/W 1 1 Bit D[15] D[14..10] Reserved Name Function Write 0 when writing. 0 is returned after a read. Wait time setting ((T3CNT[4..0] + 1) * 30 Ps) 11111 : 960 Ps : 00001 : 60 Ps 00000 : RFU Off time setting ((T2CNT[4..0] + 1) * 30 Ps) 11111 : 960 Ps : 00001 : 60 Ps 00000 : RFU Stabilization time setting ((T1CNT[4..0] + 1) * 30 Ps) 11111 : 960 Ps : 00001 : 60 Ps 00000 : RFU T3CNT[4..0] D[9..5] T2CNT[4..0] D[4..0] T1CNT[4..0] This register is used to set the wait time between when the key scan sequencer sets the KSCAN pin "High" during a key matrix scan and when the status is read from the KPORT pin. The T1CNT bit is used to set the stabilization time between when voltage is applied to the KSCAN pin and when the key scan data is read. The T2CNT bit is used to set the time between when the key data is read and when voltage applied to the KSCAN pin is set to "OFF". The T3CNT bit is used to set the time between when voltage applied to the KSCAN pin is set to "OFF" and when voltage can be again applied to the KSCAN pin. The status of output from the KSCAN pins and the timing of KPORT sampling are shown below. 429 CHAPTER 21 KIU (KEYBOARD INTERFACE UNIT) T1 T2 T3 T1 T2 KSCAN[n] Hi-Z KPORT sampling Hi-Z KSCAN[n+1] Hi-Z KPORT sampling Hi-Z 21.2.5 KIUWKI (0x0B00 0196) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 WINTVL[9] R/W 0 0 D8 WINTVL[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 WINTVL[7] R/W 0 0 D6 WINTVL[6] R/W 0 0 D5 WINTVL[5] R/W 0 0 D4 WINTVL[4] R/W 0 0 D3 WINTVL[3] R/W 0 0 D2 WINTVL[2] R/W 0 0 D1 WINTVL[1] R/W 0 0 D0 WINTVL[0] R/W 0 0 Bit D[15..10] D[9..0] Reserved Name Function Write 0 when writing. 0 is returned after a read. Key scan interval time setting (WINTVL[9..0]*30 Ps) 1111111111 : 30690 Ps : 0000000001 : 30 Ps 0000000000 : No Wait WINTVL[9..0] This register is used to set the interval time between when one set of key data is obtained by the key scan sequencer and when the next set of key data is obtained. 430 CHAPTER 21 KIU (KEYBOARD INTERFACE UNIT) 21.2.6 KIUINT (0x0B00 0198) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 KDATLOST R/W 0 0 D1 KDATRDY R/W 0 0 D0 SCANINT R/W 0 0 Bit D[15..3] D[2] Reserved Name Function Write 0 when writing. 0 is returned after a read. Key scan data lost interrupt. Cleared to 0 when 1 is written. 1 : Yes 0 : No Key data scan complete interrupt. Cleared to 0 when 1 is written. 1 : Yes 0 : No Key input detection interrupt. Cleared to 0 when 1 is written. 1 : Yes 0 : No KDATLOST D[1] KDATRDY D[0] SCANINT This register indicates the type of interrupt that has occurred in the KIU. 431 CHAPTER 21 KIU (KEYBOARD INTERFACE UNIT) 21.2.7 KIURST (0x0B00 019A) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 Reserved R 0 0 D0 KIURST W 0 0 Bit D[15..1] D[0] Reserved KIURST Name Function Write 0 when writing. 0 is returned after a read. KIU reset. Cleared to 0 when 1 is written. 1 : Reset 0 : Normal operation This register is used to forcibly reset the KIU. 432 CHAPTER 21 KIU (KEYBOARD INTERFACE UNIT) 21.2.8 KIUGPEN (0x0B00 019C) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 KGPEN[11] R/W 0 0 D10 KGPEN[10] R/W 0 0 D9 KGPEN[9] R/W 0 0 D8 KGPEN[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 KGPEN[7] R/W 0 0 D6 KGPEN[6] R/W 0 0 D5 KGPEN[5] R/W 0 0 D4 KGPEN[4] R/W 0 0 D3 KGPEN[3] R/W 0 0 D2 KGPEN[2] R/W 0 0 D1 KGPEN[1] R/W 0 0 D0 KGPEN[0] R/W 0 0 Bit D[15..12] D[11..0] Reserved Name Function Write 0 when writing. 0 is returned after a read. SCAN pin function 1 : Use as output port 0 : Use as SCAN pin KGPEN[11..0] This register is used to set whether or not the KSCAN pins will function as a general-purpose output port. Setting a "1" to each bit in this register enables the KSCAN pin to function as a general-purpose output port. The output port setting are made via the GIU's GIUPODATL register (0x0B00 011C). 433 CHAPTER 21 KIU (KEYBOARD INTERFACE UNIT) 21.2.9 SCANLINE (0x0B00 019E) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 LINE[1] R/W 0 0 D0 LINE[0] R/W 0 0 Bit D[15..2] D[1..0] Reserved LINE[1..0] Name Function Write 0 when writing. 0 is returned after a read. SCAN pin use/do not use setting 11 : Do not use SCAN pins for key scan The KIU's SCAN pins can be used as an output port. 10 : Use eight key scan pins (KSCAN[7..0]) Key scan uses eight key scan pins (supports 64 keys) The remaining four pins can be used as an output port. 01 : Use ten key scan pins (KSCAN[9..0]) Key scan uses ten key scan pins (supports 80 keys) The remaining two pins can be used as an output port. 00 : Use twelve key scan pins (KSCAN[11..0]) Key scan uses twelve key scan pins (supports 96 keys) No pins can be used as an output port. This register is used to switch the number of scan lines. 434 CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT) This chapter describes the DSIU's operations and register settings. 22.1 GENERAL The DSIU (debug serial interface unit) supports transfer rates up to 115.2 kbps. In addition to the DDIN and DDOUT input/output pins, the DSIU supports the DCTS# and DRTS# pins that are used for hardware flow control. 22.2 REGISTER SET The DSIU registers are listed below. Table 22-1. DSIU Registers Address 0x0B00 01A0 0x0B00 01A2 0x0B00 01A4 0x0B00 01A6 0x0B00 01A8 0x0B00 01AA 0x0B00 01AC 0x0B00 01AE 0x0B00 01B0 0x0B00 01B2 0x0B00 01B6 0x0B00 01B8 R/W R/W R R/W R/W R R R/W R/W R R/W R/W R/W Register Symbols PORTREG MODEMREG ASIM00REG ASIM01REG RXB0RREG RXB0LREG TXS0RREG TXS0LREG ASIS0REG INTR0REG BPRM0REG DSIURESETREG Port Change Register Modem Control Register Asynchronous Mode 0 Register Asynchronous Mode 1 Register Receive Buffer Register (Extended) Receive Buffer Register Transmit Data Register (Extended) Transmit Data Register Status Register Debug SIU Interrupt Register Baud rate Generator Prescaler Mode Register Debug SIU Reset Register Function These registers are described in detail below. 435 CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT) 22.2.1 PORTREG (0x0B00 01A0) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 CDDIN R/W 0 0 D2 CDDOUT R/W 0 0 D1 CDRTS R/W 0 0 D0 CDCTS R/W 0 0 Bit D[15:4] D[3] Reserved CDDIN Name Function Write 0 when writing. 0 is returned after a read. This pin is used to switch the DDIN pin for use as a general-purpose output pin. 1 : General-purpose output 0 : DDIN This pin is used to switch the DDOUT pin for use as a general-purpose output pin. 1 : General-purpose output 0 : DDOUT This pin is used to switch the DRTS# pin for use as a general-purpose output pin. 1 : General-purpose output 0 : DRTS# This pin is used to switch the DCTS# pin for use as a general-purpose output pin. 1 : General-purpose output 0 : DCTS# D[2] CDDOUT D[1] CDRTS D[0] CDCTS This register is used to switch the DSIU pin for use as a general-purpose output pin. Note that the output value should be set in the GIU when the DSIU pins are set to general-purpose outputs. 436 CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT) 22.2.2 MODEMREG (0x0B00 01A2) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 DRTS R 1 1 D0 DCTS R 1 1 Bit D[15:2] D[1] Reserved DRTS Name Function Write 0 when writing. 0 is returned after a read. DRTS# pin output 1: High level 0: Low level DCTS# pin input 1: High level 0: Low level D[0] DCTS This register is used for flow control and can be used to pass signals between the VR4102 and external agents. Note that the setting of RXE0 bit of ASIM00REG is reflected on the output from DRTS# pin. 437 CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT) 22.2.3 ASIM00REG (0x0B00 01A4) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 1 1 D6 RXE0 R/W 0 0 D5 PS0[1] R/W 0 0 D4 PS0[0] R/W 0 0 D3 CL0 R/W 0 0 D2 SL0 R/W 0 0 D1 Reserved R 0 0 D0 Reserved R 0 0 Bit D[15:8] D[7] D[6] Reserved Reserved RXE0 Name Function Write 0 when writing. 0 is returned after a read. Write 1 when writing. 1 is returned after a read. Debug serial reception enable 1 : Enable 0 : Prohibit Debug serial parity select 11 : Even parity 10 : Odd parity 01 : Zero parity bits during transmit No parity during receive 00 : No parity. Set to 00 for extended-bit operations Debug serial character length setting 1 : 8 bits 0 : 7 bits Debug serial stop bit setting 1 : 2 bits 0 : 1 bit Write 0 when writing. 0 is returned after a read. D[5:4] PS0[1:0] D[3] CL0 D[2] SL0 D[1:0] Reserved This register is used to make various serial communication settings for debugging. The setting of RXE0 bit is reflected on the output from DRTS# pin. 0 is output when this bit is set to 1 (reception enable), and 1 is output when this bit is set to 0 (reception prohibit). If this register is changed during transmission or reception of serial data for debugging, the DSIU's operations cannot be guaranteed. 438 CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT) 22.2.4 ASIM01REG (0x0B00 01A6) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 Reserved R 0 0 D0 EBS0 R/W 0 0 Bit D[15:1] D[0] Reserved EBS0 Name Function Write 0 when writing. 0 is returned after a read. Extended bit operation enable 1 : Enable 0 : Prohibit This register is used to set extended bit operations for the DSIU. When "1" is set to the EBS0 bit, one bit is added to the 8-bit data length for transmission and reception to enable operations using 9-bit data. Extended-bit operations are valid only when "00" has been set to ASIM00REG's PS0[1:0] bit. If a value other than "00" has been set to ASIM00REG's PS0[1:0] bit, the EBS0 bit specification is ignored and extended-bit operations cannot be performed. 439 CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT) 22.2.5 RXB0RREG (0x0B00 01A8) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 RXB0[8] R 0 0 Bit Name R/W RTCRST Other resets D7 RXB0[7] R 0 0 D6 RXB0[6] R 0 0 D5 RXB0[5] R 0 0 D4 RXB0[4] R 0 0 D3 RXB0[3] R 0 0 D2 RXB0[2] R 0 0 D1 RXB0[1] R 0 0 D0 RXB0[0] R 0 0 Bit D[15:9] D[8:0] Reserved RXB0[8:0] Name Function Write 0 when writing. 0 is returned after a read. Receive data [8:0] This register is used to store debug serial receive data. The RXB0[8] bit stores the extended bit during extended-bit operations and stores a zero during 7- or 8-bit character reception. The RXB0[7] bit stores a zero during 7-bit character reception. 440 CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT) 22.2.6 RXB0LREG (0x0B00 01AA) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 RXB0L[7] R 0 0 D6 RXB0L[6] R 0 0 D5 RXB0L[5] R 0 0 D4 RXB0L[4] R 0 0 D3 RXB0L[3] R 0 0 D2 RXB0L[2] R 0 0 D1 RXB0L[1] R 0 0 D0 RXB0L[0] R 0 0 Bit D[15:8] D[7:0] Reserved Name Function Write 0 when writing. 0 is returned after a read. Receive data [7:0] RXB0L[7:0] This register is used to store debug serial receive data. The RXB0L[7] bit stores a zero during 7-bit character reception. The only difference between this register and RXB0RREG is that this register does not support extended-bit operations. 441 CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT) 22.2.7 TXS0RREG (0x0B00 01AC) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 TXS0[8] R/W 1 1 Bit Name R/W RTCRST Other resets D7 TXS0[7] R/W 1 1 D6 TXS0[6] R/W 1 1 D5 TXS0[5] R/W 1 1 D4 TXS0[4] R/W 1 1 D3 TXS0[3] R/W 1 1 D2 TXS0[2] R/W 1 1 D1 TXS0[1] R/W 1 1 D0 TXS0[0] R/W 1 1 Bit D[15:9] D[8:0] Reserved TXS0[8:0] Name Function Write 0 when writing. 0 is returned after a read. Transmit data [8:0] This register is used to store debug serial transmit data. The TXS0[8] bit is used to transmit the extended bit during extended-bit operations. 442 CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT) 22.2.8 TXS0LREG (0x0B00 01AE) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 TXS0L[7] R/W 1 1 D6 TXS0L[6] R/W 1 1 D5 TXS0L[5] R/W 1 1 D4 TXS0L[4] R/W 1 1 D3 TXS0L[3] R/W 1 1 D2 TXS0L[2] R/W 1 1 D1 TXS0L[1] R/W 1 1 D0 TXS0L[0] R/W 1 1 Bit D[15:8] D[7:0] Reserved Name Function Write 0 when writing. 0 is returned after a read. Transmit data [7:0] TXS0L[7:0] This register is used to store debug serial transmit data. The only difference between this register and TXS0RREG is that this register does not support extended-bit operations. 443 CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT) 22.2.9 ASIS0REG (0x0B00 01B0) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 SOT0 R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 PE0 R 0 0 D1 FE0 R 0 0 D0 OVE0 R 0 0 Bit D[15:8] D[7] Reserved SOT0 Name Function Write 0 when writing. 0 is returned after a read. Transmit mode status 1 : Transmission start 0 : Transmission complete Write 0 when writing. 0 is returned after a read. Parity error status 1 : Parity error 0 : Normal Framing error status 1 : Framing error 0 : Normal Overrun error status 1 : Overrun error status 0 : Normal D[6:3] D[2] Reserved PE0 D[1] FE0 D[0] OVE0 This register indicates the debug serial transmit/receive status. A write to the TXS0RREG or TXS0LREG register sets "1" to the SOT0 bit. When the transmission is completed, "1" is set to the INTR0REG register's INTST0 bit and the SOT0 bit is cleared to zero. This bit can be used as a means of determining whether or not it is possible to write to the transmission shift register when transmitting data in debug serial mode. If the received data contains a parity error, "1" is set to the PE0 bit. If the stop bit is not detected, "1" is set to the FE0 bit. An overrun error occurs and "1" is set to the OVE0 bit if the sequencer completes the next receive processing before receive data is read from the receive buffer. When an overrun error occurs, the old data in the receive buffer is overwritten by the newly received data. 444 CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT) 22.2.10 INTR0REG (0x0B00 01B2) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 INTDCD R/W 0 0 D2 INTSER0 R/W 0 0 D1 INTSR0 R/W 0 0 D0 INTST0 R/W 0 0 Bit D[15:4] D[3] Reserved INTDCD Name Function Write 0 when writing. 0 is returned after a read. CTS# change interrupt. Cleared to 0 when 1 is written. 1 : CTS change interrupt 0 : Normal Debug serial receive error interrupt. Cleared to 0 when 1 is written. 1 : Error interrupt 0 : Normal Debug serial receive complete interrupt. Cleared to 0 when 1 is written. 1 : Receive complete 0 : Other Debug serial transmit complete interrupt. Cleared to 0 when 1 is written. 1 : Transmit complete 0 : Other D[2] INTSER0 D[1] INTSR0 D[0] INTST0 This register indicates interrupt events that occur during debug serial transmission. When debug serial operations are in the reception-enable mode, and either the PE0 bit, FE0 bit, or OVE0 bit in the ASIS0REG has been set, "1" is set to the INTSER0 bit. When debug serial operations are in the reception-enable mode, and receive data is transferred to the receive buffer, "1" is set to the INTSR0 bit. When one frame of transmit data is sent from the transmit register, "1" is set to the INTST0 bit. When the CTS# (flow control signal from an external agent) is changed, "1" is set to INTDCD bit. 445 CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT) 22.2.11 BPRM0REG (0x0B00 01B6) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 BRCE0 R/W 0 0 D6 Reserved R/W 0 0 D5 Reserved R/W 0 0 D4 Reserved R/W 0 0 D3 Reserved R/W 0 0 D2 BPR0[2] R/W 0 0 D1 BPR0[1] R/W 0 0 D0 BPR0[0] R/W 0 0 Bit D[15:8] D[7] Reserved BRCE0 Name Function Write 0 when writing. 0 is returned after a read. Baud rate generator count enable 1 : Enable 0 : Prohibit Write 0 when writing. 0 is returned after a read. Debug serial baud rate setting 111 : 115200 bps 110 : 57600 bps 101 : 38400 bps 100 : 19200 bps 011 : 9600 bps 010 : 4800 bps 001 : 2400 bps 000 : 1200 bps D[6:3] D[2:0] Reserved BPR0[2:0] This register is used to set the baud rate for debug serial communications. Debug serial operations are not guaranteed if the baud rate is changed during transmission or reception. 446 CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT) 22.2.12 DSIURESETREG (0x0B00 01B8) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 Reserved R 0 0 D0 DSIURST R/W 0 0 Bit D[15:1] D[0] Reserved DSIURST Name Function Write 0 when writing. 0 is returned after a read Debug serial reset. Cleared to 0 when 1 is written. 1 : Reset 0 : Normal This register is used to reset the debug serial mode. 447 CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT) 22.3 DESCRIPTION OF OPERATIONS 22.3.1 Data Format Serial data is transmitted and received in full-duplex mode. The format of the transmit and receive data is shown in the following figure. Each frame includes a start bit, character bits, parity bit, and stop bit(s). Specification of the character bit length in one data frame, along with the parity setting, and stop bit length specification are all made via the mode registers (ASIM00REG and ASIM01REG). Figure 22-1. Data Format for Transmission and Reception 1 data frame Character bits Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop z z z z Start bit Character bits (Dn) Parity bit Stop bit(s) : 1 bit : 7, 8, or 9 bits (when using extended bit) (n = 0 to 8) : Even parity, odd parity, zero parity, or no parity : 1 bit or 2 bits 448 CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT) 22.3.2 Transmission After the DCTS# pin value is confirmed as "1", writing data to a transmission shift register (TXS0REG or TXS0LREG) activates transmission via the DDOUT pin. Use the transmit complete interrupt (Dsiu_Intst0) service routine to write the next data to TXS0REG or TXS0LREG. Transmission enable status The DSIU unit is always set to transmission enable status. The DCTS# pin is used when it is necessary to confirm that the remote side is ready to receive. Activation of transmit operation Writing data to a transmission shift register (TXS0REG or TXS0LREG) activates the transmit operation. The transmit data is sent in LSB-first order, beginning with the start bit. The start bit, parity bit, and stop bit(s) are added automatically. Transmit complete interrupt request Once one frame of data has been sent, a transmit complete interrupt request (Dsiu_Intst0) occurs. If the next data to be transmitted is then not written to TXS0REG or TXS0LREG, the transmit operation is halted and the transmission rate is lowered. Cautions 1. Normally, the transmit complete interrupt request (Dsiu_Intst0) occurs when the TXS0REG or TXS0LREG register is empty. However, if a reset is input, the transmit complete interrupt request (Dsiu_Intst0) will not occur even when the transmission shift register (TXS0REG or TXS0LREG) is empty. 2. Writing to either TXS0REG or TXS0LREG is prohibited during a transmit operation until Dsiu_Intst0 occurs. 449 CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT) Figure 22-2. Transmit Complete Interrupt Timing (a) Stop bit length: 1 DDOUT Dsiu_Intst0 Start Stop D0 D1 D2 D3 D4 D5 D6 D7 Parity (b) Stop bit length: 2 DDOUT Dsiu_Intst0 Start Stop Stop D0 D1 D2 D3 D4 D5 D6 D7 Parity 450 CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT) 22.3.3 Reception Once reception enable has been set, sampling of the DDIN pin begins and, when a start bit is detected, data reception begins. A receive complete interrupt (Dsiu_Intst0) occurs each time reception of one frame of data is completed. Normally, this interrupt service is used to transfer receive data from a receive buffer (RXB0REG or RXB0LREG) to memory. Reception enable status Setting the ASIM00REG's bit[6] sets enable status for the receive operation, and a zero is output to DRTS#. RXE0 = 1: Reception enable status RXE0 = 0: Reception prohibit status DRTS# = 0 DRTS# = 1 The reception hardware is initialized and enters idle mode when reception prohibit status has been set. Once that happens, receive complete interrupts and receive error interrupts are not issued and the contents of the receive buffer are retained. Activation of receive operation The receive operation is activated when a start bit is detected. The DDIN pin is sampled at the interval set by the serial clock specified via the ASIM00REG. Once a signal's falling edge is detected at the DDIN pin, the DDIN pin is again sampled after an interval of eight serial clocks. This time, when a low-level state is detected it is recognized as a start bit and control is passed to the receive operation, after which the DDIN pin continues to be sampled using an interval of 16 serial clocks. After eight serial clocks have elapsed since a signal's falling edge was detected at the DDIN pin, when sampling recognizes a high-level state it does not recognize the signal's falling edge as a start bit. Instead, the serial clock counter used for the sampling timing is initialized and the receive operation is halted until the next edge input. Receive complete interrupt request When RXE0 = 1 and one frame of data has been received, the receive data in the shift register is transferred to RXB0REG and a receive complete interrupt request (Dsiu_Intsr0) is issued. Even when an error has occurred, the receive data for which the error occurred is still transferred to a receive buffer (RXB0REG or RXB0LREG) and two interrupts; a receive complete interrupt (Dsiu_Intsr0) and a receive error interrupt (Dsiu_Intser0), occur at the same time. If the RXE0 bit is reset (to "0") during a receive operation, the receive operation is halted immediately. At that point, the contents of the receive buffer (RXB0REG or RXB0LREG) and ASIS0REG are not changed and neither the receive complete interrupt (Dsiu_Intsr0) nor the receive error interrupt (Dsiu_Intser0) occur. Figure 22-3. Receive Complete Interrupt Timing DDIN Dsiu_Intsr0 Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop 451 CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT) Receive error flag Receive operations can be affected by three types of error flags that are set during the receive operations: a parity error flag, a framing error flag, and an overrun error flag. A receive error interrupt request is issued after these three types of error flags are ORed. During a receive error interrupt (Dsiu_Intser0), the contents of the ASIS0REG can be read to detect which kind of error occurred during reception. The contents of the ASIS0REG are reset (to "0") when the receive buffer (RXB0REG or RXB0LREG) is read or when the next data is received (another error flag is set if the next data also contains an error). Table 22-2. Receive Error Causes Receive error Parity error Framing error Overrun error Cause Parity specified during reception does not match parity of receive data Stop bit is not detected Reception of the next data is completed before data is read from the receive buffer Figure 22-4. Receive Error Timing DDIN Dsiu_Intsr0 Dsiu_Intser0 Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop 452 CHAPTER 23 LED (LED CONTROL UNIT) This chapter describes LED operations and register settings. 23.1 GENERAL An LED is switched on and off at a regular interval. The interval can be set as programmable. This unit can operate during Standby, Suspend, or Hibernate mode. 23.2 REGISTER SET The LED registers are listed below. Table 23-1. LED Registers Address 0x0B00 0240 0x0B00 0242 0x0B00 0248 0x0B00 024A 0x0B00 024C R/W R/W R/W R/W R/W R/W Register Symbols LEDHTSREG LEDLTSREG LEDCNTREG LEDASTCREG LEDINTREG Function LED H Time Set register LED L Time Set register LED Control register LED Auto Stop Time Count register LED Interrupt register These registers are described in detail below. 453 CHAPTER 23 LED (LED CONTROL UNIT) 23.2.1 LEDHTSREG (0x0B00 0240) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 HTS[4] R/W 1 Note D3 HTS[3] R/W 0 Note D2 HTS[2] R/W 0 Note D1 HTS[1] R/W 0 Note D0 HTS[0] R/W 0 Note Bit D[15..5] D[4..0] Reserved HTS[4..0] Name Function Write 0 when writing. 0 is returned after a read. LED ON time 00000 : Prohibit 00001 : 0.0625 seconds 00010 : 0.125 seconds : 00100 : 0.25 seconds : 01000 : 0.5 seconds : 10000 : 1 second : 11111 : 1.9375 seconds Note Previous value is retained This register is used to set the LED's ON time (high-level width of LEDOUT#). The ON time ranges from 0.0625 to 1.9375 seconds and can be set in 0.0625-second units. The initial value is 1 second. This register cannot be changed once the LEDENABLE bit of LEDCNTREG has been set as "enable". Operation is not guaranteed if a change is made after that point. 454 CHAPTER 23 LED (LED CONTROL UNIT) 23.2.2 LEDLTSREG (0x0B00 0242) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 LTS[6] R/W 0 Note D5 LTS[5] R/W 1 Note D4 LTS[4] R/W 0 Note D3 LTS[3] R/W 0 Note D2 LTS[2] R/W 0 Note D1 LTS[1] R/W 0 Note D0 LTS[0] R/W 0 Note Bit D[15..7] D[6..0] Reserved LTS[6..0] Name Function Write 0 when writing. 0 is returned after a read. LED OFF time 0000000 : Prohibit 0000001 : 0.0625 seconds 0000010 : 0.125 seconds : 0000100 : 0.25 seconds : 0001000 : 0.5 seconds : 0010000 : 1 second : 0100000 : 2 seconds : 1000000 : 4 seconds : 1111111 : 7.9375 seconds Note Previous value is retained This register is used to set the LED's OFF time (low-level width of LEDOUT#). The OFF time ranges from 0.0625 to 7.9375 seconds and can be set in 0.0625-second units. The initial value is 2 seconds. This register cannot be changed once the LEDENABLE bit of LEDCNTREG has been set as "enable". Operation is not guaranteed if a change is made after that point. 455 CHAPTER 23 LED (LED CONTROL UNIT) 23.2.3 LEDCNTREG (0x0B00 0248) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 LEDSTOP R/W 1 Note D0 LEDENABLE R/W 0 Note Bit D[15..2] D[1] Reserved LEDSTOP Name Function Write 0 when writing. 0 is returned after a read. LED ON/OFF auto stop setting 1 : ON 0 : OFF LED ON/OFF (blink) setting 1 : Blink 0 : Do not blink D[0] LEDENABLE Note Previous value is retained This register is used to make various LED settings. Caution When setting up LED activation, make sure that a value other than zero has already been set to the LEDHTSREG, LEDLTSREG, and LEDASTCREG. The operation is not guaranteed if zero is set to these registers. 456 CHAPTER 23 LED (LED CONTROL UNIT) 23.2.4 LEDASTCREG (0x0B00 024A) Bit Name R/W RTCRST Other resets D15 ASTC[15] R/W 0 0 D14 ASTC[14] R/W 0 0 D13 ASTC[13] R/W 0 0 D12 ASTC[12] R/W 0 0 D11 ASTC[11] R/W 0 0 D10 ASTC[10] R/W 1 1 D9 ASTC[9] R/W 0 0 D8 ASTC[8] R/W 0 0 Bit Name R/W RTCRST Other resets D7 ASTC[7] R/W 1 1 D6 ASTC[6] R/W 0 0 D5 ASTC[5] R/W 1 1 D4 ASTC[4] R/W 1 1 D3 ASTC[3] R/W 0 0 D2 ASTC[2] R/W 0 0 D1 ASTC[1] R/W 0 0 D0 ASTC[0] R/W 0 0 Bit D[15..0] Name ASTC[15..0] LED auto stop time count bit Function This register is a 16-bit down counter that sets the number of ON/OFF times prior to automatic stopping of LED activation. The set value is read during a read. The pair of operations in which the LED is switched ON once and OFF once is counted as "1" by this counter. The counter counts down from the set value and an LEDINT interrupt occurs when it reaches zero. The initial setting is 1,200 times (ON/OFF pairs) in which each time includes one second of ON time and two seconds of OFF time. Caution Setting a zero to this register is prohibited. The operation is not guaranteed if zero is set to this register. 457 CHAPTER 23 LED (LED CONTROL UNIT) 23.2.5 LEDINTREG (0x0B00 024C) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 Reserved R 0 0 D0 LEDINT R/W 0 0 Bit D[15..1] D[0] Reserved LEDINT Name Function Write 0 when writing. 0 is returned after a read. Auto stop interrupt. Cleared to 0 when 1 is written. 1 : Yes 0 : No This register indicates when an auto stop interrupt has occurred. An auto stop interrupt occurs if "1" has already been set to bit 1 and bit 0 of the LEDCNTREG when the LEDASTCREG is cleared to "0". When this interrupt occurs, bit 1 and bit 0 of the LEDCNTREG are both cleared to "0". 458 CHAPTER 23 LED (LED CONTROL UNIT) 23.3 OPERATION FLOW LEDs blink (Auto Stop) Set LEDHTSREG LED blinking time setting x LEDHTSREG Sets LED lighting time. x LEDLTSREG Sets LED off time. x LEDASTCREG Sets number of LEDs blinking. Caution Setting these registers to 0 is prohibited because it may cause undefined operation. LED auto-stop setting x LEDSTOP Sets the LED blink auto-stop function to enable. This setting terminates LED blinking automatically after blinking time set above has elapsed. LED blinking start x LEDENABLE Starts LED blinking. Set LEDLTSREG Set LEDASTCREG LEDs blinking start condition LEDCNTREG LEDSTOP = 1 LEDCNTREG LEDENABLE = 1 LEDs blink LED blinking x Supervising the auto-stop counter LED blinking terminates when the auto-stop counter reaches 0. Caution Setting the LEDENABLE or LEDSTOP bit to 0 during blinking is prohibited because it may cause undefined operation. LED blinking termination x LEDENABLE = 0 Terminates LED blinking. No Auto Stop Counter = 0? Yes LEDENABLE = 0 LEDSTOP = 0 LEDINT = 1 LED blinking terminate interrupt generation x LEDINT = 1 Generates an interrupt request to the ICU. LEDs off 459 [MEMO] 460 CHAPTER 24 SIU (SERIAL INTERFACE UNIT) This chapter describes the SIU's operations and register settings. 24.1 GENERAL The SIU is a serial interface that conforms to the RS-232-C communication standard and is equipped with two one-channel interfaces, one for transmission and one for reception. This unit is functionally compatible with the NS16550. 24.2 REGISTER SET The SIU registers are listed below. Table 24-1. SIU Registers Address 0x0C00 0000 LCR[7] 0 R/W R W 1 0x0C00 0001 0 1 0x0C00 0002 R/W R/W R/W R W 0x0C00 0003 0x0C00 0004 0x0C00 0005 0x0C00 0006 0x0C00 0007 0x0C00 0008 R/W R/W R/W R/W R/W R/W Register Symbols SIURB SIUTH SIUDLL SIUIE SIUDLM SIUIID SIUFC SIULC SIUMC SIULS SIUMS SIUSC SIUIRSEL Function Receiver Buffer Register (Read) Transmitter Holding Register (Write) Divisor Latch (Least Significant Byte) Interrupt Enable Divisor Latch (Most Significant Byte) Interrupt Identification Register (Read) FIFO Control Register (Write) Line Control Register MODEM Control Register Line Status Register MODEM Status Register Scratch Register SIU/FIR IrDA Selector Remark LCR[7] is the bit 7 of SIULC register. 461 CHAPTER 24 SIU (SERIAL INTERFACE UNIT) 24.2.1 SIURB (0x0C00 0000: LCR[7] = 0, Read) Bit Name R/W RTCRST Other resets D7 RXD[7] R 0 0 D6 RXD[6] R 0 0 D5 RXD[5] R 0 0 D4 RXD[4] R 0 0 D3 RXD[3] R 0 0 D2 RXD[2] R 0 0 D1 RXD[1] R 0 0 D0 RXD[0] R 0 0 Bit D[7..0] RXD[7..0] Name Serial receive data Function This register stores receive data used in serial communications. To access this register, set LCR[7] (bit 7 of SIULC register) to 0. 24.2.2 SIUTH (0x0C00 0000: LCR[7] = 0, Write) Bit Name R/W RTCRST Other resets D7 TXD[7] W 0 0 D6 TXD[6] W 0 0 D5 TXD[5] W 0 0 D4 TXD[4] W 0 0 D3 TXD[3] W 0 0 D2 TXD[2] W 0 0 D1 TXD[1] W 0 0 D0 TXD[0] W 0 0 Bit D[7..0] TXD[7..0] Name Serial transmit data Function This register stores transmit data used in serial communications. To access this register, set LCR[7] (bit 7 of SIULC register) to 0. 462 CHAPTER 24 SIU (SERIAL INTERFACE UNIT) 24.2.3 SIUDLL (0x0C00 0000: LCR[7] = 1) Bit Name R/W RTCRST Other resets D7 DLL[7] R/W 0 0 D6 DLL[6] R/W 0 0 D5 DLL[5] R/W 0 0 D4 DLL[4] R/W 0 0 D3 DLL[3] R/W 0 0 D2 DLL[2] R/W 0 0 D1 DLL[1] R/W 0 0 D0 DLL[0] R/W 0 0 Bit D[7..0] DLL[7..0] Name Function Baud rate generator divisor (low-order byte) This register is used to set the divisor (division rate) for the baud rate generator. The data in this register and the data in SIUDLM register on the high-order side are together handled as 16-bit data. To access this register, set LCR[7] (bit 7 of SIULC register) to 1. 463 CHAPTER 24 SIU (SERIAL INTERFACE UNIT) 24.2.4 SIUIE (0x0C00 0001: LCR[7] = 0) Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 IE[3] R/W 0 0 D2 IE[2] R/W 0 0 D1 IE[1] R/W 0 0 D0 IE[0] R/W 0 0 Bit D[7..4] D[3] Reserved IE[3] Name Function Write 0 when writing. 0 is returned after read. Modem status interrupt 1 : Interrupt enable 0 : Interrupt prohibit Receive status interrupt 1 : Interrupt enable 0 : Interrupt prohibit Transmitter holding register empty interrupt 1 : Interrupt enable 0 : Interrupt prohibit Receive data interrupt or timeout interrupt in FIFO mode 1 : Interrupt enable 0 : Interrupt prohibit D[2] IE[2] D[1] IE[1] D[0] IE[0] This register is used to specify interrupt enable/prohibit settings for the five types of interrupt used by the SIU. These interrupts can be used to make the corresponding interrupt output signal (INTR) active. Overall use of interrupt functions can be halted by setting bit 0 to bit 3 of the interrupt enable register (IER) to zero. If one or more of the bits from bit 0 to bit 3 has a value of 1, the corresponding interrupt is enabled. When interrupts are prohibited, "pending" is not displayed in the IIR[0] bit even when the interrupt condition has been met and INTR output does not become active. Other functions in the system are not affected even though interrupts are prohibited and the settings in the line status register and modem status register are valid. To access this register, set LCR[7] (bit 7 of SIULC register) to 0. 464 CHAPTER 24 SIU (SERIAL INTERFACE UNIT) 24.2.5 SIUDLM (0x0C00 0001: LCR[7] = 1) Bit Name R/W RTCRST Other resets D7 DLM[7] R/W 0 0 D6 DLM[6] R/W 0 0 D5 DLM[5] R/W 0 0 D4 DLM[4] R/W 0 0 D3 DLM[3] R/W 0 0 D2 DLM[2] R/W 0 0 D1 DLM[1] R/W 0 0 D0 DLM[0] R/W 0 0 Bit D[7..0] DLM[7..0] Name Function Baud rate generator divisor (high-order byte) This register is used to set the divisor (division rate) for the baud rate generator. The data in this register and the data in SIUDLL register on the low-order side are together handled as 16-bit data. To access this register, set LCR[7] (bit 7 of SIULC register) to 1. 465 CHAPTER 24 SIU (SERIAL INTERFACE UNIT) Table 24-2. Correspondence between Baud Rates and Divisors Baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 128000 144000 192000 230400 288000 384000 576000 1152000 Divisor 23040 15360 10473 8565 7680 3840 1920 920 640 573 480 320 240 160 120 60 30 21 9 8 6 5 4 3 2 1 466 CHAPTER 24 SIU (SERIAL INTERFACE UNIT) 24.2.6 SIUIID (0x0C00 0002: Read) Bit Name R/W RTCRST Other resets D7 IIR[7] R 0 0 D6 IIR[6] R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 IIR[3] R 0 0 D2 IIR[2] R 0 0 D1 IIR[1] R 0 0 D0 IIR[0] R 1 1 Bit D[7..6] D[5..4] D[3] IIR[7..6] Reserved IIR[3] Name Becomes 11 when FCR0 = 1 Function Write 0 when writing. 0 is returned after read. Pending character timeout interrupt (in FIFO mode) 1 : Pending interrupt 0 : No pending interrupt Indicates the priority level of pending interrupt. See the following table. Pending interrupts 1 : No pending interrupt 0 : Pending interrupt D[2..1] IIR[2..1] D[0] IIR[0] This register indicates priority levels for interrupts and existence of pending interrupt. From highest to lowest priority, these interrupts are receive line status, receive data ready, character timeout, transmit holding register empty, and modem status. The contents of IIR[3] bit is valid only in FIFO mode, and it is always 0 in 16550 mode. IIR[2] bit becomes 1 when IIR[3] bit is set to 1. 467 CHAPTER 24 SIU (SERIAL INTERFACE UNIT) Table 24-3. Interrupt Function SIUIID register Bit3 0 Note Interrupt set/reset function Bit1 1 Priority level Interrupt type Interrupt source Overrun error, parity error, framing error, or break interrupt Receive data exists or has reached the trigger level. Interrupt reset control Read line status register Bit2 1 Highest (1st) Receive line status 2nd Receive data ready 0 1 0 Read the receive buffer register or lower trigger level via FIFO. 1 1 0 2nd Character timeout During the time period for the four most Read receive buffer recent characters, not one character has register been read from the receive FIFO nor has a character been input to the receive FIFO. During this period, at least one character has been held in the receive FIFO. Transmit register is empty Read IIR (if it is the interrupt source) or write to transmit holding register Read modem status register 0 0 1 3rd Transmit holding register empty 0 0 0 4th Modem status CTS#, DSR#, or DCD# Note FIFO mode only 468 CHAPTER 24 SIU (SERIAL INTERFACE UNIT) 24.2.7 SIUFC (0x0C00 0002: Write) Bit Name R/W RTCRST Other resets D7 FCR[7] W 0 0 D6 FCR[6] W 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 FCR[3] W 0 0 D2 FCR[2] W 0 0 D1 FCR[1] W 0 0 D0 FCR[0] W 0 0 Bit D[7..6] FCR[7..6] Name Receive FIFO trigger level 11 : 14 Bytes 10 : 08 Bytes 01 : 04 Bytes 00 : 00 Byte Function D[5..4] D[3] Reserved FCR[3] Write 0 when writing. 0 is returned after read. Switch between 16550 mode and FIFO mode 1 : From 16550 mode to FIFO mode 0 : From FIFO mode to 16550 mode Transmit FIFO clear/counter clear. Cleared to 0 when 1 is written. 1 : FIFO clear/counter clear 0 : Normal Receive FIFO clear/counter clear. Cleared to 0 when 1 is written. 1 : FIFO clear/counter clear 0 : Normal Receive/Transmit FIFO enable 1 : Enable 0 : Disable D[2] FCR[2] D[1] FCR[1] D[0] FCR[0] This register is used to control the FIFOs. 469 CHAPTER 24 SIU (SERIAL INTERFACE UNIT) z FIFO interrupt modes When receive FIFO is enabled and receive interrupts are enabled, receive interrupts can occur as described below. 1. When the FIFO is reached to the specified trigger level, a receive data ready interrupt occurs to inform the CPU. This interrupt is cleared when the FIFO goes below the trigger level. 2. When the FIFO is reached to the specified trigger level, the SIUIID register indicates a receive data ready interrupt. As with the interrupt above, this interrupt is cleared when the FIFO goes below the trigger level. 3. 4. Receive line status interrupts are assigned a higher priority level than are receive data ready interrupts. When characters are transferred from the shift register to the receive FIFO, "1" is set to the LSR0 bit. The value of this bit returns to "0" when the FIFO becomes empty. When receive FIFO is use-enabled and receive interrupts are enabled, receive FIFO timeout interrupts can occur as described below. 1. The following are conditions under which FIFO timeout interrupts occur. * At least one character is being stored in the FIFO. * The time required for sending four characters has elapsed since the serial reception of the last character (includes the time for two stop bits in cases where a stop bit has been specified). * The time required for sending four characters has elapsed since the CPU last accessed the FIFO. The time between receiving the last character and issuing a timeout interrupt is a maximum of 160 ms when operating at 300 baud and receiving 12-bit data. 2. The transfer time for a character is calculated based on the baud rate clock for reception (internal) input as clock signals (which is why the elapsed time is in proportion to the baud rate). 3. Once a timeout interrupt has occurred, the timeout interrupt is cleared and the timer is reset as soon as the CPU reads one character from the receive FIFO. 4. If no timeout interrupt has occurred, the timer is reset when a new character is received or when the CPU reads the receive FIFO. 470 CHAPTER 24 SIU (SERIAL INTERFACE UNIT) When transmit FIFO is use-enabled and transmit interrupts are enabled, transmit interrupts can occur as described below. 1. When the transmit FIFO becomes empty, a transmit holding register empty interrupt occurs. This interrupt is cleared when a character is written to the transmit holding register (from one to 16 characters can be written to the transmit FIFO during servicing of this interrupt), or when the SIUIID (interrupt ID register) is read. 2. If there are not at least two bytes of character data in the transmit FIFO between one time when LSR[5] = 1 (transmit FIFO is empty) and the next time when LSR[5] = 1, empty transmit FIFO status is reported to the IIR after a delay period calculated as "the time for one character the time for the last stop bit(s)." When transmit interrupts are enabled, the first transmit interrupt that occurs after the FCR0 (FIFO enable bit) is overwritten is indicated immediately. The priority level of the character timeout interrupt and receive FIFO trigger level interrupt is the same as that of the receive data ready interrupt. The priority level of the transmit FIFO empty interrupt is the same as that of the transmit holding register empty interrupt. z FIFO polling mode When FCR0 = 1 (FIFO is enabled), if the value of any or all of the interrupt enable register (SIUIE) bits 3 to 0 becomes "0", the SIU enters FIFO polling mode. Because the transmit block and receive block are controlled separately, polling mode can be set for either or both blocks. When in this mode, the status of the transmit block and/or receive block can be checked by reading the line status register (SIULS) via a user program. When in FIFO polling mode, there is no notification when the trigger level is reached or when a timeout occurs, but the receive FIFO and transmit FIFO can still store characters as they normally do. 471 CHAPTER 24 SIU (SERIAL INTERFACE UNIT) 24.2.8 SIULC (0x0C00 0003) Bit Name R/W RTCRST Other resets D7 LCR[7] R/W 0 0 D6 LCR[6] R/W 0 0 D5 LCR[5] R/W 0 0 D4 LCR[4] R/W 0 0 D3 LCR[3] R/W 0 0 D2 LCR[2] R/W 0 0 D1 LCR[1] R/W 0 0 D0 LCR[0] R/W 0 0 Bit D[7] LCR[7] Name Function Divisor latch access bit specification 1 : Divisor latch access 0 : Receive buffer, transmit holding register, interrupt enable register Break control 1 : Set break 0 : Clear break Parity fixing 1 : Fixed parity 0 : Parity not fixed Parity setting 1 : Set one bit as odd bit 0 : Set one bit as even bit Parity enable 1 : Create parity (during transmission) or check parity (during reception) 0 : No parity (during transmission) or no checking (during reception) Stop bit specification 1 : 1.5 bits (character length is 5 bits) 2 bits (character length is 6, 7, or 8 bits) 0 : 1 bit Specifies the length of one character (number of bits) 11 : 8 Bits 10 : 7 Bits 01 : 6 Bits 00 : 5 Bits D[6] LCR[6] D[5] LCR[5] D[4] LCR[4] D[3] LCR[3] D[2] LCR[2] D[1..0] LCR[1..0] This register is used to specify the format for asynchronous data communication and exchange and to set the divisor latch access bit. The setting of bit 5 becomes valid according to settings in bits 4 and 3. Bit 6 is used to send the break status to the receive side's UART. When Bit6 = 1, the serial output (TxD) is forcibly set to the spacing (0) state. 472 CHAPTER 24 SIU (SERIAL INTERFACE UNIT) 24.2.9 SIUMC (0x0C00 0004) Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 MCR[4] R/W 0 0 D3 MCR[3] R/W 0 0 D2 MCR[2] R/W 0 0 D1 MCR[1] R/W 0 0 D0 MCR[0] R/W 0 0 Bit D[7..5] D[4] Reserved MCR[4] Name Function Write 0 when writing. 0 is returned after read. For diagnostic testing (local loopback) 1 : Enable use of local loopback 0 : Disable use of local loopback OUT2 signal (internal) specification 1 : Output the low-level signal 0 : Output the high-level signal OUT1 signal (internal) specification 1 : Output the low-level signal 0 : Output the high-level signal RTS# output control 1 : Output the low-level signal 0 : Output the high-level signal DTR# output control 1 : Output the low-level signal 0 : Output the high-level signal D[3] MCR[3] D[2] MCR[2] D[1] MCR[1] D[0] MCR[0] This register is used for interface control with a modem or data set (or a peripheral device that emulates a modem). The settings of bit 3 and bit 2 become valid only when bit 4 is set to 1 (enable use of local loopback). z Local Loopback The local loopback can be used to test the transmit/receive data path in the SIU. The following operation is executed when bit 4 value = 1. The transmit block's serial output (TxD) enters the marking state (logical 1) and the serial input (RxD) to the receive block is cut off. The transmit shift register's output is looped back to the receive shift register's input. The four modem control inputs (DSR#, CTS#, RI (internal), and DCD#) are cut off and the four modem control outputs (DTR#, RTS#, OUT1 (internal), and OUT2 (internal)) are internally connected to the corresponding modem control inputs. The modem control output pins are forcibly set as inactive (high level). During this kind of loopback mode, transmitted data can be immediately and directly received. This function can be used to check on the transmit/receive data bus within the SIU. When in loopback mode, both transmission and receive interrupts can be used. The interrupt sources are external sources in relation to the transmit and receive blocks. Although modem control interrupts can be used, the low-order four bits of the modem control register can be used instead of the four modem control inputs as interrupt sources. As usual, each interrupt is controlled by an interrupt enable register. 473 CHAPTER 24 SIU (SERIAL INTERFACE UNIT) 24.2.10 SIULS (0x0C00 0005) Bit Name R/W RTCRST Other resets D7 LSR[7] R/W 0 0 D6 LSR[6] R/W 1 1 D5 LSR[5] R/W 1 1 D4 LSR[4] R/W 0 0 D3 LSR[3] R/W 0 0 D2 LSR[2] R/W 0 0 D1 LSR[1] R/W 0 0 D0 LSR[0] R/W 0 0 Bit D[7] LSR[7] Name Function Indicates error detection (in FIFO mode) 1 : Parity error, framing error, or break is detected 0 : Normal Transmit block empty 1 : No data in transmit holding register or transmit shift register No data in transmit FIFO (during FIFO mode) 0 : Data exists in transmit holding register or transmit shift register Data exists in transmit FIFO (during FIFO mode) Transmit holding register empty 1 : Character is transferred to transmit shift register (during 16550 mode) Transmit FIFO is empty (during FIFO mode) 0 : Character is stored in transmit holding register (during 16550 mode) Transmit data exists in transmit FIFO (during FIFO mode) Break interrupt 1 : Break interrupt detected 0 : Normal Framing error 1 : Framing error detected 0 : Normal Parity error 1 : Parity error detected 0 : Normal Overrun error 1 : Overwrite receive data 0 : Normal Receive data ready 1 : Receive data exists in FIFO 0 : No receive data in FIFO D[6] LSR[6] D[5] LSR[5] D[4] LSR[4] D[3] LSR[3] D[2] LSR[2] D[1] LSR[1] D[0] LSR[0] The CPU uses this register to get information related to data transfers. LSR[7] bit is valid only in FIFO mode, and it indicates always 0 in 16550 mode. 474 CHAPTER 24 SIU (SERIAL INTERFACE UNIT) Bit4: Break interrupt The value of bit 4 becomes 1 when the spacing mode (logical 0) is held longer than the time required for transmission of one word of receive data input (start bit + data bits + parity bit + stop bit). This bit value returns "0" when the CPU reads the contents of the line status register. When in FIFO mode, if a break interrupt is detected for one character in the FIFO, the character is regarded as an error character and the CPU is notified of a break interrupt when that character reaches the highest position in the FIFO. When a break occurs, one "zero" character is sent to the FIFO. The RxD enters marking mode, and when the next valid start bit is received, the next character can be transmitted. Bit3: Framing error This indicates that the received character data did not include a correct stop bit. The value of this becomes 1 when a zero (spacing level) stop bit is detected following the final data bit or parity bit. This bit value returns to 0 when the CPU reads the contents of the line status register. When in FIFO mode, if a framing error is detected for one character in the FIFO, the character is regarded as an error character and the CPU is notified of a framing error when that character reaches the highest position in the FIFO. When a framing error occurs, the SIU prepares for further synchronization. The next start bit is assumed to be the cause of the framing error and further data is not accepted until the next start bit has been sampled twice. Bit2: Parity error This error indicates that the received character data does not satisfy the even-parity or odd-parity setting specified by the even parity select bit. The value of this becomes 1 when a parity error is detected. This bit value returns to 0 when the CPU reads the contents of the line status register. When in FIFO mode, if a parity error is detected for one character within the FIFO, the character is regarded as an error character and the CPU is notified of a parity error when that character reaches the highest position in the FIFO. Bit1: Overrun error (OE) When the CPU transfers the next character to the receive buffer register before it reads the receive buffer register, the characters existing in that register are deleted. The value of this bit becomes 1 when overrun status is detected and returns to "0" when the CPU reads the contents of the line status register. When in FIFO mode, if the data exceeds the trigger level as it continues to be transferred to the FIFO, even after the FIFO becomes full an overrun error will not occur until all characters are stored in the shift register. The CPU is notified as soon as an overrun error occurs. overwritten and are not transferred to the FIFO. The characters in the shift register are 475 CHAPTER 24 SIU (SERIAL INTERFACE UNIT) 24.2.11 SIUMS (0x0C00 0006) Bit Name R/W RTCRST Other resets D7 MSR[7] R Undefined Undefined D6 MSR[6] R Undefined Undefined D5 MSR[5] R Undefined Undefined D4 MSR[4] R Undefined Undefined D3 MSR[3] R/W 0 0 D2 MSR[2] R/W 0 0 D1 MSR[1] R/W 0 0 D0 MSR[0] R/W 0 0 Bit D[7] MSR[7] Name Complement of DCD# signal 1 : High level 0 : Low level Complement of RI signal (internal) 1 : High level 0 : Low level Complement of DSR# input 1 : High level 0 : Low level Complement of CTS# input 1 : High level 0 : Low level DCD# signal change 1 : Change in DCD# signal 0 : No change RI signal (internal) change 1 : Change in RI signal (internal) 0 : No change DSR# signal change 1 : Change in DSR# signal 0 : No change CTS# signal change 1 : Change in CTS# signal 0 : No change Function D[6] MSR[6] D[5] MSR[5] D[4] MSR[4] D[3] MSR[3] D[2] MSR[2] D[1] MSR[1] D[0] MSR[0] This register indicates the current status of various control signals that are input to the CPU from a modem or other peripheral device. MSR[3..0] bits are cleared to 0 when they are read. 476 CHAPTER 24 SIU (SERIAL INTERFACE UNIT) 24.2.12 SIUSC (0x0C00 0007) Bit Name R/W RTCRST Other resets D7 SCR[7] R/W 0 0 D6 SCR[6] R/W 0 0 D5 SCR[5] R/W 0 0 D4 SCR[4] R/W 0 0 D3 SCR[3] R/W 0 0 D2 SCR[2] R/W 0 0 D1 SCR[1] R/W 0 0 D0 SCR[0] R/W 0 0 Bit D[7..0] SCR[7..0] Name Can be freely applied by user Function This register is a readable/writable 8-bit register. It does not affect control of the SIU. 477 CHAPTER 24 SIU (SERIAL INTERFACE UNIT) 24.2.13 SIUIRSEL (0x0C00 0008) Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 TMICMODE R/W 0 0 D4 TMICTX R/W 0 0 D3 IRMSEL[1] R/W 0 0 D2 IRMSEL[0] R/W 0 0 D1 IRUSESEL R/W 0 0 D0 SIRSEL R/W 0 0 Bit D[7..6] D[5] D[4] Reserved Name Function Write 0 when writing. 0 is returned after read. Specifies the mode of the emitter or receptor module. Specifies the communication rate. 1 : Communication at 4 Mbps 0 : Communication at 1.15 Mbps or less Sets the type of emitter/receptor module to be used 11 : RFU 10 : HP model (HSDL-1100 is assumed) 01 : TEMIC model (TFDS6000 is assumed) 00 : SHARP model (RY5FD01D is assumed) Selects SIU or FIR for use with IrDA emitter/receptor module 1 : FIR uses IrDA module 0 : SIU uses IrDA module Selects whether the SIU uses the IrDA module or the RS-232-C pins during communications 1 : Use IrDA module 0 : Use RS-232-C interface TMICMODE TMICTX D[3..2] IRMSEL[1..0] D[1] IRUSESEL D[0] SIRSEL This register is used to set the IrDA module settings, IrDA module access privileges, and the SIU's communication format (IrDA or serial). The settings of TMICMODE and TMICTX bits are valid only when IRMSEL[1..0] bits are set to 01 (TEMIC model). 478 CHAPTER 24 SIU (SERIAL INTERFACE UNIT) The figure below shows the connection examples between the VR4102 and IrDA modules. Figure 24-1. Connection Example between the VR4102 and IrDA Module (a) HP product VR4102 IRDIN IrDA module RxDA VR4102 (b) TEMIC product IrDA module RxD IRDIN IRDOUT TxD IRDOUT TxD FIRDIN#/SEL RXDB FIRDIN#/SEL SEL (c) SHARP product VR4102 IRDIN IrDA module RxD IRDOUT TxD FIRDIN#/SEL NC Remark NC: No Connection 479 [MEMO] 480 CHAPTER 25 HSP (MODEM INTERFACE UNIT) This chapter describes the HSP unit's operations and register settings. 25.1 GENERAL The core of the HSP unit uses PCtel's PCT288I chip. The main functions of the PCT288I is as follows. <1> CODEC device control and serial l parallel conversion of the CODEC transmit/receive data <2> Control of relay lines, hook lines, and other signal lines in DAA (Data Access Arrangement) block Block diagrams of HSP unit and an example of connection between the VR4102 and external agents are shown below. 481 CHAPTER 25 HSP (MODEM INTERFACE UNIT) Figure 25-1. HSP Unit Block Diagram testhsp i_tclk cshspb iadd[4:0] hsp_address decoder decode[4:0] iaddr288_before[4:0] hspinitreg hspinitreg ireset_before iafesel_before0 ibyte_before ihspout_before[15:0] OPD# bsc rst_gab iiowb iiorb idin[15:0] ihspout[15:0] Decoder To level Interrupt hsp_intr seclk_hsp IMCLK IRESET IAEN IIOWCB IIORCB OIOCS16B OIOCHRDYB IADDR[11:0] IBD[15:0] OBD[15:0] OE OIRQ2 OIRQ3 OIRQ4 OIRQ5 OIRQ10 OIRQ11 OIRQ12 OIRQ15 OCRYSTL ICRYSTAL IAFESEL[1] IAFESEL[0] IBYTE ICASIN ISLAVEB IHWPDNB ISA BUS INTERFACE PARALLEL I/O INTERFACE IRING ILC-SENSE ILV-SENSE IN[4:0] OPD OOFF-HOOK OCID-RELAY OAFERSTB OMUTE OUT[2] OUT[1] OUT[0] OOFF-HOOKB ISCLK IFSI ISDI IFSX OFSX OSDO OCLK0 OCLK1 IRING ILCSENSE OFFHOOK AFERST# MUTE HC0 TELECON HSPSCLK FS SDI INTERRUPT CODEC SERIAL I/O SDO HSPMCLK CONTROL BLOCK OCASOUT D CK Q Q_B Figure 25-2. Circuit Configuration Block Diagram Examples IRING ILCSENSE OFFHOOK TELCON DAA VR4102 (HSP) SDO HSPMCLK AFERST# HC0 FS SDI HSPSCLK TXAN TXAP RXA CODEC Line 3 4 MUTE Speaker 482 CHAPTER 25 HSP (MODEM INTERFACE UNIT) 25.2 REGISTER SET The HSP registers are listed below. The data registers can be accessed as the control registers by specifying the INDEX number and then reading from or writing to. All registers other than the HSPINIT register are original to the PCT288I. Table 25-1. HSP Registers Address 0x0C00 0020 0x0C00 0022 0x0C00 0023 0x0C00 0024 0x0C00 0028 0x0C00 0029 0x0C00 0029 R/W R/W R/W R/W W R R W Register Symbols HSPINIT HSPDATA[7:0] HSPDATA[15:8] HSPINDEX HSPID[7:0] HSPPCS[7:0] HSPPCTEL[7:0] Name HSP Initialize Register HSP Data Register [7:0] HSP Data Register [15:8] HSP Index Register HSP ID Register HSP I/O Address Program Confirmation Register HSP Signature Checking Port 483 CHAPTER 25 HSP (MODEM INTERFACE UNIT) 25.2.1 HSP Initialize Register (1) HSPINIT (0x0C00 0020) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 OPD R/W 0 0 D3 AFESEL R/W 0 0 D2 BYTE R/W 0 0 D1 BSC R/W 0 0 D0 HSPRST R/W 0 0 Bit D[15:5] D[4] Reserved OPD Name Function Write 0 when writing. 0 is returned after read. Power-down CODEC (indicates OPD# pin's state) 1 : High level 0 : Low level CODEC interface mode switch 1 : ST7546, STLC7546(SGS), T7525(AT) 0 : TLC320C44, TLC320AC01/02(TI) HSP data bus width setting 1 : 8 bits 0 : 16 bits CODEC interface control 1 : Normal 0 : Initial value HSP unit reset (same as hardware reset) 1 : Reset 0 : Do not reset D[3] AFESEL D[2] BYTE D[1] BSC D[0] HSPRST This register is used to control the HSP. BSC bit is used to control the CODEC interface. This bit must be set to 1 when using the HSP. The hardware reset and the reset by the HSPRST bit result the same function. 484 CHAPTER 25 HSP (MODEM INTERFACE UNIT) 25.2.2 HSP Data Register, HSP Index Register HSPDATA[15..0] is a 16-bit data port. HSPINDEX[15..0] setting. HSPINDEX[15..0] is a write-only index register. The role of the data register changes according to the values set to this register. The correspondence between INDEX numbers and registers is shown below. Table 25-2. Control Register Definitions INDEX Higher Byte 0 1 2 3 4 5 to 15 16 to 255 HSPTxData[15..8] HSPCNTL[9..8] Reserved HSPTOC[3..0] Reserved WRITE Lower Byte HSPTxData[7..0] HSPCNTL[7..0] HSPEXTOUT[7..0] HSPMCLK1[4..0] HSPFFSZ[6..0] Reserved Setting prohibited Higher Byte HSPRxData[15..8] HSPSTS[15..8] HSPID[7..0] READ Lower Byte HSPRxData[7..0] HSPSTS[7..0] HSPEXTIN[7..0] This register can be accessed as control registers according to the HSPERRCNT[11..8] HSPERRCNT[7..0] Reserved Reserved Setting prohibited Described below are control registers. (1) HSPTxData (0x0C00 0022: Index 0, Write) Bit Name R/W RTCRST Other resets D15 TxData[15] W Undefined Undefined D14 TxData[14] W Undefined Undefined D13 TxData[13] W Undefined Undefined D12 TxData[12] W Undefined Undefined D11 TxData[11] W Undefined Undefined D10 TxData[10] W Undefined Undefined D9 TxData[9] W Undefined Undefined D8 TxData[8] W Undefined Undefined Bit Name R/W RTCRST Other resets D7 TxData[7] W Undefined Undefined D6 TxData[6] W Undefined Undefined D5 TxData[5] W Undefined Undefined D4 TxData[4] W Undefined Undefined D3 TxData[3] W Undefined Undefined D2 TxData[2] W Undefined Undefined D1 TxData[1] W Undefined Undefined D0 TxData[0] W Undefined Undefined Bit D[15:0] Name TxData[15:0] Transmit data Function 485 CHAPTER 25 HSP (MODEM INTERFACE UNIT) (2) HSPCNTL (0x0C00 0022: Index 1, Write) Bit Name R/W RTCRST Other resets D15 Reserved W 0 0 D14 Reserved W 0 0 D13 Reserved W Undefined Undefined D12 Reserved W Undefined Undefined D11 Reserved W Undefined Undefined D10 Reserved W Undefined Undefined D9 Reserved W Undefined Undefined D8 Reserved W Undefined Undefined Bit Name R/W RTCRST Other resets D7 NTORST W 0 0 D6 ENIRQ W 0 0 D5 START W 0 0 D4 Reserved W 0 0 D3 ENTX W 0 0 D2 IRQS2 W 0 0 D1 IRQS1 W 0 0 D0 IRQS0 W 0 0 Bit D[15:8] D[7] Reserved NTORST Name Write 0 when writing. Function Disable timeout reset When this bit is "0", it enables a timeout to occur when a specified number of errors have been counted, at which point the HSP resets itself. 1 : Disable 0 : Enable Interrupt enable 1 : Enable 0 : Disable RX/TX FIFO pointer initialization When this bit is set to "1", the RX/TX FIFO pointer is set to its initial position. 1 : Initialize (at rising edge) 0 : Status hold Write 0 when writing. Transfer enable 1 : Enable 0 : Disable Interrupt signal select. However, IRQ signal is always selected whatever value is set to these bits. D[6] ENIRQ D[5] START D[4] D[3] Reserved ENTX D[2:0] IRQS[2:0] Caution If 1 is set to ENTX bit, the only way to stop the operation is by resetting the HSP unit. 486 CHAPTER 25 HSP (MODEM INTERFACE UNIT) (3) HSPEXTOUT (0x0C00 0022: Index 2, Write) Bit Name R/W RTCRST Other resets D15 Reserved W Undefined Undefined D14 Reserved W Undefined Undefined D13 Reserved W Undefined Undefined D12 Reserved W Undefined Undefined D11 Reserved W Undefined Undefined D10 Reserved W Undefined Undefined D9 Reserved W Undefined Undefined D8 Reserved W Undefined Undefined Bit Name R/W RTCRST Other resets D7 Reserved W Undefined Undefined D6 HC0 W 0 0 D5 TELECON W 0 0 D4 Reserved W 0 0 D3 MUTE W 0 0 D2 AFERST W 1 1 D1 Reserved W 0 0 D0 OFFHOOK W 0 0 Bit D[15:7] D[6] Reserved HC0 Name Write 0 when writing. Select CODEC mode This bit is connected to the HC0 pin. 1 : High-level signal output 0 : Low-level signal output Function D[5] TELECON Hand set relay control This bit is connected to the TELECON pin. 1 : High-level signal output 0 : Low-level signal output Write 0 when writing. Mute speaker This bit is connected to the MUTE pin. 1 : High-level signal output 0 : Low-level signal output CODEC reset This bit is connected to the AFERST# pin. 1 : High-level signal output 0 : Low-level signal output Write 0 when writing. OFF HOOK relay control This bit is connected to the OFFHOOK pin. 1 : High-level signal output 0 : Low-level signal output D[4] D[3] Reserved MUTE D[2] AFERST D[1] D[0] Reserved OFFHOOK This register is used to set output values of various signals when the INDEX number is 2. 487 CHAPTER 25 HSP (MODEM INTERFACE UNIT) (4) HSPTOC and HSPMCLKD (0x0C00 0022: Index 3, Write) Bit Name R/W RTCRST Other resets D15 Reserved W Undefined Undefined D14 Reserved W Undefined Undefined D13 Reserved W Undefined Undefined D12 Reserved W Undefined Undefined D11 TOC3 W 0 0 D10 TOC2 W 0 0 D9 TOC1 W 0 0 D8 TOC0 W 0 0 Bit Name R/W RTCRST Other resets D7 Reserved W Undefined Undefined D6 Reserved W Undefined Undefined D5 Reserved W Undefined Undefined D4 MCLKD4 W 1 1 D3 MCLKD3 W 1 1 D2 MCLKD2 W 1 1 D1 MCLKD1 W 1 1 D0 MCLKD0 W 0 0 Bit D[15:12] D[11:8] D[7:5] D[4:0] Reserved TOC[3:0] Reserved Name Write 0 when writing. High-order 4 bits of timeout count Write 0 when writing. Function MCLKD[4:0] HSPMCLK divisor to clock input HSPMCLK frequency = 18.432 MHz / (MCLKD[4:0] + 2) The upper byte of this register sets the timeout counter value and lower byte sets the HSPMCLK's division ratio when the INDEX number is 3. TOC[3:0] is used to set the high-order four bits of the final count of the timeout counter. The timeout counter is a 12-bit counter and is incremented once for each interrupt signal that is not serviced. The low-order 8 bits are automatically set to 0 when TOC[3:0] is set. When the specified timeout count value is reached, TO bit of HSPSTS register is set to 1. The user is responsible for resetting the HSP core to prevent a system hang-up. MCLKD[4:0] is used to set the division ratio when the 18.432-MHz clock supplied to HSPMCLK pin can be output using a programmable division ratio. If MCLKD[4:0] is "0", there is no clock division and the 18.432-MHz clock is output. Note that an even number must be set to MCLKD[4:0]. 488 CHAPTER 25 HSP (MODEM INTERFACE UNIT) (5) HSPFFSZ (0x0C00 0022: Index 4, Write) Bit Name R/W RTCRST Other resets D15 Reserved W Undefined Undefined D14 Reserved W Undefined Undefined D13 Reserved W Undefined Undefined D12 Reserved W 0 0 D11 Reserved W 0 0 D10 Reserved W 0 0 D9 Reserved W 0 0 D8 Reserved W 0 0 Bit Name R/W RTCRST Other resets D7 Reserved W Undefined Undefined D6 Reserved W Undefined Undefined D5 FFSZ5 W 1 1 D4 FFSZ4 W 0 0 D3 FFSZ3 W 0 0 D2 FFSZ2 W 0 0 D1 FFSZ1 W 0 0 D0 FFSZ0 W 0 0 Bit D[15:6] D[5:0] Reserved FFSZ[5:0] Name Write 0 when writing. FIFO size control Function When the INDEX number is 4, this register is used to set the transmit/receive buffer size, and can be set up to 32 (0x20). If buffer-full interrupt is enabled, an interrupt will occur when the data in the transmit/receive buffer reaches to the size set in this register. 489 CHAPTER 25 HSP (MODEM INTERFACE UNIT) (6) HSPRxData (0x0C00 0022: Index 0, Read) Bit Name R/W RTCRST Other resets D15 RxData[15] R Undefined Undefined D14 RxData[14] R Undefined Undefined D13 RxData[13] R Undefined Undefined D12 RxData[12] R Undefined Undefined D11 RxData[11] R Undefined Undefined D10 RxData[10] R Undefined Undefined D9 RxData[9] R Undefined Undefined D8 RxData[8] R Undefined Undefined Bit Name R/W RTCRST Other resets D7 RxData[7] R Undefined Undefined D6 RxData[6] R Undefined Undefined D5 RxData[5] R Undefined Undefined D4 RxData[4] R Undefined Undefined D3 RxData[3] R Undefined Undefined D2 RxData[2] R Undefined Undefined D1 RxData[1] R Undefined Undefined D0 RxData[0] R Undefined Undefined Bit D[15:0] Name RxData[15:0] Receive data from the receive FIFO Function This register is used to store the receive data from the receive FIFO when the INDEX number is 0. 490 CHAPTER 25 HSP (MODEM INTERFACE UNIT) (7) HSPSTS (0x0C00 0022: Index 1, Read) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R Undefined Undefined D9 Reserved R Undefined Undefined D8 Reserved R Undefined Undefined Bit Name R/W RTCRST Other resets D7 AFESEL1 R Undefined Undefined D6 AFESEL0 R Undefined Undefined D5 IBYTE R Undefined Undefined D4 TO R 0 0 D3 CFGCP R 0 0 D2 IRQS R 0 0 D1 RxOVRUN R 0 0 D0 TxUDRUN R 0 0 Bit D[15:8] D[7:6] D[5] D[4] Reserved Name 0 is returned after read. Function AFESEL[1:0] IBYTE TO Indicates the AFESEL[1:0] signal (internal) state Indicates the BYTE signal (internal) state Error-related timeout 1 : Timeout occurred 0 : No timeout CODEC configuration complete 1 : Complete 0 : Not complete Pending interrupt exists 1 : Exists 0 : No pending interrupts Receive overrun occurred 1 : Occurred 0 : No receive overruns Transmit underrun occurred 1 : Occurred 0 : No transmit overruns D[3] CFGCP D[2] IRQS D[1] RxOVRUN D[0] TxUDRUN This register is used to indicate the status in communication when the INDEX number is 1. TO bit is set (to "1") when the timeout counter reaches the value specified by the TOC bit of HSPTOC register. CFGCP bit indicates whether or not CODEC initialization has been completed. Actually, this bit is set (to "1") when the START bit of HSPCNTL register has been set as active to reset the FIFO pointer and then 9-word data has been transmitted (1 word = 16 bits). IRQS bit indicates whether or not any pending interrupt exists. When an interrupt request from HSP to the CPU core is in pending, the request is cleared after this register is read. IRQS, RxOVRUN, TxUDRUN bits are cleared (to "0") when read. 491 CHAPTER 25 HSP (MODEM INTERFACE UNIT) (8) HSPID and HSPEXTIN (0x0C00 0022: Index 2, Read) Bit Name R/W RTCRST Other resets D15 ID7 R 0 0 D14 ID6 R 0 0 D13 ID5 R 0 0 D12 ID4 R 1 1 D11 ID3 R 0 0 D10 ID2 R 0 0 D9 ID1 R 0 0 D8 ID0 R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R Undefined Undefined D6 Reserved R Undefined Undefined D5 Reserved R Undefined Undefined D4 Reserved R Undefined Undefined D3 Reserved R Undefined Undefined D2 Reserved R Undefined Undefined D1 ILCS R Undefined Undefined D0 IRING R Undefined Undefined Bit D[15:8] D[7:2] D[1] D[0] ID[7:0] Reserved ILCS IRING Name Function Indicates HSP unit's ID and revision number 0 is returned after read. ILCSENSE input pin state indication IRING input pin state indication The upper byte of this register is used to indicate the ID of HSP, and the lower byte is used to indicate the status of the HSP input signals. ID[7:0] is divided into two parts. The high-order 4 bits ID[7:4] indicate the ID number of HSP, and the low-order 4 bits ID[3:0] indicate the revision number of HSP. 492 CHAPTER 25 HSP (MODEM INTERFACE UNIT) (9) HSPERRCNT (0x0C00 0022: Index 3, Read) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 ERRCNT11 R 0 0 D10 ERRCNT10 R 0 0 D9 ERRCNT9 R 0 0 D8 ERRCNT8 R 0 0 Bit Name R/W RTCRST Other resets D7 ERRCNT7 R 0 0 D6 ERRCNT6 R 0 0 D5 ERRCNT5 R 0 0 D4 ERRCNT4 R 0 0 D3 ERRCNT3 R 0 0 D2 ERRCNT2 R 0 0 D1 ERRCNT1 R 0 0 D0 ERRCNT0 R 0 0 Bit D[15:12] D[11:0] Reserved Name 0 is returned after read. Error count Function ERRCNT[11:0] This register is used to indicate the number of errors when the INDEX number is 3. This register indicates the number of overrun or underrun errors that have occurred. synchronizing software and hardware. 25.2.3 HSP ID Register, HSP I/O Address Program Confirmation Register The specific values are displayed to HSPID[7:0] and HSPPCS[7:0] registers following normal access of HSPPCTEL register. 25.2.4 HSP Signature Checking Port HSPPCTEL[7:0] register must be accessed when to start using HSP unit. 0xA5 can be read from the HSPPCS register by writing a certain value. Other registers cannot be accessed unless this processing is executed. It must be executed during initialization. This is used for 493 CHAPTER 25 HSP (MODEM INTERFACE UNIT) 25.3 POWER CONTROL Power control of the CODEC and AFE can be performed using the OPD# pin and the BSC bit (HSPINIT). The following is an example of a control method using these units. Figure 25-3. Block Diagram of HSP Interface Power Control Voltage control unit L: ON H: OFF VR4102 OPD# pin BSC bit Telephone CODEC AFE line HSP interface other than OPD# (1) After RTC reset Item OPD# pin BSC bit HSP bus state VR4102 power CODEC/AFE power OFF ON ON ON 1 2 3 4 When initialized During power-on of CODEC or AFE When HSP bus's gate is set to "ON" Software modem control L H H H 0 0 1 1 Note Note Normal Normal ON ON ON ON Note Refer to 2.3 PIN STATUS UPON A SPECIFIC STATE. (2) During power-down (VR4102: Fullspeed/Standby/Suspend mode) Item OPD# pin BSC bit HSP bus state VR4102 power CODEC/AFE power ON ON OFF 1 2 3 Operation complete When HSP bus's gate is set to "OFF" When CODEC or AFE power is set to "OFF" If necessary, execute STANDBY/ SUSPEND command H H L 1 0 0 Normal Note Note ON ON ON 4 L 0 Note ON OFF Note Refer to 2.3 PIN STATUS UPON A SPECIFIC STATE. 494 CHAPTER 25 HSP (MODEM INTERFACE UNIT) (3) During recovery from power-down (VR4102: Fullspeed/Standby/Suspend mode) Item OPD# pin BSC bit HSP bus state VR4102 power CODEC/AFE power OFF ON ON ON 1 2 3 4 Power down status During power-on of CODEC or AFE When HSP bus's gate is set to "ON" Use HSP unit L H H H 0 0 1 1 Note Note Normal Normal ON ON ON ON Note Refer to 2.3 PIN STATUS UPON A SPECIFIC STATE. (4) When changing to Hibernate mode (the following processing must occur before entering Hibernate mode) Item OPD# pin BSC bit HSP bus state VR4102 power CODEC/AFE power ON ON OFF 1 2 3 Operation complete When HSP bus's gate is set to "OFF" When CODEC or AFE power is set to "OFF" Execute HIBERNATE command H H L 1 0 0 Normal Note Note ON ON ON 4 L 0 Note ON OFF Note Refer to 2.3 PIN STATUS UPON A SPECIFIC STATE. (5) During recovery from Hibernate mode to use HSP unit Item OPD# pin BSC bit HSP bus state VR4102 power CODEC/AFE power OFF ON ON ON 1 2 3 4 During Hibernate mode During power-on of CODEC or AFE When HSP bus's gate is set to "ON" Use HSP unit L H H H 0 0 1 1 Note Note Normal Normal ON ON ON ON Note Refer to 2.3 PIN STATUS UPON A SPECIFIC STATE. 495 [MEMO] 496 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) The FIR operation and register settings are described below. 26.1 GENERAL This unit supports the IrDA 1.1 high-speed infrared communication physical layer standard. Supported FIR (Fast SIR) transfer rates include 0.576 Mbps, 1.152 Mbps, and 4 Mbps. SIR (up to 115.2 kbps) is not supported. 497 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 26.2 REGISTER SET The FIR registers are listed below. Table 26-1. FIR Registers Address 0x0C00 0040 0x0C00 0042 0x0C00 0044 0x0C00 0050 0x0C00 0052 0x0C00 0054 0x0C00 0056 0x0C00 0058 0x0C00 005C 0x0C00 005E 0x0C00 0060 0x0C00 0062 0x0C00 0064 0x0C00 0066 0x0C00 0068 0x0C00 006A 0x0C00 006C 0x0C00 006E 0x0C00 0070 0x0C00 0074 R/W R/W R/W R/W W R R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W R Register symbols FRSTR DPINTR DPCNTR TDR RDR IMR FSR IRSR1 CRCSR FIRCR MIRCR DMACR DMAER TXIR RXIR IFR RXSTS TXFL MRXF RXFL Function FIR Reset register DMA Page Interrupt register DMA Control register Transmit Data register Receive Data register Interrupt Mask register FIFO Setup register Infrared Setup register 1 CRC Setup register FIR Control register MIR Control register DMA Control register DMA Enable register Transmit Indication register Receive Indication register Interrupt Flag register Receive Status register Transmit Frame Length Maximum Receive Frame Length Receive Frame Length register These registers are described in detail below. 498 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 26.2.1 FRSTR (0x0C00 0040) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 Reserved R 0 0 D0 FRST R/W 0 0 Bit D15 to D1 D0 Name Reserved FRST Function Write 0 when writing. 0 is returned after a read. FIR reset. Set 0 when releasing reset. 0: Normal 1: Reset 499 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 26.2.2 DPINTR (0x0C00 0042) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 FDPINT5 R 0 0 D3 FDPINT4 R/W 0 0 D2 FDPINT3 R/W 0 0 D1 FDPINT2 R/W 0 0 D0 FDPINT1 R/W 0 0 Bit D15 to D5 D4 Name Reserved FDPINT5 Function Write 0 when writing. 0 is returned after a read. This bit indicates an FIR macro interrupt occurs. Cleared to 0 when 1 is written. 0: Normal 1: Occurred This bit indicates that the DMA buffer (receive side) becomes full (2 pages). Cleared to 0 when 1 is written. 0: Normal 1: Occurred (DMA request is stopped) Caution The last data of the transfer data is not guaranteed. D3 FDPINT4 D2 FDPINT3 This bit indicates that the DMA buffer (transmit side) becomes full (2 pages). Cleared to 0 when 1 is written. 0: Normal 1: Occurred (DMA request is stopped) Caution The last data of the transfer data is not guaranteed. D1 FDPINT2 This bit indicates that the DMA buffer (receive side) becomes full (1 page). Cleared to 0 when 1 is written. 0: Normal 1: Occurred (when bit 0 of DPCNTR is 1, DMA request is stopped) Caution When 1-page transfer is set, the last data of the transfer data is not guaranteed. D0 FDPINT1 This bit indicates that the DMA buffer (transmit side) becomes full (1 page). Cleared to 0 when 1 is written. 0: Normal 1: Occurred (when bit 0 of DPCNTR is 1, DMA request is stopped) Caution When 1-page transfer is set, the last data of the transfer data is not guaranteed. This register is used to indicate the generation of FIR's DMA page interrupt request. 500 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 26.2.3 DPCNTR (0x0C00 0044) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 Reserved R 0 0 D0 FDPCNT R/W 0 0 Bit D15 to D1 D0 Name Reserved FDPCNT Function Write 0 when writing. 0 is returned after a read. DMA transfer stopping boundary. 0: 2-page boundary (the last data of the second page is not guaranteed) 1: 1-page boundary (the last data of the first page is not guaranteed) 501 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 26.2.4 TDR (0x0C00 0050) Bit Name R/W RTCRST Other resets D15 Reserved W 0 0 D14 Reserved W 0 0 D13 Reserved W 0 0 D12 Reserved W 0 0 D11 Reserved W 0 0 D10 Reserved W 0 0 D9 Reserved W 0 0 D8 Reserved W 0 0 Bit Name R/W RTCRST Other resets D7 TDR7 W 0 0 D6 TDR6 W 0 0 D5 TDR5 W 0 0 D4 TDR4 W 0 0 D3 TDR3 W 0 0 D2 TDR2 W 0 0 D1 TDR1 W 0 0 D0 TDR0 W 0 0 Bit D15 to D8 D7 to D0 Name Reserved TDR7 to 0 Function Write 0 when writing. 0 is returned after a read. Transmit FIFO [Function] This register is used to store the address to which data is written for the transmit data store FIFO. Up to 64- or 32-byte data (determined by bit 3 of FSR) is stored to the transmit data store FIFO. Transmit data FIFO is used as follows. (1) Write Data is written to the transmit data store FIFO while the IrDA is operating. When a write operation is completed, the write pointer of the transmit data store FIFO is incremented. However, if data is written when this write pointer is full, it is not incremented. After the data of frame size is written to the TXFL register in a status other than the transmit busy status (start enable), if the data written to this register reaches frame size, data transfer starts even if the number of write to this register is short of the threshold. This is Start 1. After that, data is always transferred if it reaches frame size, even if it is short of the threshold. This is Start 2. (2) Read After frame transfer is completed, the sequencer reads the transmit data during the data transfer sequence, and the read pointer is incremented. If read is done while the transmit FIFO is empty, a transmit underrun error occurs. This stops the current frame transmission and then starts the abort frame transmission. The following frames scheduled to be transmitted next are not transferred. 502 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 26.2.5 RDR (0x0C00 0052) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 RDR7 R 0 0 D6 RDR6 R 0 0 D5 RDR5 R 0 0 D4 RDR4 R 0 0 D3 RDR3 R 0 0 D2 RDR2 R 0 0 D1 RDR1 R 0 0 D0 RDR0 R 0 0 Bit D15 to D8 D7 to D0 Name Reserved RDR7 to 0 Function Write 0 when writing. 0 is returned after a read. Receive FIFO [Function] This register is used to store the address from which data is read for the receive data store FIFO. Up to 64- or 32-byte data (determined by bit 3 of FSR) is stored to the receive data store FIFO. Receive data is used as follows. (1) Write During a frame data reception, the sequencer writes the receive data during the data transfer sequence, and the write pointer is incremented. If data is written when the unread data in the receive FIFO reaches the maximum volume, the receive overrun error occurs and the current frame reception is ended. The write pointer is not incremented. After the receive FIFO is cleared, if the number of received frames is less than 7 frames, it is possible to continue frame reception. To receive 8 or more frames, read all the data and frames that are already received from the receive FIFO, then clear the receive FIFO and restart reception. (2) Read Data is read from the receive data store FIFO while the IrDA is operating. When a read operation is completed, the read pointer of the receive data store FIFO is incremented. However, it is not incremented when the receive FIFO is empty. When the number of read frames reaches the receive frame size, an interrupt occurs and bit 7 of the RXSTS register is set to 1. [Caution] If data is read when the receive FIFO is empty (read pointer = write pointer), it may contend with the sequencer's write operation. This may cause undefined data. The error generated by read underrun is not reported in this macro. 503 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 26.2.6 IMR (0x0C00 0054) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 IMR7 R/W 0 0 D6 IMR6 R/W 0 0 D5 IMR5 R/W 0 0 D4 IMR4 R/W 0 0 D3 IMR3 R/W 0 0 D2 IMR2 R/W 0 0 D1 IMR1 R/W 0 0 D0 IMR0 R/W 0 0 Bit D15 to D8 D7 to D0 Name Reserved IMR7 to 0 Function Write 0 when writing. 0 is returned after a read. These bits are used to enable/prohibit interrupt output. This register sets whether or not to inform outside when the interrupt is generated. Each bit corresponds to the equivalent IFR register bit. When interrupt output is enabled and corresponding bit is 1, interrupt output is active. IMRn 0 1 Interrupt output Prohibit Enable [Caution] The IFR register is set irrespective of this register's setting. 504 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 26.2.7 FSR (0x0C00 0056) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 RX_TH1 R/W 0 0 D6 RX_TH0 R/W 0 0 D5 TX_TH1 R/W 0 0 D4 TX_TH0 R/W 0 0 D3 F_SIZE R/W 0 0 D2 TXF_CLR R/W 0 0 D1 RXF_CLR R/W 0 0 D0 TX_STOP R/W 0 0 Bit D15 to D8 D7 and D6 Name Reserved RX_TH1, 0 Function Write 0 when writing. 0 is returned after a read. These bits are used to specify the receive FIFO's threshold. RX_TH 1, 0 00 01 10 11 F_SIZE = 0 1 byte 4 bytes 16 bytes 26 bytes F_SIZE = 1 1 byte 8 bytes 32 bytes 48 bytes D5 and D4 TX_TH1, 0 These bits are used to specify the transmit FIFO's threshold. TX_TH 1, 0 00 01 10 11 F_SIZE = 0 1 byte 8 bytes 16 bytes 26 bytes F_SIZE = 1 1 byte 16 bytes 32 bytes 48 bytes D3 F_SIZE This bit is used to specify the maximum size of transmit/receive FIFO. F_SIZE FIFO maximum size 32 bytes 64 bytes 0 1 D2 TXF_CLR Transmit FIFO clear trigger (read value = 0) When this bit is set to 1, the pointers of the transmit data FIFO and transmit frame size FIFO are initialized. Receive FIFO clear trigger (read value = 0) When this bit is set to 1, the pointers of the receive data FIFO, receive frame size FIFO, and receive status FIFO are initialized. Transmission stop trigger (read value = 0) When this bit is set to 1, the current frame transmission is stopped and the abort frame transmission starts. The following frames scheduled to be transmitted next are not transferred. Setting 1 to this bit also stops DMA operation and generates the DMA completion interrupt. D1 RXF_CLR D0 TX_STOP This register is used to specify the settings for the transmit/receive FIFOs. 505 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) [Caution] During transmission/reception, the contents of bits 7 through 3 of the FSR register must not be changed (refresh is possible). The data in the FIFO is not cleared by FIFO clear. Regardless of transmission/reception, after data transfer is completed, set the TX_STOP bit and stop the DMA operation. When reception, confirm the transfer data command bit and stop the DMA operation. 506 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 26.2.8 IRSR1 (0x0C00 0058) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 IRDA_EN R/W 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 IRDA_MD R/W 0 0 D0 MIR_MD R/W 0 0 Bit D15 to D8 D7 Name Reserved IRDA_EN Function Write 0 when writing. 0 is returned after a read. This bit is used to control (enable/prohibit) IrDA macro operation. When this bit is set to 1, peripheral main block's reset is released and clock supply starts. 0: Prohibit 1: Enable Write 0 when writing. 0 is returned after a read. These bits are used to specify the IrDA/MIR mode. IRDA_MD MIR_MD Operation mode Frequency Modulation method 4 PPM Bit stream/stuff Bit stream/stuff D6 to D2 D1 and D0 Reserved IRDA_MD/ MIR_MD 0 1 1 1 or 0 0 1 FIR mode MIR full mode MIR half mode 8 MHz 1.152MHz 0.576 MHz [Caution] During transmission/reception, the contents of this register must not be changed (refresh is possible). When the IRDA_EN bit is set, the peripheral main part reset is released and the clock supply starts. Pulse output level changes according to operation mode changes. The operation mode should be changed after changing the IrDA operation to prohibit state (by setting bit (bit 7) to 0). Once the mode is changed, be sure to switch bit inversion of I/O data ON/OFF by setting bit 0 of the CRCSR register. The output level does not change because output latch is reset. Example) Sequence of changing operation mode from FIR mode to MIR full mode clr1 set1 set1 set1 0x7, IRSR1 0x1, IRSR1 0x0, CRCSR 0x7, IRSR1 Prohibit IrDA operation Change the mode Set bit inversion Enable IrDA operation 507 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 26.2.9 CRCSR (0x0C00 005C) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 TX_EN R/W 0 0 D6 RX_EN R/W 0 0 D5 4PPM_DIS R/W 0 0 D4 DPLL_DIS R/W 0 0 D3 Reserved R 0 0 D2 NON_CRC R/W 1 1 D1 CRC_INV R/W 0 0 D0 DATA_INV R/W 0 0 Bit D15 to D8 D7 Name Reserved TX_EN Function Write 0 when writing. 0 is returned after a read. This bit is used to control (enable/prohibit) masking of transmit start enable flag. Masking sequence transition to transmission enable state entered by writing the TXFL register is: 0: Prohibited 1: Enabled This bit is used to control (enable/prohibit) receive operation. Releasing masking of receive line, sampling data, and generating receive clocks are: 0: Prohibited 1: Enabled This bit is used to control (enable/prohibit) the 4PPM modulation (for debugging). The 4PPM modulation of transmit data is: 0: Enabled 1: Prohibited This bit is used to control (enable/prohibit) the bit correction (for debugging). Bit correction of received data is: 0: Enabled 1: Prohibited Write 0 when writing. 0 is returned after a read. This bit is used to control whether or not a CRC is added for frames to be transmitted (for debugging). 0: Add CRC 1: Do not add CRC D6 RX_EN D5 4PPM_DIS D4 DPLL_DIS D3 D2 Reserved NON_CRC 508 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) Bit D1 Name CRC_INV Function This bit is used to set whether or not a CRC is inverted to create an incorrect CRC in the normal routine. 0: Normal CRC (not inverted) 1: Inverted CRC This bit is used to set whether or not received/transmitted data I/O is inverted. 0: Normal (not inverted) 1: Inverted Be sure to set as normal in FIR, and set as inverted in MIR. D0 DATA_INV [Caution] During transmission/reception, the contents of this register must not be changed (refresh is possible). 26.2.10 FIRCR (0x0C00 005E) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 PA_LEN2 R/W 1 1 D6 PA_LEN1 R/W 0 0 D5 PA_LEN0 R/W 0 0 D4 W_PULSE1 R 0 0 D3 W_PULSE0 R 0 0 D2 F_WIDTH2 R/W 1 1 D1 F_WIDTH1 R/W 0 0 D0 F_WIDTH0 R/W 1 1 509 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) Bit D15 to D8 D7 to D5 Name Reserved PA_LEN2 to PA_LEN0 Function Write 0 when writing. 0 is returned after a read. These bits are used to specify the number of PA (preamble) added to FIR's transmit frame. PA_LEN2 to 0 001 010 011 100 (default) 111 Others Number of PA 1 2 4 16 32 16 (reserved) D4 and D3 W_PULSE1 and W_PULSE0 These bits are used to specify the undefined receive pulse width area. Pulse width within the undefined receive pulse width area = recognized as single pulse Pulse width within other than the undefined receive pulse width area = recognized as double pulse W_PULSE 1 and 0 00 01 (default) 10 11 Undefined receive pulse width area 7 to 8 clocks 8 to 9 clocks 9 to 10 clocks 10 to 11 clocks D2 to D0 F_WIDTH2 to F_WIDTH0 These bits are used to specify FIR pulse modulation width. The FIR's output pulse is modulated to a pulse consisting of the number of reference clocks (48 MHz) specified by these bits. F_WIDTH2 to 0 000 001 010 011 100 101 (default) Others Single pulse 1 clock 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks Double pulse 7 clocks 8 clocks 9 clocks 10 clocks 11 clocks 12 clocks Setting prohibited [Function] Controls the FIR operation. [Caution] During transmission/reception, the contents of this register must not be changed. 510 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 26.2.11 MIRCR (0x0C00 0060) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 STA_LEN2 R/W 0 0 D6 STA_LEN1 R/W 1 1 D5 STA_LEN0 R/W 0 0 D4 M_WIDTH4 R/W 0 0 D3 M_WIDTH3 R/W 1 1 D2 M_WIDTH2 R/W 0 0 D1 M_WIDTH1 R/W 0 0 D0 M_WIDTH0 R/W 1 1 Bit D15 to D8 D7 to D5 Name Reserved STA_LEN2 to STA_LEN0 Function Write 0 when writing. 0 is returned after a read. These bits are used to specify the number of STA (start flag) added to MIR's transmit frame. STA_LEN2 to 0 001 010 (default) 011 100 111 Others Number of STA 1 2 4 16 32 2 (reserved) D4 to D0 M_WIDTH4 to M_WIDTH0 These bits are used to specify the MIR pulse modulation width. The MIR's output pulse is modulated to a pulse consisting of the number of reference clocks (48 MHz) specified by these bits. F_WIDTH4 to 0 00000 00001 : 01001 (default) : 10100 : 11111 Single pulse 1 clock 2 clocks : 10 clocks : 21 clocks : 32 clocks [Function] Controls the MIR operation. The nominal pulse width of MIR is 1/4. Therefore, be sure to set as follows: MIR full mode (1.152 MHz) = 01001 (rate 10/42) MIR half mode (0.576 MHz) = 10100 (rate 21/83) [Caution] During transmission/reception, the contents of this register must not be changed. 511 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 26.2.12 DMACR (0x0C00 0062) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 ACES_MD R/W 0 0 D6 TRANS_MD R/W 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 DEMAND2 R/W 0 0 D1 DEMAND1 R/W 0 0 D0 DEMAND0 R/W 0 0 Bit D15 to D8 D7 Name Reserved ACES_MD Function Write 0 when writing. 0 is returned after a read. This bit is used to select the access mode. Write 0 when writing. 0 is returned after a read. This bit is used to specify the transfer direction. TRANS_MD 0 1 Transfer direction Memory o TDR RDR o Memory D6 TRANS_MD D5 to D3 D2 to D0 Reserved DEMAND2 to DEMAND0 Write 0 when writing. 0 is returned after a read. These bits are used to specify the demand size. DEMAND2 to 0 000 001 010 011 100 101 110 111 Demand size 1 2 3 4 5 6 7 Free size [Caution] During the DMA operation (both the master side and IrDA side), the contents of this register must not be changed. 512 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 26.2.13 DMAER (0x0C00 0064) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Reserved R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 Reserved R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 DMA_BUSY R 0 0 D0 DMA_EN R/W 0 0 Bit D15 to D2 D1 Name Reserved DMA_BUSY Function Write 0 when writing. 0 is returned after a read. DMA busy status 1: Busy 0: Not Busy This bit is used as a DMA operation enable trigger. 1: Enable 0: Disable Note that the DMA is not stopped by clearing this bit (to 0). D0 DMA_EN [Function] The DMA_BUSY bit is set automatically by setting the DMA_EN bit to 1. The DMA_BUSY bit is cleared when bit 0 of the FSR register is set or when all frame transmit data is written. 513 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 26.2.14 TXIR (0x0C00 0066) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 TX_BUSY R 0 0 D6 Reserved R 0 0 D5 LAST_TFL R 0 0 D4 TX_TH_OV R 0 0 D3 Reserved R 0 0 D2 TXF_UNDR R 0 0 D1 TXF_FULL R 0 0 D0 TXF_EMP R 0 0 Bit D15 to D8 D7 Name Reserved TX_BUSY Function Write 0 when writing. 0 is returned after a read. Transmission busy. This bit is set to 1 during the period between PA (in FIR) or STA (in MIR) transmission and abort transmission. 0: Not Busy 1: Busy Write 0 when writing. 0 is returned after a read. Last transmission frame status. This bit indicates whether data exists or not in the transmission frame size FIFO. This bit changes when the STA transmission sequence ends. Its initial value is 1. 0: Normal 1: Exists Transmission FIFO threshold over status. This bit indicates whether or not the data size within the transmission FIFO exceeds the threshold. 0: Normal 1: Excesses Write 0 when writing. 0 is returned after a read. Transmission FIFO underrun status. This bit indicates whether or not data is read when there is no data in the transmission FIFO. 0: Normal 1: Data is read Transmission FIFO full status. This bit indicates that there is no writable space in the transmission FIFO. 0: Normal 1: No writable space Transmission FIFO empty status. This bit indicates whether or not data to be read exists in the transmission FIFO. 0: Normal 1: Exists D6 D5 Reserved LAST_TFL D4 TX_TH_OV D3 D2 Reserved TXF_UNDR D1 TXF_FULL D0 TXF_EMP 514 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 26.2.15 RXIR (0x0C00 0068) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 RX_BUSY R 0 0 D6 END_DATA R 0 0 D5 LAST_RFL R 0 0 D4 RX_TH_O R 0 0 D3 Reserved R 0 0 D2 Reserved R 0 0 D1 RXF_FULL R 0 0 D0 RXF_EMP R 0 0 Bit D15 to D8 D7 Name Reserved RX_BUSY Function Write 0 when writing. 0 is returned after a read. Reception busy. This bit is set to 1 during the period between when PA (in FIR) or STA (in MIR) is detected and when reception ends. 0: Not Busy 1: Busy Frame last data status. This bit indicates whether the last data of frame that is received completely exists or not in the FIFO. 0: Normal 1: Exists Last reception frame status. This bit is set (to 1) when the reception result (frame size and status) of the 7th frame is stored. 0: Normal 1: Result is stored Reception FIFO threshold over status. This bit indicates whether or not the data size within the reception FIFO exceeds the threshold. 0: Normal 1: Excesses Write 0 when writing. 0 is returned after a read. Reception FIFO full status. This bit indicates that there is no writable space in the reception FIFO. 0: Normal 1: No writable space Reception FIFO empty status. This bit indicates whether or not data to be read exists in the reception FIFO. 0: Normal 1: Exists D6 END_DATA D5 LAST_RFL D4 RX_TH_O D3 and D2 D1 Reserved RXF_FULL D0 RXF_EMP 515 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) [Caution] This register can be read only in IrDA mode. [Remark] Initial value is the value immediately after the IrDA operation is enabled or after the reception FIFO is cleared. 0x00 is read while the operation stops. 516 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 26.2.16 IFR (0x0C00 006A) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 TX_ABORT R 0 0 D6 TX_ERR R 0 0 D5 RX_VALID R 0 0 D4 DMA_END R 0 0 D3 RX_END R 0 0 D2 TX_END R 0 0 D1 D0 TX_WR_RQ RX_RD_RQ R 0 0 R 0 0 Bit D15 to D8 D7 Name Reserved TX_ABORT Function Write 0 when writing. 0 is returned after a read. Abort frame transmission end interrupt. This bit indicates that abort frame is transmitted and the following frame's transfer reservation is cancelled. 0: Normal 1: Cancelled Transmission error interrupt. This bit indicates that the transmission error occurs. 0: Normal 1: Occurs Reception result valid interrupt. This bit indicates that the last data of frame is read from the reception FIFO and the received status becomes valid. 0: Normal 1: Valid DMA end interrupt. This bit indicates that the DMA operation ends. 0: Normal 1: Ends Reception end interrupt. This bit indicates that STO is detected for each reception frame. 0: Normal 1: Detected Transmission end interrupt. This bit indicates that STO is transmitted for each transmission frame. 0: Normal 1: Detected D6 TX_ERR D5 RX_VALID D4 DMA_END D3 RX_END D2 TX_END 517 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) Bit D1 Name TX_WR_RQ Function Transmission data write request interrupt. This bit indicates that a transmission data write request interrupt has occurred. 0: Normal 1: Occurs Reception data read request interrupt. This bit indicates that a reception data read request interrupt has occurred. 0: Normal 1: Occurs D0 RX_RD_RQ [Caution] If bits 7 through 2 of the IFR register are set, the flags that are set to 1 before a read are all cleared to 0. 518 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 26.2.17 RXSTS (0x0C00 006C) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 Reserved R 0 0 D11 Reserved R 0 0 D10 Reserved R 0 0 D9 Reserved R 0 0 D8 Reserved R 0 0 Bit Name R/W RTCRST Other resets D7 Valid R 0 0 D6 Reserved R 0 0 D5 Reserved R 0 0 D4 RXF_OV R 0 0 D3 CRC_ERR R 0 0 D2 ABORT R 0 0 D1 MRXF_OV R 0 0 D0 Reserved R 0 0 Bit D15 to D8 D7 Name Reserved Valid Function Write 0 when writing. 0 is returned after a read. Valid status in the indication status. This bit is set to 1 when received data of one frame is read completely. 0: Received data read not completed 1: Received data read completed Write 0 when writing. 0 is returned after a read. Receive FIFO overrun error. This bit is set to 1 when a receive operation is stopped by receive FIFO's overrun. 0: Normal 1: Overrun CRC Error. This bit is set t o 1 when the receive result CRC does not match with expected value. 0: Normal 1: CRC error Abort detection error. This bit is set to 1 when a receive operation is stopped by abort frame detection. 0: Normal 1: Abort error Maximum receive frame size error. This bit is set to 1 when a receive operation is stopped by maximum receive frame size overrun. 0: Normal 1: Overrun Write 0 when writing. 0 is returned after a read. D6 and D5 D4 Reserved RXF_OV D3 CRC_ERR D2 ABORT D1 MRXF_OV D0 Reserved [Function] Reads data from the receive status store FIFO, in which data of up to 7 frames can be stored. The FIFO is initialized by setting bit 1 of the FSR register. Received status FIFO is used as follows. 519 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) (1) Write (bits 4 to 1) The receive status is written to this register at the same timing of writing data to the receive frame length register. This register shares the write pointer with the receive frame length register. (2) Write (bit 7) This bit is set to 1 when the data of receive frame size is read from the FIFO. While this bit is 1, data is recognized as valid. (3) Read This register shares the read pointer with the receive frame length register. The read pointer is incremented by reading the RXFL (receive frame length) register after valid data is read from this register. 520 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 26.2.18 TXFL (0x0C00 006E) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 TXFL12 R/W 0 0 D11 TXFL11 R/W 0 0 D10 TXFL10 R/W 0 0 D9 TXFL9 R/W 0 0 D8 TXFL8 R/W 0 0 Bit Name R/W RTCRST Other resets D7 TXFL7 R/W 0 0 D6 TXFL6 R/W 0 0 D5 TXFL5 R/W 0 0 D4 TXFL4 R/W 0 0 D3 TXFL3 R/W 0 0 D2 TXFL2 R/W 0 0 D1 TXFL1 R/W 0 0 D0 TXFL0 R/W 0 0 Bit D15 to D13 D12 to D0 Name Reserved Function Write 0 when writing. 0 is returned after a read. TXFL12 to TXFL0 Transmit frame size. [Function] This register functions as prebuffer address for data write to the transmit frame size data store FIFO, in which data of up to 7 frames can be stored. Setting value = transmit size - 1 Setting range = 1 to 2 Kbytes The FIFO is initialized by setting bit 2 of the FSR register. (1) Write The data transmit size of frames to be transferred is written to this register. Transmission is enabled when data is written to this register in the state other than transmission busy state (after FIFO initialization and after transmission completion). The frames whose number is specified by this register are transferred continuously (back-to-back transfer). During the single frame transfer, FIFO should be initialized at each 1-frame transfer completion to restart transmit operation. (2) Read The sequencer reads the transmission size from this register after the STA flag of transmission frame is transmitted completed. Then, the read pointer is incremented. [Caution] If data exists in the FIFO when the STO transmit sequence is completed, continuous transfer mode is entered. When multiple frames are transferred, be sure to write data to the TXFL register before the STO transmit sequence is completed. 521 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 26.2.19 MRXF (0x0C00 0070) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 MRXF12 R/W 0 0 D11 MRXF11 R/W 0 0 D10 MRXF10 R/W 0 0 D9 MRXF9 R/W 0 0 D8 MRXF8 R/W 0 0 Bit Name R/W RTCRST Other resets D7 MRXF7 R/W 0 0 D6 MRXF6 R/W 0 0 D5 MRXF5 R/W 0 0 D4 MRXF4 R/W 0 0 D3 MRXF3 R/W 0 0 D2 MRXF2 R/W 0 0 D1 MRXF1 R/W 0 0 D0 MRXF0 R/W 0 0 Bit D15 to D13 D12 to D0 Name Reserved Function Write 0 when writing. 0 is returned after a read. MRXF12 to MRXF0 Specifies receivable maximum frame size. MRXF 0x0000 0x0001 : 0x1FFF MAX Tx Frame length 1 byte 2 bytes : 2 Kbytes [Function] The maximum frame size is stored in this register. When a 1-frame receive data is transferred to the receive FIFO exceeding the receivable maximum frame size set by this register, an error occurs even under frame reception to end the current frame reception. This sets bit 1 of the RXSTS register. After the receive FIFO is cleared, if the number of received frames is less than 7 frames, it is possible to continue frame reception. To receive 8 or more frames, read all the data and frames that are already received from the receive FIFO, then clear the receive FIFO and restart reception. When receiving data via the DMA operation, set the transfer size value by the following expression: DMA receivable capacitance = set value x 7 frames Caution The data exceeding the maximum size cannot be transferred to the FIFO. 522 CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 26.2.20 RXFL (0x0C00 0074) Bit Name R/W RTCRST Other resets D15 Reserved R 0 0 D14 Reserved R 0 0 D13 Reserved R 0 0 D12 RXFL12 R 0 0 D11 RXFL11 R 0 0 D10 RXFL10 R 0 0 D9 RXFL9 R 0 0 D8 RXFL8 R 0 0 Bit Name R/W RTCRST Other resets D7 RXFL7 R 0 0 D6 RXFL6 R 0 0 D5 RXFL5 R 0 0 D4 RXFL4 R 0 0 D3 RXFL3 R 0 0 D2 RXFL2 R 0 0 D1 RXFL1 R 0 0 D0 RXFL0 R 0 0 Bit D15 to D13 D12 to D0 Name Reserved Function Write 0 when writing. 0 is returned after a read. RXFL12 to RXFL0 Receive frame size. [Function] This register functions as prebuffer address for data read from the receive frame size data store FIFO, in which data of up to 7 frames can be stored. Setting value = transmit size - 1 Setting range = 1 to 2 Kbytes The FIFO is initialized by setting bit 1 of the FSR register. (1) Write When the frame reception is completed after its data is transferred (even if only 1 byte) to the receive FIFO, the sequencer writes the current transfer data size to this register, and the write pointer is incremented. When the frame reception is completed before its data is transferred to the receive FIFO, write operation is not performed (lost frame). (2) Read The read pointer is enabled to be incremented by reading valid data from the RXSTS register, and the next data can be read. [Caution] If a receive operation ends abnormally, the data size transferred to the receive FIFO at that time is written to this register. When the data of 7 frames are stored, the receive line is automatically masked. Therefore, the frame whose receive result cannot be stored is not transferred to the FIFO. The update condition of the read pointer of the receive frame size store FIFO is also valid in the test mode. 523 [MEMO] 524 CHAPTER 27 CPU INSTRUCTION SET DETAILS This chapter provides a detailed description of the operation of each VR4102 instruction in both 32- and 64-bit modes. The instructions are listed in alphabetical order. 27.1 INSTRUCTION NOTATION CONVENTIONS In this chapter, all variable subfields in an instruction format (such as rs, rt, immediate, etc.) are shown in lowercase names. For the sake of clarity, we sometimes use an alias for a variable subfield in the formats of specific instructions. For example, we use rs = base in the format for load and store instructions. Such an alias is always lower case, since it refers to a variable subfield. Figures with the actual bit encoding for all the mnemonics are located at the end of this chapter, and the bit encoding also accompanies each instruction. In the instruction descriptions that follow, the Operation section describes the operation performed by each instruction using a high-level language notation. The VR4102 can operate as either a 32- or 64-bit microprocessor and the operation for both modes is included with the instruction description. Special symbols used in the notation are described in Table 27-1. 525 CHAPTER 27 CPU INSTRUCTION SET DETAILS Table 27-1. CPU Instruction Operation Notations Symbol <|| x y Meaning Assignment. Bit string concatenation. Replication of bit value x into a y-bit string. x is always a single-bit value. Selection of bits y through z of bit string x. Little-endian bit notation is always used. If y is less than z, this expression is an empty (zero length) bit string. 2's complement or floating-point addition. 2's complement or floating-point subtraction. 2's complement or floating-point multiplication. 2's complement integer division. 2's complement modulo. Floating-point division. 2's complement less than comparison. Bit-wise logical AND. Bit-wise logical OR. Bit-wise logical XOR. Bit-wise logical NOR. General-Register x. The content of GPR [0] is always zero. Attempts to alter the content of GPR [0] have no effect. Coprocessor unit z, general register x. Coprocessor unit z, control register x. Coprocessor unit z condition signal. xy:z + * div mod / < and or xor nor GPR [x] CPR [z, x] CCR [z, x] COC [z] BigEndianMem Big-endian mode as configured at reset (0 -> Little, 1 -> Big). Specifies the endianness of the memory interface (see LoadMemory and StoreMemory), and the endianness of Kernel and Supervisor mode execution. However, this value is always 0 since the VR4102 supports the little endian order only. ReverseEndian Signal to reverse the endianness of load and store instructions. This feature is available in User mode only, and is effected by setting the RE bit of the Status register. Thus, ReverseEndian may be computed as (SR25 and User mode). However, this value is always 0 since the VR4102 supports the little endian order only. BigEndianCPU The endianness for load and store instructions (0 -> Little, 1 -> Big). In User mode, this endianness may be reversed by setting SR25. Thus, BigEndianCPU may be computed as BigEndianMem XOR ReverseEndian. However, this value is always 0 since the VR4102 supports the little endian order only. T + i: Indicates the time steps between operations. Each of the statements within a time step are defined to be executed in sequential order (as modified by conditional and loop constructs). Operations which are marked T + i: are executed at instruction cycle i relative to the start of execution of the instruction. Thus, an instruction which starts at time j executes operations marked T + i: at time i + j. The interpretation of the order of execution between two instructions or two operations which execute at the same time should be pessimistic; the order is not defined. 526 CHAPTER 27 CPU INSTRUCTION SET DETAILS (1) Instruction notation examples The following examples illustrate the application of some of the instruction notation conventions: Example #1: 16 GPR [rt] <- immediate || 0 Sixteen zero bits are concatenated with an immediate value (typically 16 bits), and the 32-bit string (with the lower 16 bits set to zero) is assigned to General-purpose register rt. Example #2: 16 (immediate15) || immediate15...0 Bit 15 (the sign bit) of an immediate value is extended for 16 bit positions, and the result is concatenated with bits 15 through 0 of the immediate value to form a 32-bit sign extended value. 27.2 LOAD AND STORE INSTRUCTIONS In the VR4102 implementation, the instruction immediately following a load may use the loaded contents of the register. In such cases, the hardware interlocks, requiring additional real cycles, so scheduling load delay slots is still desirable, although not required for functional code. In the load and store descriptions, the functions listed in Table 27-2 are used to summarize the handling of virtual addresses and physical memory. Table 27-2. Load and Store Common Functions Function Address Translation Meaning Uses the TLB to find the physical address given the virtual address. The function fails and an exception is taken if the required translation is not present in the TLB. Load Memory Uses the cache and main memory to find the contents of the word containing the specified physical address. The low-order three bits of the address and the Access Type field indicate which of each of the four bytes within the data word need to be returned. If the cache is enabled for this access, the entire word is returned and loaded into the cache. Store Memory Uses the cache, write buffer, and main memory to store the word or part of word specified as data in the word containing the specified physical address. The low-order three bits of the address and the Access Type field indicate which of each of the four bytes within the data word should be stored. As shown in Table 27-3, the Access Type field indicates the size of the data item to be loaded or stored. Regardless of access type or byte-numbering order (endianness), the address specifies the byte which has the smallest byte address in the addressed field. This is the rightmost byte in the VR4102 since it supports the littleendian order only. 527 CHAPTER 27 CPU INSTRUCTION SET DETAILS Table 27-3. Access Type Specifications for Loads/Stores Access Type Mnemonic DOUBLEWORD SEPTIBYTE SEXTIBYTE QUINTIBYTE WORD TRIPLEBYTE HALFWORD BYTE Value 7 6 5 4 3 2 1 0 Meaning 8 bytes (64 bits) 7 bytes (56 bits) 6 bytes (48 bits) 5 bytes (40 bits) 4 bytes (32 bits) 3 bytes (24 bits) 2 bytes (16 bits) 1 byte (8 bits) The bytes within the addressed doubleword which are used can be determined directly from the access type and the three low-order bits of the address. 27.3 JUMP AND BRANCH INSTRUCTIONS All jump and branch instructions have an architectural delay of exactly one instruction. That is, the instruction immediately following a jump or branch (that is, occupying the delay slot) is always executed while the target instruction is being fetched from storage. A delay slot may not itself be occupied by a jump or branch instruction; however, this error is not detected and the results of such an operation are undefined. If an exception or interrupt prevents the completion of a legal instruction during a delay slot, the hardware sets the EPC register to point at the jump or branch instruction that precedes it. When the code is restarted, both the jump or branch instructions and the instruction in the delay slot are reexecuted. Because jump and branch instructions may be restarted after exceptions or interrupts, they must be restartable. Therefore, when a jump or branch instruction stores a return link value, register r31 (the register in which the link is stored) may not be used as a source register. Since instructions must be word-aligned, a Jump Register or Jump and Link Register instruction must use a register which contains an address whose two low-order bits are zero. If these low-order bits are not zero, an address exception will occur when the jump target instruction is subsequently fetched. 27.4 SYSTEM CONTROL COPROCESSOR (CP0) INSTRUCTIONS There are some special limitations imposed on operations involving CP0 that is incorporated within the CPU. Although load and store instructions to transfer data to/from coprocessors and to move control to/from coprocessor instructions are generally permitted by the MIPS architecture, CP0 is given a somewhat protected status since it has responsibility for exception handling and memory management. Therefore, the move to/from coprocessor instructions are the only valid mechanism for writing to and reading from the CP0 registers. Several CP0 instructions are defined to directly read, write, and probe TLB entries and to modify the operating modes in preparation for returning to User mode or interrupt-enabled states. 528 CHAPTER 27 CPU INSTRUCTION SET DETAILS 27.5 CPU INSTRUCTION This section describes the functions of CPU instructions in detail for both 32-bit mode and 64-bit mode. The exception that may occur by executing each instruction is shown in the last of each instruction's description. For details of exceptions and their processes, see Chapter 6. 529 CHAPTER 27 CPU INSTRUCTION SET DETAILS ADD 31 26 25 21 20 Add 16 15 11 10 65 ADD 0 SPECIAL 000000 6 rs 5 rt 5 rd 5 0 00000 5 ADD 100000 6 Format: ADD rd, rs, rt Description: The contents of general register rs and the contents of general register rt are added to form the result. The result is placed into general register rd. In 64-bit mode, the operands must be valid sign-extended, 32-bit values. An overflow exception occurs if the carries out of bits 30 and 31 differ (2's complement overflow). The destination register rd is not modified when an integer overflow exception occurs. Operation: 32 64 T: T: GPR [rd] <- GPR [rs] + GPR [rt] temp <- GPR [rs] + GPR [rt] GPR [rd] <- (temp31) 32 || temp31...0 Exceptions: Integer overflow exception 530 CHAPTER 27 CPU INSTRUCTION SET DETAILS ADDI 31 26 25 21 20 Add Immediate 16 15 ADDI 0 ADDI 001000 6 rs 5 rt 5 immediate 16 Format: ADDI rt, rs, immediate Description: The 16-bit immediate is sign-extended and added to the contents of general register rs to form the result. The result is placed into general register rt. In 64-bit mode, the operand must be valid sign-extended, 32-bit values. An overflow exception occurs if carries out of bits 30 and 31 differ (2's complement overflow). The destination register rt is not modified when an integer overflow exception occurs. Operation: 32 64 T: T: GPR [rt] <- GPR [rs] + (immediate15) temp <- GPR [rs] + (immediate15) GPR [rt] <- (temp31) 32 48 16 || immediate15...0 || immediate15...0 || temp31...0 Exceptions: Integer overflow exception 531 CHAPTER 27 CPU INSTRUCTION SET DETAILS ADDIU 31 26 25 Add Immediate Unsigned 21 20 16 15 ADDIU 0 ADDIU 001001 6 rs 5 rt 5 immediate 16 Format: ADDIU rt, rs, immediate Description: The 16-bit immediate is sign-extended and added to the contents of general register rs to form the result. The result is placed into general register rt. No integer overflow exception occurs under any circumstances. In 64-bit mode, the operand must be valid sign-extended, 32-bit values. The only difference between this instruction and the ADDI instruction is that ADDIU never causes an integer overflow exception. Operation: 32 64 T: T: GPR [rt] <- GPR [rs] + (immediate15) temp <- GPR [rs] + (immediate15) GPR [rt] <- (temp31) 32 48 16 || immediate15...0 || immediate15...0 || temp31...0 Exceptions: None 532 CHAPTER 27 CPU INSTRUCTION SET DETAILS ADDU 31 26 25 21 20 Add Unsigned 16 15 11 10 65 ADDU 0 SPECIAL 000000 6 rs 5 rt 5 rd 5 0 00000 5 ADDU 100001 6 Format: ADDU rd, rs, rt Description: The contents of general register rs and the contents of general register rt are added to form the result. The result is placed into general register rd. No integer overflow exception occurs under any circumstances. In 64-bit mode, the operands must be valid sign-extended, 32-bit values. The only difference between this instruction and the ADD instruction is that ADDU never causes an integer overflow exception. Operation: 32 64 T: T: GPR [rd] <- GPR [rs] + GPR [rt] temp <- GPR [rs] + GPR [rt] GPR [rd] <- (temp31) 32 || temp31...0 Exceptions: None 533 CHAPTER 27 CPU INSTRUCTION SET DETAILS AND 31 26 25 21 20 And 16 15 11 10 65 AND 0 SPECIAL 000000 6 rs 5 rt 5 rd 5 0 00000 5 AND 100100 6 Format: AND rd, rs, rt Description: The contents of general register rs are combined with the contents of general register rt in a bit-wise logical AND operation. The result is placed into general register rd. Operation: 32 64 T: T: GPR [rd] <- GPR [rs] and GPR [rt] GPR [rd] <- GPR [rs] and GPR [rt] Exceptions: None 534 CHAPTER 27 CPU INSTRUCTION SET DETAILS ANDI 31 26 25 21 20 And Immediate 16 15 ANDI 0 ANDI 001100 6 rs 5 rt 5 immediate 16 Format: ANDI rt, rs, immediate Description: The 16-bit immediate is zero-extended and combined with the contents of general register rs in a bit-wise logical AND operation. The result is placed into general register rt. Operation: 32 64 T: T: GPR [rt] <- 0 GPR [rt] <- 0 16 || (immediate and GPR [rs]15...0) || (immediate and GPR [rs]15...0) 48 Exceptions: None 535 CHAPTER 27 CPU INSTRUCTION SET DETAILS BC0F 31 26 25 Branch On Coprocessor 0 False 21 20 16 15 BC0F 0 COPz Note 0100XX 6 BC 01000 5 BCF 00000 5 offset 16 Format: BC0F offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. If coprocessor 0's condition signal (CpCond: Status register bit-18 CH field), as sampled during the previous instruction, is false, then the program branches to the target address with a delay of one instruction. Because the condition line is sampled during the previous instruction, there must be at least one instruction between this instruction and a coprocessor instruction that changes the condition line. Operation: 32 T-1: T: condition <- not SR18 target <- (offset15) 14 2 || offset || 0 T+1: if condition then PC <- PC + target endif 64 T-1: T: condition <- not SR18 target <- (offset15) 46 || offset || 0 2 T+1: if condition then PC <- PC + target endif Exceptions: Coprocessor unusable exception Note See the opcode table below, or 27.6 CPU INSTRUCTION OPCODE BIT ENCODING. Opcode Table: 31 BC0F 0 30 1 29 0 28 0 27 0 26 0 25 0 24 1 23 0 22 0 21 0 20 0 19 0 18 0 17 0 16 0 0 Opcode Coprocessor number BC sub-opcode Branch condition 536 CHAPTER 27 CPU INSTRUCTION SET DETAILS BC0FL 31 26 25 Branch On Coprocessor 0 False Likely 21 20 16 15 BC0FL 0 COPz Note 0100XX 6 BC 01000 5 BCFL 00010 5 offset 16 Format: BC0FL offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. If the contents of coprocessor 0's condition line, as sampled during the previous instruction, is false, the target address is branched to with a delay of one instruction. If the conditional branch is not taken, the instruction in the branch delay slot is nullified. Because the condition line is sampled during the previous instruction, there must be at least one instruction between this instruction and a coprocessor instruction that changes the condition line. Operation: 32 T-1: T: condition <- not SR18 target <- (offset15) 14 2 || offset || 0 T+1: if condition then PC <- PC + target else NullifyCurrentInstruction endif 64 T-1: T: condition <- not SR18 target <- (offset15) 46 || offset || 0 2 T+1: if condition then PC <- PC + target else NullifyCurrentlnstruction endif Exceptions: Coprocessor unusable exception Note See the opcode table below, or 27.6 CPU INSTRUCTION OPCODE BIT ENCODING. Opcode Table: 31 BC0FL 0 30 1 29 0 28 0 27 0 26 0 25 0 24 1 23 0 22 0 21 0 20 0 19 0 18 0 17 1 16 0 0 Opcode Coprocessor number BC sub-opcode Branch condition 537 CHAPTER 27 CPU INSTRUCTION SET DETAILS BC0T 31 26 25 Branch On Coprocessor 0 True 21 20 16 15 BC0T 0 COPz Note 0100XX 6 BC 01000 5 BCT 00001 5 offset 16 Format: BC0T offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. If the coprocessor 0's condition signal (CpCond: Status register bit18 CH field) is true, then the program branches to the target address, with a delay of one instruction. Because the condition line is sampled during the previous instruction, there must be at least one instruction between this instruction and a coprocessor instruction that changes the condition line. Operation: 32 T-1: T: condition <- SR18 target <- (offset15) 14 2 || offset || 0 T+1: if condition then PC <- PC + target endif 64 T-1: T: condition <- SR18 target <- (offset15) 46 || offset || 0 2 T+1: if condition then PC <- PC + target endif Exceptions: Coprocessor unusable exception Note See the opcode table below, or 27.6 CPU INSTRUCTION OPCODE BIT ENCODING. Opcode Table: 31 BC0T 0 30 1 29 0 28 0 27 0 26 0 25 0 24 1 23 0 22 0 21 0 20 0 19 0 18 0 17 0 16 1 0 Opcode Coprocessor number BC sub-opcode Branch condition 538 CHAPTER 27 CPU INSTRUCTION SET DETAILS BC0TL 31 26 25 Branch On Coprocessor 0 True Likely 21 20 16 15 BC0TL 0 COPz Note 0100XX 6 BC 01000 5 BCTL 00011 5 offset 16 Format: BC0TL offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. If the contents of coprocessor 0's condition line, as sampled during the previous instruction, is true, the target address is branched to with a delay of one instruction. If the conditional branch is not taken, the instruction in the branch delay slot is nullified. Because the condition line is sampled during the previous instruction, there must be at least one instruction between this instruction and a coprocessor instruction that changes the condition line. Operation: 32 T-1: T: condition <- SR18 target <- (offset15) 14 2 || offset || 0 T+1: if condition then PC <- PC + target else NullifyCurrentInstruction endif 64 T-1: T: condition <- SR18 target <- (offset15) 46 || offset || 0 2 T+1: if condition then PC <- PC + target else NullifyCurrentInstruction endif Exceptions: Coprocessor unusable exception Note See the opcode table below, or 27.6 CPU INSTRUCTION OPCODE BIT ENCODING. Opcode Table: 31 BC0TL 0 30 1 29 0 28 0 27 0 26 0 25 0 24 1 23 0 22 0 21 0 20 0 19 0 18 0 17 1 16 1 0 Opcode Coprocessor number BC sub-opcode Branch condition 539 CHAPTER 27 CPU INSTRUCTION SET DETAILS BEQ 31 26 25 21 20 Branch On Equal 16 15 BEQ 0 BEQ 000100 6 rs 5 rt 5 offset 16 Format: BEQ rs, rt, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. The contents of general register rs and the contents of general register rt are compared. If the two registers are equal, then the program branches to the target address, with a delay of one instruction. Operation: 32 T: target <- (offset15) 14 || offset || 0 2 condition <- (GPR [rs] = GPR [rt]) T+1: if condition then PC <- PC + target endif 64 T: target <- (offset15) 46 || offset || 0 2 condition <- (GPR [rs] = GPR [rt]) T+1: if condition then PC <- PC + target endif Exceptions: None 540 CHAPTER 27 CPU INSTRUCTION SET DETAILS BEQL 31 26 25 Branch On Equal Likely 21 20 16 15 BEQL 0 BEQL 010100 6 rs 5 rt 5 offset 16 Format: BEQL rs, rt, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. The contents of general register rs and the contents of general register rt are compared. If the two registers are equal, the target address is branched to, with a delay of one instruction. If the conditional branch is not taken, the instruction in the branch delay slot is nullified. Operation: 32 T: target <- (offset15) 14 || offset || 0 2 condition <- (GPR [rs] = GPR [rt]) T+1: if condition then PC <- PC + target else NullifyCurrentInstruction endif 64 T: target <- (offset15) 46 || offset || 0 2 condition <- (GPR [rs] = GPR [rt]) T+1: if condition then PC <- PC + target else NullifyCurrentInstruction endif Exceptions: None 541 CHAPTER 27 CPU INSTRUCTION SET DETAILS BGEZ 31 Branch On Greater Than Or Equal To Zero 26 25 21 20 16 15 BGEZ 0 REGIMM 000001 6 rs 5 BGEZ 00001 5 offset 16 Format: BGEZ rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. If the contents of general register rs have the sign bit cleared, then the program branches to the target address, with a delay of one instruction. Operation: 32 T: target <- (offset15) 14 || offset || 0 2 condition <- (GPR [rs]31 = 0) T+1: if condition then PC <- PC + target endif 64 T: target <- (offset15) 46 || offset || 0 2 condition <- (GPR [rs]63 = 0) T+1: if condition then PC <- PC + target endif Exceptions: None 542 CHAPTER 27 CPU INSTRUCTION SET DETAILS BGEZAL 31 Branch On Greater Than Or Equal To Zero And Link 21 20 16 15 BGEZAL 0 26 25 REGIMM 000001 6 rs 5 BGEZAL 10001 5 offset 16 Format: BGEZAL rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. Unconditionally, the address of the instruction after the delay slot is placed in the link register, r31. If the contents of general register rs have the sign bit cleared, then the program branches to the target address, with a delay of one instruction. General register rs may not be general register r31, because such an instruction is not restartable. An attempt to execute this instruction is not trapped, however. Operation: 32 T: target <- (offset15) 14 || offset || 0 2 condition <- (GPR [rs]31 = 0) GPR [31] <- PC + 8 T+1: if condition then PC <- PC + target endif 64 T: target <- (offset15) 46 || offset || 0 2 condition <- (GPR [rs]63 = 0) GPR [31] <- PC + 8 T+1: if condition then PC <- PC + target endif Exceptions: None 543 CHAPTER 27 CPU INSTRUCTION SET DETAILS BGEZALL 31 Branch On Greater Than Or Equal To Zero And Link Likely 21 20 16 15 BGEZALL 0 26 25 REGIMM 000001 6 rs 5 BGEZALL 10011 5 offset 16 Format: BGEZALL rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. Unconditionally, the address of the instruction after the delay slot is placed in the link register, r31. If the contents of general register rs have the sign bit cleared, then the program branches to the target address, with a delay of one instruction. General register rs may not be general register 31, because such an instruction is not restartable. An attempt to execute this instruction is not trapped, however. If the conditional branch is not taken, the instruction in the branch delay slot is nullified. Operation: 32 T: target <- (offset15) 14 || offset || 0 2 condition <- (GPR [rs]31 = 0) GPR [31] <- PC + 8 T+1: if condition then PC <- PC + target else NullifyCurrentInstruction endif 64 T: target <- (offset15) 46 || offset || 0 2 condition <- (GPR [rs]63 = 0) GPR [31] <- PC + 8 T+1: if condition then PC <- PC + target else NullifyCurrentInstruction endif Exceptions: None 544 CHAPTER 27 CPU INSTRUCTION SET DETAILS BGEZL 31 Branch On Greater Than Or Equal To Zero Likely BGEZL 26 25 21 20 16 15 0 REGIMM 000001 6 rs 5 BGEZL 00011 5 offset 16 Format: BGEZL rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. If the contents of general register rs have the sign bit cleared, then the program branches to the target address, with a delay of one instruction. If the conditional branch is not taken, the instruction in the branch delay slot is nullified. Operation: 32 T: target <- (offset15) 14 || offset || 0 2 condition <- (GPR [rs]31 = 0) T+1: if condition then PC <- PC + target else NullifyCurrentInstruction endif 64 T: target <- (offset15) 46 || offset || 0 2 condition <- (GPR [rs]63 = 0) T+1: if condition then PC <- PC + target else NullifyCurrentInstruction endif Exceptions: None 545 CHAPTER 27 CPU INSTRUCTION SET DETAILS BGTZ 31 26 25 Branch On Greater Than Zero 21 20 16 15 BGTZ 0 BGTZ 000111 6 rs 5 0 00000 5 offset 16 Format: BGTZ rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. The contents of general register rs are compared to zero. If the contents of general register rs have the sign bit cleared and are not equal to zero, then the program branches to the target address, with a delay of one instruction. Operation: 32 T: target <- (offset15) 14 || offset || 0 2 32 condition <- (GPR [rs]31 = 0) and (GPR [rs] z 0 ) T+1: if condition then PC <- PC + target endif 64 T: target <- (offset15) 46 || offset || 0 2 64 condition <- (GPR [rs]63 = 0) and (GPR [rs] z 0 ) T+1: if condition then PC <- PC + target endif Exceptions: None 546 CHAPTER 27 CPU INSTRUCTION SET DETAILS BGTZL 31 26 25 Branch On Greater Than Zero Likely 21 20 16 15 BGTZL 0 BGTZL 010111 6 rs 5 0 00000 5 offset 16 Format: BGTZL rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. The contents of general register rs are compared to zero. If the contents of general register rs have the sign bit cleared and are not equal to zero, then the program branches to the target address, with a delay of one instruction. If the conditional branch is not taken, the instruction in the branch delay slot is nullified. Operation: 32 T: target <- (offset15) 14 || offset || 0 2 32 condition <- (GPR [rs]31 = 0) and (GPR [rs] z 0 ) T+1: if condition then PC <- PC + target else NullifyCurrentInstruction endif 64 T: target <- (offset15) 46 || offset || 0 2 64 condition <- (GPR [rs]63 = 0) and (GPR [rs] z 0 ) T+1: if condition then PC <- PC + target else NullifyCurrentInstruction endif Exceptions: None 547 CHAPTER 27 CPU INSTRUCTION SET DETAILS BLEZ 31 26 25 Branch On Less Than Or Equal To Zero 21 20 16 15 BLEZ 0 BLEZ 000110 6 rs 5 0 00000 5 offset 16 Format: BLEZ rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. The contents of general register rs are compared to zero. If the contents of general register rs have the sign bit set, or are equal to zero, then the program branches to the target address, with a delay of one instruction. Operation: 32 T: target <- (offset15) 14 || offset || 0 2 32 condition <- (GPR [rs]31 = 1) or (GPR [rs] = 0 ) T+1: if condition then PC <- PC + target endif 64 T: target <- (offset15) 46 || offset || 0 2 64 condition <- (GPR [rs]63 = 1) or (GPR [rs] = 0 ) T+1: if condition then PC <- PC + target endif Exceptions: None 548 CHAPTER 27 CPU INSTRUCTION SET DETAILS BLEZL 31 Branch On Less Than Or Equal To Zero Likely 26 25 21 20 16 15 BLEZL 0 BLEZL 010110 6 rs 5 0 00000 5 offset 16 Format: BLEZL rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. The contents of general register rs is compared to zero. If the contents of general register rs have the sign bit set, or are equal to zero, then the program branches to the target address, with a delay of one instruction. If the conditional branch is not taken, the instruction in the branch delay slot is nullified. Operation: 32 T: target <- (offset15) 14 || offset || 0 2 32 condition <- (GPR [rs]31 = 1) or (GPR [rs] = 0 ) T+1: if condition then PC <- PC + target else NullifyCurrentInstruction endif 64 T: target <- (offset15) 46 || offset || 0 2 64 condition <- (GPR [rs]63 = 1) or (GPR [rs] = 0 ) T+1: if condition then PC <- PC + target else NullifyCurrentInstruction endif Exceptions: None 549 CHAPTER 27 CPU INSTRUCTION SET DETAILS BLTZ 31 26 25 Branch On Less Than Zero 21 20 16 15 BLTZ 0 REGIMM 000001 6 rs 5 BLTZ 00000 5 offset 16 Format: BLTZ rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. If the contents of general register rs have the sign bit set, then the program branches to the target address, with a delay of one instruction. Operation: 32 T: target <- (offset15) 14 || offset || 0 2 condition <- (GPR [rs]31 = 1) T+1: if condition then PC <- PC + target endif 64 T: target <- (offset15) 46 || offset || 0 2 condition <- (GPR [rs]63 = 1) T+1: if condition then PC <- PC + target endif Exceptions: None 550 CHAPTER 27 CPU INSTRUCTION SET DETAILS BLTZAL 31 26 25 Branch On Less Than Zero And Link 21 20 16 15 BLTZAL 0 REGIMM 000001 6 rs 5 BLTZAL 10000 5 offset 16 Format: BLTZAL rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. Unconditionally, the address of the instruction after the delay slot is placed in the link register, r31. If the contents of general register rs have the sign bit set, then the program branches to the target address, with a delay of one instruction. General register rs may not be general register 31, because such an instruction is not restartable. An attempt to execute this instruction with register 31 specified as rs is not trapped, however. Operation: 32 T: target <- (offset15) 14 || offset || 0 2 condition <- (GPR [rs]31 = 1) GPR [31] <- PC + 8 T+1: if condition then PC <- PC + target endif 64 T: target <- (offset15) 46 || offset || 0 2 condition <- (GPR [rs]63 = 1) GPR [31] <- PC + 8 T+1: if condition then PC <- PC + target endif Exceptions: None 551 CHAPTER 27 CPU INSTRUCTION SET DETAILS BLTZALL 31 26 25 Branch On Less Than Zero And Link Likely 21 20 16 15 BLTZALL 0 REGIMM 000001 6 rs 5 BLTZALL 10010 5 offset 16 Format: BLTZALL rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. Unconditionally, the address of the instruction after the delay slot is placed in the link register, r31. If the contents of general register rs have the sign bit set, then the program branches to the target address, with a delay of one instruction. General register rs may not be general register 31, because such an instruction is not restartable. An attempt to execute this instruction with register 31 specified as rs is not trapped, however. If the conditional branch is not taken, the instruction in the branch delay slot is nullified. Operation: 32 T: target <- (offset15) 14 || offset || 0 2 condition <- (GPR [rs]31 = 1) GPR [31] <- PC + 8 T+1: if condition then PC <- PC + target else NullifyCurrentInstruction endif 64 T: target <- (offset15) 46 || offset || 0 2 condition <- (GPR [rs]63 = 1) GPR [31] <- PC + 8 T+1: if condition then PC <- PC + target else NullifyCurrentInstruction endif Exceptions: None 552 CHAPTER 27 CPU INSTRUCTION SET DETAILS BLTZL 31 26 25 Branch On Less Than Zero Likely 21 20 16 15 BLTZL 0 REGIMM 000001 6 rs 5 BLTZL 00010 5 offset 16 Format: BLTZ rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. If the contents of general register rs have the sign bit set, then the program branches to the target address, with a delay of one instruction. If the conditional branch is not taken, the instruction in the branch delay slot is nullified. Operation: 32 T: target <- (offset15) 14 || offset || 0 2 condition <- (GPR [rs]31 = 1) T+1: if condition then PC <- PC + target else NullifyCurrentInstruction endif 64 T: target <- (offset15) 46 || offset || 0 2 condition <- (GPR [rs]63 = 1) T+1: if condition then PC <- PC + target else NullifyCurrentInstruction endif Exceptions: None 553 CHAPTER 27 CPU INSTRUCTION SET DETAILS BNE 31 26 25 Branch On Not Equal 21 20 16 15 BNE 0 BNE 000101 6 rs 5 rt 5 offset 16 Format: BNE rs, rt, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. The contents of general register rs and the contents of general register rt are compared. If the two registers are not equal, then the program branches to the target address, with a delay of one instruction. Operation: 32 T: target <- (offset15) 14 || offset || 0 2 condition <- (GPR [rs] z GPR [rt]) T+1: if condition then PC <- PC + target endif 64 T: target <- (offset15) 46 || offset || 0 2 condition <- (GPR [rs] z GPR [rt]) T+1: if condition then PC <- PC + target endif Exceptions: None 554 CHAPTER 27 CPU INSTRUCTION SET DETAILS BNEL 31 26 25 Branch On Not Equal Likely 21 20 16 15 BNEL 0 BNEL 010101 6 rs 5 rt 5 offset 16 Format: BNEL rs, rt, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. The contents of general register rs and the contents of general register rt are compared. If the two registers are not equal, then the program branches to the target address, with a delay of one instruction. If the conditional branch is not taken, the instruction in the branch delay slot is nullified. Operation: 32 T: target <- (offset15) 14 || offset || 0 2 condition <- (GPR [rs] z GPR [rt]) T+1: if condition then PC <- PC + target else NullifyCurrentInstruction endif 64 T: target <- (offset15) 46 || offset || 0 2 condition <- (GPR [rs] z GPR [rt]) T+1: if condition then PC <- PC + target else NullifyCurrentInstruction endif Exceptions: None 555 CHAPTER 27 CPU INSTRUCTION SET DETAILS BREAK 31 26 25 Breakpoint 65 BREAK 0 SPECIAL 000000 6 code 20 BREAK 001101 6 Format: BREAK Description: A breakpoint trap occurs, immediately and unconditionally transferring control to the exception handler. The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. Operation: 32,64 T: BreakpointException Exceptions: Breakpoint exception 556 CHAPTER 27 CPU INSTRUCTION SET DETAILS CACHE 31 26 25 21 20 Cache 16 15 CACHE 0 CACHE 101111 6 base 5 op 5 offset 16 Format: CACHE op, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The virtual address is translated to a physical address using the TLB, and the 5-bit sub-opcode specifies a cache operation for that address. If CP0 is not usable (User or Supervisor mode) and the CP0 enable bit in the Status register is clear, a coprocessor unusable exception is taken. The operation of this instruction on any operation/cache combination not listed below, or on a secondary cache, is undefined. The operation of this instruction on uncached addresses is also undefined. The Index operation uses part of the virtual address to specify a cache block. For a primary cache of 2 CACHEBITS bytes with 2 LINEBITS bytes per tag, vAddrCACHEBITS...LINEBITS specifies the block. Index Load Tag also uses vAddrLINEBITS...3 to select the doubleword for reading parity. When the CE bit of the Status register is set, Fill Cache op uses the PErr register to store parity values into the cache. The Hit operation accesses the specified cache as normal data references, and performs the specified operation if the cache block contains valid data with the specified physical address (a hit). If the cache block is invalid or contains a different address (a miss), no operation is performed. 557 CHAPTER 27 CPU INSTRUCTION SET DETAILS CACHE Cache (Continued) CACHE Write back from a primary cache goes to memory. The address to be written is specified by the cache tag and not the translated physical address. TLB Refill and TLB Invalid exceptions can occur on any operation. For Index operations (where the physical address is used to index the cache but need not match the cache tag) unmapped addresses may be used to avoid TLB exceptions. This operation never causes a TLB Modified exception. Bits 17...16 of the instruction specify the cache as follows: Code 0 1 2, 3 Name I D NA Cache Primary instruction Primary data Reserved (undefined) 558 CHAPTER 27 CPU INSTRUCTION SET DETAILS CACHE Cache (Continued) CACHE Bits 20...18 (this value is listed under the Code column) of the instruction specify the operation as follows: Code 0 0 Cache I D Name Index_Invalidate Index_Write_Back Invalidate Operation Set the cache state of the cache block to Invalid. Examine the cache state and W bit of the primary data cache block at the index specified by the virtual address. If the state is not Invalid and the W bit is set, then write back the block to memory. The address to write is taken from the primary cache tag. Set cache state of primary cache block to Invalid. Read the tag for the cache block at the specified index and place it into the TagLo CP0 registers, ignoring parity errors. Also load the data parity bits into the ECC register. Write the tag for the cache block at the specified index from the TagLo and TagHi CP0 registers. This operation is used to avoid loading data needlessly from memory when writing new contents into an entire cache block. If the cache block does not contain the specified address, and the block is dirty, write it back to the memory. In all cases, set the cache state to Dirty. If the cache block contains the specified address, mark the cache block invalid. If the cache block contains the specified address, write back the data if it is dirty, and mark the cache block invalid. Fill the primary instruction cache block from memory. If the CE bit of the Status register is set, the contents of the ECC register is used instead of the computed parity bits for addressed doubleword when written to the instruction cache. If the cache block contains the specified address and the W bit is set, write back the data to memory and clear the W bit. If the cache block contains the specified address, write back the data unconditionally. 1 I, D Index_Load_Tag 2 3 I, D D Index_Store_Tag Create_Dirty_ Exclusive 4 5 5 I, D D I Hit_Invalidate Hit_Write_Back Invalidate Fill 6 6 D I Hit_Write_Back Hit_Write_Back 559 CHAPTER 27 CPU INSTRUCTION SET DETAILS CACHE Operation: 32, 64 T: vAddr <- ((offset15) 48 Cache (Continued) CACHE || offset15...0) + GPR [base] (pAddr, uncached) <- AddressTranslation (vAddr, DATA) CacheOp (op, vAddr, pAddr) Exceptions: Coprocessor unusable exception TLB Refill exception TLB Invalid exception Bus Error exception Address Error exception Cache Error exception 560 CHAPTER 27 CPU INSTRUCTION SET DETAILS DADD 31 26 25 21 20 Doubleword Add 16 15 11 10 65 DADD 0 SPECIAL 000000 6 rs 5 rt 5 rd 5 0 00000 5 DADD 101100 6 Format: DADD rd, rs, rt Description: The contents of general register rs and the contents of general register rt are added to form the result. The result is placed into general register rd. An overflow exception occurs if the carries out of bits 62 and 63 differ (2's complement overflow). The destination register rd is not modified when an integer overflow exception occurs. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: GPR [rd] <- GPR [rs] + GPR [rt] Exceptions: Integer overflow exception Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 561 CHAPTER 27 CPU INSTRUCTION SET DETAILS DADDI 31 26 25 Doubleword Add Immediate 21 20 16 15 DADDI 0 DADDI 011000 6 rs 5 rt 5 immediate 16 Format: DADDI rt, rs, immediate Description: The 16-bit immediate is sign-extended and added to the contents of general register rs to form the result. The result is placed into general register rt. An overflow exception occurs if carries out of bits 62 and 63 differ (2's complement overflow). The destination register rt is not modified when an integer overflow exception occurs. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: GPR [rt] <- GPR [rs] + (immediate15) 48 || immediate15...0 Exceptions: Integer overflow exception Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 562 CHAPTER 27 CPU INSTRUCTION SET DETAILS DADDIU 31 26 25 Doubleword Add Immediate Unsigned 21 20 16 15 DADDIU 0 DADDIU 011001 6 rs 5 rt 5 immediate 16 Format: DADDIU rt, rs, immediate Description: The 16-bit immediate is sign-extended and added to the contents of general register rs to form the result. The result is placed into general register rt. No integer overflow exception occurs under any circumstances. The only difference between this instruction and the DADDI instruction is that DADDIU never causes an overflow exception. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: GPR [rt] <- GPR [rs] + (immediate15) 48 || immediate15...0 Exceptions: Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 563 CHAPTER 27 CPU INSTRUCTION SET DETAILS DADDU 31 26 25 Doubleword Add Unsigned 21 20 16 15 11 10 65 DADDU 0 SPECIAL 000000 6 rs 5 rt 5 rd 5 0 00000 5 DADDU 101101 6 Format: DADDU rd, rs, rt Description: The contents of general register rs and the contents of general register rt are added to form the result. The result is placed into general register rd. No overflow exception occurs under any circumstances. The only difference between this instruction and the DADD instruction is that DADDU never causes an overflow exception. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: GPR [rd] <- GPR [rs] + GPR [rt] Exceptions: Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 564 CHAPTER 27 CPU INSTRUCTION SET DETAILS DDIV 31 26 25 Doubleword Divide 21 20 16 15 65 DDIV 0 SPECIAL 000000 6 rs 5 rt 5 00 0 0000 10 0000 DDIV 011110 6 Format: DDIV rs, rt Description: The contents of general register rs are divided by the contents of general register rt, treating both operands as 2's complement values. No overflow exception occurs under any circumstances, and the result of this operation is undefined when the divisor is zero. This instruction is typically followed by additional instructions to check for a zero divisor and for overflow. When the operation completes, the quotient word of the double result is loaded into special register LO, and the remainder word of the double result is loaded into special register HI. If either of the two preceding instructions is MFHI or MFLO, the results of those instructions are undefined. Correct operation requires separating reads of HI or LO from writes by two or more instructions. This is defined in this manner to take account of the VR4000TM hazards (for code compatibility) as well as the VR4100's own hazards. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T-2: T-1: T: LO HI LO HI LO HI <- undefined <- undefined <- undefined <- undefined <- GPR [rs] div GPR [rt] <- GPR [rs] mod GPR [rt] Exceptions: Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 565 CHAPTER 27 CPU INSTRUCTION SET DETAILS DDIVU 31 26 25 Doubleword Divide Unsigned 21 20 16 15 65 DDIVU 0 SPECIAL 000000 6 rs 5 rt 5 0 00 0000 0000 10 DDIVU 011111 6 Format: DDIVU rs, rt Description: The contents of general register rs are divided by the contents of general register rt, treating both operands as unsigned values. No integer overflow exception occurs under any circumstances, and the result of this operation is undefined when the divisor is zero. This instruction may be followed by additional instructions to check for a zero divisor, inserted by the programmer. When the operation completes, the quotient word of the double result is loaded into special register LO, and the remainder word of the double result is loaded into special register HI. If either of the two preceding instructions is MFHI or MFLO, the results of those instructions are undefined. Correct operation requires separating reads of HI or LO from writes by two or more instructions. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T-2: T-1: T: LO HI LO HI LO HI <- undefined <- undefined <- undefined <- undefined <- (0 || GPR [rs]) div (0 || GPR [rt]) <- (0 || GPR [rs]) mod (0 || GPR [rt]) Exceptions: Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 566 CHAPTER 27 CPU INSTRUCTION SET DETAILS DIV 31 26 25 21 20 Divide 16 15 65 DIV 0 SPECIAL 000000 6 rs 5 rt 5 00 0 0000 10 0000 DIV 011010 6 Format: DIV rs, rt Description: The contents of general register rs are divided by the contents of general register rt, treating both operands as 2's complement values. No overflow exception occurs under any circumstances, and the result of this operation is undefined when the divisor is zero. In 64-bit mode, the operands must be valid sign-extended, 32-bit values. This instruction is typically followed by additional instructions to check for a zero divisor and for overflow. When the operation completes, the quotient word of the double result is loaded into special register LO, and the remainder word of the double result is loaded into special register HI. If either of the two preceding instructions is MFHI or MFLO, the results of those instructions are undefined. Correct operation requires separating reads of HI or LO from writes by two or more instructions. Operation: 32 T-2: T-1: T: LO HI LO HI LO HI 64 T-2: T-1: T: LO HI LO HI q r LO HI <- undefined <- undefined <- undefined <- undefined <- GPR [rs] div GPR [rt] <- GPR [rs] mod GPR [rt] <- undefined <- undefined <- undefined <- undefined <- GPR [rs]31..0 div GPR [rt]31..0 <- GPR [rs]31..0 mod GPR [rt]31..0 <- (q31) <- (r31) 32 || q31..0 || r31..0 32 Exceptions: None 567 CHAPTER 27 CPU INSTRUCTION SET DETAILS DIVU 31 26 25 21 20 Divide Unsigned 16 15 65 DIVU 0 SPECIAL 000000 6 rs 5 rt 5 0 00 0000 0000 10 DIVU 011011 6 Format: DIVU rs, rt Description: The contents of general register rs are divided by the contents of general register rt, treating both operands as unsigned values. No integer overflow exception occurs under any circumstances, and the result of this operation is undefined when the divisor is zero. In 64-bit mode, the operands must be valid sign-extended, 32-bit values. This instruction is typically followed by additional instructions to check for a zero divisor. When the operation completes, the quotient word of the double result is loaded into special register LO, and the remainder word of the double result is loaded into special register HI. If either of the two preceding instructions is MFHI or MFLO, the results of those instructions are undefined. Correct operation requires separating reads of HI or LO from writes by two or more instructions. Operation: 32 T-2: T-1: T: LO HI LO HI LO HI 64 T-2: T-1: T: LO HI LO HI q r LO HI <- undefined <- undefined <- undefined <- undefined <- (0 || GPR [rs]) div (0 || GPR [rt]) <- (0 || GPR [rs]) mod (0 || GPR [rt]) <- undefined <- undefined <- undefined <- undefined <- (0 || GPR [rs]31..0) div (0 || GPR [rt]31..0) <- (0 || GPR [rs]31..0) mod (0 || GPR [rt]31..0) <- (q31) <- (r31) 32 || q31..0 || r31..0 32 Exceptions: None 568 CHAPTER 27 CPU INSTRUCTION SET DETAILS DMADD16 31 26 25 Doubleword Multiply and Add 16-bit integer DMADD16 21 20 16 15 65 0 SPECIAL 000000 6 rs 5 rt 5 00 0 0000 10 0000 DMADD16 101001 6 Format: DMADD16 rs, rt Description: The contents of general registers rs and rt are multiplied, treating both operands as 16-bit 2's complement values. The operand[62:15] must be valid 15-bit, sign-extended values. If not, the result is unpredictable. This multiplied result and the 64-bit data joined of special register LO is added to form the result as a signed integer. When the operation completes, the doubleword result is loaded into special register LO. No integer overflow exception occurs under any circumstances. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. The following table shows hazard cycles between DMADD16 and other instructions. Instruction sequence MULT/MULTU -> DMADD16 DMULT/DMULTU -> DMADD16 DIV/DIVU -> DMADD16 DDIV/DDIVU -> DMADD16 MFHI/MFLO -> DMADD16 MADD16 -> DMADD16 DMADD16 -> DMADD16 No. of cycles 1 Cycle 4 Cycles 36 Cycles 68 Cycles 2 Cycles 0 Cycles 0 Cycles 569 CHAPTER 27 CPU INSTRUCTION SET DETAILS DMADD16 Operation: 64 T-2: T-1: T: LO HI LO HI Doubleword Multiply and Add 16-bit integer DMADD16 (Continued) <- undefined <- undefined <- undefined <- undefined temp <- GPR [rs] * GPR [rt] temp <- temp + LO LO HI <- temp <- undefined Exceptions: Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 570 CHAPTER 27 CPU INSTRUCTION SET DETAILS DMFC0 31 Doubleword Move From System Control Coprocessor 26 25 21 20 16 15 11 10 DMFC0 0 COP0 010000 6 DMF 00001 5 rt 5 rd 5 000 0 0000 11 0000 Format: DMFC0 rt, rd Description: The contents of coprocessor register rd of the CP0 are loaded into general register rt. This operation is defined for the VR4102 operating in 64-bit mode and in 32-bit kernel mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. All 64-bits of the general register destination are written from the coprocessor register source. The operation of DMFC0 on a 32-bit coprocessor 0 register is undefined. Operation: 64 T: data <- CPR [0, rd] T+1: GPR [rt] <- data Exceptions: Coprocessor unusable exception (user mode and supervisor mode if CP0 not enabled) Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 571 CHAPTER 27 CPU INSTRUCTION SET DETAILS DMTC0 31 Doubleword Move To System Control Coprocessor 26 25 21 20 16 15 11 10 DMTC0 0 COP0 010000 6 DMT 00101 5 rt 5 rd 5 000 0 0000 11 0000 Format: DMTC0 rt, rd Description: The contents of general register rt are loaded into coprocessor register rd of the CP0. This operation is defined for the VR4102 operating in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. All 64-bits of the coprocessor 0 register are written from the general register source. The operation of DMTC0 on a 32-bit coprocessor 0 register is undefined. Because the state of the virtual address translation system may be altered by this instruction, the operation of load instructions, store instructions, and TLB operations immediately prior to and after this instruction are undefined. Operation: 64 T: data <- GPR [rt] T+1: CPR [0, rd] <- data Exceptions: Coprocessor unusable exception (In user and supervisor mode if CP0 not enabled) Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 572 CHAPTER 27 CPU INSTRUCTION SET DETAILS DMULT 31 26 25 Doubleword Multiply 21 20 16 15 65 DMULT 0 SPECIAL 000000 6 rs 5 rt 5 00 0 0000 10 0000 DMULT 011100 6 Format: DMULT rs, rt Description: The contents of general registers rs and rt are multiplied, treating both operands as 2's complement values. No integer overflow exception occurs under any circumstances. When the operation completes, the low-order word of the double result is loaded into special register LO, and the high-order word of the double result is loaded into special register HI. If either of the two preceding instructions is MFHI or MFLO, the results of these instructions are undefined. Correct operation requires separating reads of HI or LO from writes by a minimum of two other instructions. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T-2: T-1: T: LO HI LO HI t LO HI <- undefined <- undefined <- undefined <- undefined <- GPR [rs] * GPR [rt] <- t63..0 <- t127..64 Exceptions: Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 573 CHAPTER 27 CPU INSTRUCTION SET DETAILS DMULTU 31 26 25 Doubleword Multiply Unsigned 21 20 16 15 65 DMULTU 0 SPECIAL 000000 6 rs 5 rt 5 00 0 0000 10 0000 DMULTU 011101 6 Format: DMULTU rs, rt Description: The contents of general register rs and the contents of general register rt are multiplied, treating both operands as unsigned values. No overflow exception occurs under any circumstances. When the operation completes, the low-order word of the double result is loaded into special register LO, and the high-order word of the double result is loaded into special register HI. If either of the two preceding instructions is MFHI or MFLO, the results of these instructions are undefined. Correct operation requires separating reads of HI or LO from writes by a minimum of two instructions. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T-2: T-1: T: LO HI LO HI t LO HI <- undefined <- undefined <- undefined <- undefined <- (0 || GPR [rs]) * (0 || GPR [rt]) <- t63..0 <- t127..64 Exceptions: Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 574 CHAPTER 27 CPU INSTRUCTION SET DETAILS DSLL 31 26 25 Doubleword Shift Left Logical 21 20 16 15 11 10 65 DSLL 0 SPECIAL 000000 6 0 00000 5 rt 5 rd 5 sa 5 DSLL 111000 6 Format: DSLL rd, rt, sa Description: The contents of general register rt are shifted left by sa bits, inserting zeros into the low-order bits. The result is placed in register rd. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: s <- 0 || sa GPR [rd] <- GPR [rt](63 - s)..0 || 0 s Exceptions: Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 575 CHAPTER 27 CPU INSTRUCTION SET DETAILS DSLLV 31 26 25 Doubleword Shift Left Logical Variable 21 20 16 15 11 10 65 DSLLV 0 SPECIAL 000000 6 rs 5 rt 5 rd 5 0 00000 5 DSLLV 010100 6 Format: DSLLV rd, rt, rs Description: The contents of general register rt are shifted left by the number of bits specified by the low-order six bits contained in general register rs, inserting zeros into the low-order bits. The result is placed in register rd. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: s <- GPR [rs]5..0 GPR [rd] <- GPR [rt](63 - s)..0 || 0 s Exceptions: Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 576 CHAPTER 27 CPU INSTRUCTION SET DETAILS DSLL32 31 26 25 Doubleword Shift Left Logical + 32 21 20 16 15 11 10 65 DSLL32 0 SPECIAL 000000 6 0 00000 5 rt 5 rd 5 sa 5 DSLL32 111100 6 Format: DSLL32 rd, rt, sa Description: The contents of general register rt are shifted left by 32 + sa bits, inserting zeros into the low-order bits. The result is placed in register rd. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: s <- 1 || sa GPR [rd] <- GPR [rt](63 - s)..0 || 0 s Exceptions: Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 577 CHAPTER 27 CPU INSTRUCTION SET DETAILS DSRA 31 26 25 Doubleword Shift Right Arithmetic 21 20 16 15 11 10 65 DSRA 0 SPECIAL 000000 6 0 00000 5 rt 5 rd 5 sa 5 DSRA 111011 6 Format: DSRA rd, rt, sa Description: The contents of general register rt are shifted right by sa bits, sign-extending the high-order bits. The result is placed in register rd. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: s <- 0 || sa GPR [rd] <- (GPR [rt]63) || GPR [rt] 63..s s Exceptions: Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 578 CHAPTER 27 CPU INSTRUCTION SET DETAILS DSRAV 31 Doubleword Shift Right Arithmetic Variable 26 25 21 20 16 15 11 10 65 DSRAV 0 SPECIAL 000000 6 rs 5 rt 5 rd 5 0 00000 5 DSRAV 010111 6 Format: DSRAV rd, rt, rs Description: The contents of general register rt are shifted right by the number of bits specified by the low-order six bits of general register rs, sign-extending the high-order bits. The result is placed in register rd. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: s <- GPR [rs]5..0 GPR [rd] <- (GPR [rt]63) || GPR [rt] 63..s s Exceptions: Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 579 CHAPTER 27 CPU INSTRUCTION SET DETAILS DSRA32 31 26 25 Doubleword Shift Right Arithmetic + 32 21 20 16 15 11 10 65 DSRA32 0 SPECIAL 000000 6 0 00000 5 rt 5 rd 5 sa 5 DSRA32 111111 6 Format: DSRA32 rd, rt, sa Description: The contents of general register rt are shifted right by 32 + sa bits, sign-extending the high-order bits. The result is placed in register rd. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: s <- 1 || sa GPR [rd] <- (GPR [rt]63) || GPR [rt]63..s s Exceptions: Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 580 CHAPTER 27 CPU INSTRUCTION SET DETAILS DSRL 31 26 25 Doubleword Shift Right Logical 21 20 16 15 11 10 65 DSRL 0 SPECIAL 000000 6 0 00000 5 rt 5 rd 5 sa 5 DSRL 111010 6 Format: DSRL rd, rt, sa Description: The contents of general register rt are shifted right by sa bits, inserting zeros into the high-order bits. The result is placed in register rd. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: s <- 0 || sa GPR [rd] <- 0 || GPR [rt]63..s s Exceptions: Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 581 CHAPTER 27 CPU INSTRUCTION SET DETAILS DSRLV 31 26 25 Doubleword Shift Right Logical Variable 21 20 16 15 11 10 65 DSRLV 0 SPECIAL 000000 6 rs 5 rt 5 rd 5 0 00000 5 DSRLV 010110 6 Format: DSRLV rd, rt, rs Description: The contents of general register rt are shifted right by the number of bits specified by the low-order six bits of general register rs, inserting zeros into the high-order bits. The result is placed in register rd. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: s <- GPR [rs]5..0 GPR [rd] <- 0 || GPR [rt]63..s s Exceptions: Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 582 CHAPTER 27 CPU INSTRUCTION SET DETAILS DSRL32 31 26 25 Doubleword Shift Right Logical + 32 21 20 16 15 11 10 65 DSRL32 0 SPECIAL 000000 6 0 00000 5 rt 5 rd 5 sa 5 DSRL32 111110 6 Format: DSRL32 rd, rt, sa Description: The contents of general register rt are shifted right by 32 + sa bits, inserting zeros into the high-order bits. The result is placed in register rd. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: s <- 1 || sa GPR [rd] <- 0 || GPR [rt]63..s s Exceptions: Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 583 CHAPTER 27 CPU INSTRUCTION SET DETAILS DSUB 31 26 25 Doubleword Subtract 21 20 16 15 11 10 65 DSUB 0 SPECIAL 000000 6 rs 5 rt 5 rd 5 0 00000 5 DSUB 101110 6 Format: DSUB rd, rs, rt Description: The contents of general register rt are subtracted from the contents of general register rs to form a result. The result is placed into general register rd. The only difference between this instruction and the DSUBU instruction is that DSUBU never traps on overflow. An integer overflow exception takes place if the carries out of bits 62 and 63 differ (2's complement overflow). The destination register rd is not modified when an integer overflow exception occurs. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: GPR [rd] <- GPR [rs] - GPR [rt] Exceptions: Integer overflow exception Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 584 CHAPTER 27 CPU INSTRUCTION SET DETAILS DSUBU 31 26 25 Doubleword Subtract Unsigned 21 20 16 15 11 10 65 DSUBU 0 SPECIAL 000000 6 rs 5 rt 5 rd 5 0 00000 5 DSUBU 101111 6 Format: DSUBU rd, rs, rt Description: The contents of general register rt are subtracted from the contents of general register rs to form a result. The result is placed into general register rd. The only difference between this instruction and the DSUB instruction is that DSUBU never traps on overflow. No integer overflow exception occurs under any circumstances. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: GPR [rd] <- GPR [rs] - GPR [rt] Exceptions: Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 585 CHAPTER 27 CPU INSTRUCTION SET DETAILS ERET 31 26 25 24 Exception Return 65 CO 1 ERET 0 COP0 010000 6 000 0000 0 0000 19 0000 0000 ERET 011000 6 1 Format: ERET Description: ERET is the VR4102 instruction for returning from an interrupt, exception, or error trap. Unlike a branch or jump instruction, ERET does not execute the next instruction. ERET must not itself be placed in a branch delay slot. If the processor is servicing an error trap (SR2 = 1), then load the PC from the ErrorEPC register and clear the ERL bit of the Status register (SR2). Otherwise (SR2 = 0), load the PC from the EPC register, and clear the EXL bit of the Status register (SR1). Operation: 32, 64 T: if SR2 = 1 then PC <- ErrorEPC SR <- SR31..3 || 0 || SR1..0 else PC <-EPC SR <- SR31..2 || 0 || SR0 endif Exceptions: Coprocessor unusable exception 586 CHAPTER 27 CPU INSTRUCTION SET DETAILS HIBERNATE 31 26 25 24 Hibernate 0 000 0000 0000 0000 0000 19 HIBERNATE 65 0 COP0 010000 6 CO 1 HIBERNATE 100011 6 1 Format: HIBERNATE Description: HIBERNATE instruction starts mode transition from Fullspeed mode to Hibernate mode. When the HIBERNATE instruction finishes the WB stage, the VR4102 wait by the SysAD bus is idle state, after then the internal clocks and the system interface clocks will shut down, thus freezing the pipeline. Once the VR4102 is in Hibernate mode, the Cold Reset sequence will cause the VR4102 to exit Hibernate mode and to enter Fullspeed mode. Operation: 32, 64 T: T+1: Hibernate operation () Exceptions: Coprocessor unusable exception Remark Refer to Chapter 15 for details about the operation of the peripheral units at mode transition. 587 CHAPTER 27 CPU INSTRUCTION SET DETAILS J 31 26 25 Jump J 000010 6 J 0 target 26 Format: J target Description: The 26-bit target address is shifted left two bits and combined with the high-order four bits of the address of the delay slot. The program unconditionally jumps to this calculated address with a delay of one instruction. Operation: 32 T: temp <- target 2 T+1: PC <- PC31..28 || temp || 0 64 T: temp <- target T+1: PC <- PC63..28 || temp || 0 2 Exceptions: None 588 CHAPTER 27 CPU INSTRUCTION SET DETAILS JAL 31 26 25 Jump And Link JAL 0 JAL 000011 6 target 26 Format: JAL target Description: The 26-bit target address is shifted left two bits and combined with the high-order four bits of the address of the delay slot. The program unconditionally jumps to this calculated address with a delay of one instruction. The address of the instruction after the delay slot is placed in the link register, r31. Operation: 32 T: temp <- target GPR [31] <- PC + 8 T+1: PC <- PC31..28 || temp || 0 64 T: temp <- target GPR [31] <- PC + 8 T+1: PC <- PC63..28 || temp || 0 2 2 Exceptions: None 589 CHAPTER 27 CPU INSTRUCTION SET DETAILS JALR 31 26 25 Jump And Link Register 21 20 16 15 11 10 65 JALR 0 SPECIAL 000000 6 rs 5 0 00000 5 rd 5 0 00000 5 JALR 001001 6 Format: JALR rs JALR rd, rs Description: The program unconditionally jumps to the address contained in general register rs, with a delay of one instruction. The address of the instruction after the delay slot is placed in general register rd. The default value of rd, if omitted in the assembly language instruction, is 31. Register specifiers rs and rd may not be equal, because such an instruction does not have the same effect when re-executed. However, an attempt to execute this instruction is not trapped, and the result of executing such an instruction is undefined. Since instructions must be word-aligned, a Jump and Link Register instruction must specify a target register (rs) which contains an address whose two low-order bits are zero. If these low-order bits are not zero, an address error exception will occur when the jump target instruction is subsequently fetched. Operation: 32,64 T: temp <- GPR [rs] GPR [rd] <- PC + 8 T+1: PC <- temp Exceptions: None 590 CHAPTER 27 CPU INSTRUCTION SET DETAILS JR 31 26 25 21 20 Jump Register 65 JR 0 SPECIAL 000000 6 rs 5 000 0000 0 0000 15 0000 JR 001000 6 Format: JR rs Description: The program unconditionally jumps to the address contained in general register rs, with a delay of one instruction. Since instructions must be word-aligned, a Jump Register instruction must specify a target register (rs) which contains an address whose two low-order bits are zero. If these low-order bits are not zero, an address error exception will occur when the jump target instruction is subsequently fetched. Operation: 32,64 T: temp <- GPR [rs] T+1: PC <- temp Exceptions: None 591 CHAPTER 27 CPU INSTRUCTION SET DETAILS LB 31 26 25 21 20 Load Byte 16 15 LB 0 LB 100000 6 base 5 rt 5 offset 16 Format: LB rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the byte at the memory location specified by the effective address are sign-extended and loaded into general register rt. Operation: 32 T: vAddr <- ((offset15) 16 || offset15..0) + GPR [base] 3 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1..3 || (pAddr2..0 xor ReverseEndian ) mem <- LoadMemory (uncached, BYTE, pAddr, vAddr, DATA) byte <- vAddr2..0 xor BigEndianCPU GPR [rt] <- (mem7 + 8* byte) 64 T: vAddr <- ((offset15) 48 24 3 || mem7 + 8* byte..8* byte || offset15..0) + GPR [base] 3 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1..3 || (pAddr2..0 xor ReverseEndian ) mem <- LoadMemory (uncached, BYTE, pAddr, vAddr, DATA) byte <- vAddr2..0 xor BigEndianCPU GPR [rt] <- (mem7 + 8* byte) 56 3 || mem7 + 8* byte..8* byte Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception 592 CHAPTER 27 CPU INSTRUCTION SET DETAILS LBU 31 26 25 Load Byte Unsigned 21 20 16 15 LBU 0 LBU 100100 6 base 5 rt 5 offset 16 Format: LBU rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the byte at the memory location specified by the effective address are zero-extended and loaded into general register rt. Operation: 32 T: vAddr <- ((offset15) 16 || offset15..0) + GPR [base] 3 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1..3 || (pAddr2..0 xor ReverseEndian ) mem <- LoadMemory (uncached, BYTE, pAddr, vAddr, DATA) byte <- vAddr2..0 xor BigEndianCPU GPR [rt] <- 0 64 T: 24 3 || mem7 + 8* byte..8* byte 48 vAddr <- ((offset15) || offset15..0) + GPR [base] 3 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1..3 || (pAddr2..0 xor ReverseEndian ) mem <- LoadMemory (uncached, BYTE, pAddr, vAddr, DATA) byte <- vAddr2..0 xor BigEndianCPU GPR [rt] <- 0 56 3 || mem7 + 8* byte..8* byte Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception 593 CHAPTER 27 CPU INSTRUCTION SET DETAILS LD 31 26 25 21 20 Load Doubleword 16 15 LD 0 LD 110111 6 base 5 rt 5 offset 16 Format: LD rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the 64-bit doubleword at the memory location specified by the effective address are loaded into general register rt. If any of the three least-significant bits of the effective address are non-zero, an address error exception occurs. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: vAddr <- ((offset15) 48 || offset15..0) + GPR [base] (pAddr, uncached) <- AddressTranslation (vAddr, DATA) data <- LoadMemory (uncached, DOUBLEWORD, pAddr, vAddr, DATA) GPR [rt] <- data Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 594 CHAPTER 27 CPU INSTRUCTION SET DETAILS LDL 31 26 25 Load Doubleword Left 21 20 16 15 LDL 0 LDL 011010 6 base 5 rt 5 offset 16 Format: LDL rt, offset (base) Description: This instruction can be used in combination with the LDR instruction to load a register with eight consecutive bytes from memory, when the bytes cross a doubleword boundary. LDL loads the left portion of the register with the appropriate part of the high-order doubleword; LDR loads the right portion of the register with the appropriate part of the low-order doubleword. The LDL instruction adds its sign-extended 16-bit offset to the contents of general register base to form a virtual address which can specify an arbitrary byte. It reads bytes only from the doubleword in memory which contains the specified starting byte. From one to eight bytes will be loaded, depending on the starting byte specified. Conceptually, it starts at the specified byte in memory and loads that byte into the high-order (left-most) byte of the register; then it loads bytes from memory into the register until it reaches the low-order byte of the doubleword in memory. The least-significant (right-most) byte(s) of the register will not be changed. memory address 8 address 0 15 14 13 12 11 10 7 6 5 4 3 2 9 1 8 0 register before A B C D E F G H $24 LDL $24, 12 ($0) after 12 11 10 9 8 F G H $24 595 CHAPTER 27 CPU INSTRUCTION SET DETAILS LDL Load Doubleword Left (Continued) LDL The contents of general register rt are internally bypassed within the processor so that no NOP is needed between an immediately preceding load instruction which specifies register rt and a following LDL (or LDR) instruction which also specifies register rt. No address error exceptions due to alignment are possible. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: vAddr <- ((offset15) 48 || offset15..0) + GPR [base] 3 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1..3 || (pAddr2..0 xor ReverseEndian ) if BigEndianMem = 0 then pAddr <- pAddrPSIZE - 1..3 || 0 endif byte <- vAddr2..0 xor BigEndianCPU 3 3 mem <- LoadMemory (uncached, byte, pAddr, vAddr, DATA) GPR [rt] <- mem7 + 8* byte..0 || GPR [rt]55 - 8* byte..0 596 CHAPTER 27 CPU INSTRUCTION SET DETAILS LDL Load Doubleword Left (Continued) LDL Given a doubleword in a register and a doubleword in memory, the operation of LDL is as follows: LDL Register Memory A I B J C K D L E M F N G O H P vAddr2..0 BigEndianCPU = 0 destination type offset (LEM) 0 1 2 3 4 5 6 7 P BCDE FGH OPCDE FGH NOPDE FGH MNO P E F G H L MNOP F GH K LMNOPGH J K LMNOP H I J K LMNOP 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 LEM Type Offset Little-endian memory (BigEndianMem = 0) AccessType (see Table 3-2) sent to memory pAddr2..0 sent to memory Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 597 CHAPTER 27 CPU INSTRUCTION SET DETAILS LDR 31 26 25 Load Doubleword Right 21 20 16 15 LDR 0 LDR 011011 6 base 5 rt 5 offset 16 Format: LDR rt, offset (base) Description: This instruction can be used in combination with the LDL instruction to load a register with eight consecutive bytes from memory, when the bytes cross a doubleword boundary. LDR loads the right portion of the register with the appropriate part of the low-order doubleword; LDL loads the left portion of the register with the appropriate part of the high-order doubleword. The LDR instruction adds its sign-extended 16-bit offset to the contents of general register base to form a virtual address which can specify an arbitrary byte. It reads bytes only from the doubleword in memory which contains the specified starting byte. From one to eight bytes will be loaded, depending on the starting byte specified. Conceptually, it starts at the specified byte in memory and loads that byte into the low-order (right-most) byte of the register; then it loads bytes from memory into the register until it reaches the high-order byte of the doubleword in memory. The most significant (left-most) byte(s) of the register will not be changed. memory address 8 address 0 15 14 13 12 11 10 7 6 5 4 3 2 9 1 8 0 register before A B C D E F G H $24 LDR $24, 5 ($0) after A B C register D E 7 6 5 $24 598 CHAPTER 27 CPU INSTRUCTION SET DETAILS LDR Load Doubleword Right (Continued) LDR The contents of general register rt are internally bypassed within the processor so that no NOP is needed between an immediately preceding load instruction which specifies register rt and a following LDR (or LDL) instruction which also specifies register rt. No address error exceptions due to alignment are possible. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: vAddr <- ((offset15) 48 || offset15..0) + GPR [base] 3 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1..3 || (pAddr2..0 xor ReverseEndian ) if BigEndianMem = 1 then pAddr <- pAddrPSIZE - 1..3 || 0 endif byte <- vAddr2..0 xor BigEndianCPU 3 3 mem <- LoadMemory (uncached, DOUBLEWORD-byte, pAddr, vAddr, DATA) GPR [rt] <- GPR [rt]63..64 - 8 * byte || mem63..8 * byte 599 CHAPTER 27 CPU INSTRUCTION SET DETAILS LDR Load Doubleword Right (Continued) LDR Given a doubleword in a register and a doubleword in memory, the operation of LDR is as follows: LDR Register Memory A I B J C K D L E M F N G O H P vAddr2..0 BigEndianCPU = 0 destination type offset (LEM) 0 1 2 3 4 5 6 7 I J K LMNOP A I J K LMNO A B I J K LMN ABC I JKLM ABCD I J K L ABCDE I J K ABCDEF I J ABCDEFG I 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 LEM Type Offset Little-endian memory (BigEndianMem = 0) AccessType (see Table 3-2) sent to memory pAddr2..0 sent to memory Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 600 CHAPTER 27 CPU INSTRUCTION SET DETAILS LH 31 26 25 21 20 Load Halfword 16 15 LH 0 LH 100001 6 base 5 rt 5 offset 16 Format: LH rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the halfword at the memory location specified by the effective address are sign-extended and loaded into general register rt. If the least-significant bit of the effective address is non-zero, an address error exception occurs. Operation: 32 T: vAddr <- ((offset15) 16 || offset15...0) + GPR [base] 2 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian || 0)) mem <- LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA) byte <- vAddr2...0 xor (BigEndianCPU || 0) GPR [rt] <- (mem15 + 8 * byte) 64 T: vAddr <- ((offset15) 48 16 2 || mem15 + 8 * byte...8 * byte || offset15...0) + GPR [base] 2 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian || 0)) mem <- LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA) byte <- vAddr2...0 xor (BigEndianCPU || 0) GPR [rt] <- (mem15 + 8 * byte) 48 2 || mem15 + 8 * byte...8 * byte Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception 601 CHAPTER 27 CPU INSTRUCTION SET DETAILS LHU 31 26 25 Load Halfword Unsigned 21 20 16 15 LHU 0 LHU 100101 6 base 5 rt 5 offset 16 Format: LHU rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the halfword at the memory location specified by the effective address are zero-extended and loaded into general register rt. If the least-significant bit of the effective address is non-zero, an address error exception occurs. Operation: 32 T: vAddr <- ((offset15) 16 || offset15...0) + GPR [base] 2 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian || 0)) mem <- LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA) byte <- vAddr2...0 xor (BigEndianCPU || 0) GPR [rt] <- 0 64 T: 16 2 || mem15 + 8 * byte...8 * byte 48 vAddr <- ((offset15) || offset15...0) + GPR [base] 2 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian || 0)) mem <- LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA) byte <- vAddr2...0 xor (BigEndianCPU || 0) GPR [rt] <- 0 48 2 || mem15 + 8 * byte...8 * byte Exceptions: TLB refill exception TLB invalid exception Bus Error exception Address error exception 602 CHAPTER 27 CPU INSTRUCTION SET DETAILS LUI 31 26 25 Load Upper Immediate 21 20 16 15 LUI 0 LUI 001111 6 0 00000 5 rt 5 immediate 16 Format: LUI rt, immediate Description: The 16-bit immediate is shifted left 16 bits and concatenated to 16 bits of zeros. The result is placed into general register rt. In 64-bit mode, the loaded word is sign-extended. Operation: 32 64 T: T: GPR [rt] <- immediate || 0 GPR [rt] <- (immediate15) 16 32 || immediate || 0 16 Exceptions: None 603 CHAPTER 27 CPU INSTRUCTION SET DETAILS LW 31 26 25 21 20 Load Word 16 15 LW 0 LW 100011 6 base 5 rt 5 offset 16 Format: LW rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the word at the memory location specified by the effective address are loaded into general register rt. In 64-bit mode, the loaded word is sign-extended. If either of the two least-significant bits of the effective address is non-zero, an address error exception occurs. Operation: 32 T: vAddr <- ((offset15) 16 || offset15...0) + GPR [base] 2 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian || 0 )) mem <- LoadMemory (uncached, WORD, pAddr, vAddr, DATA) byte <- vAddr2...0 xor (BigEndianCPU || 0 ) GPR [rt] <- mem31 + 8 * byte...8 * byte 64 T: vAddr <- ((offset15) 48 2 || offset15...0) + GPR [base] 2 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian || 0 )) mem <- LoadMemory (uncached, WORD, pAddr, vAddr, DATA) byte <- vAddr2...0 xor (BigEndianCPU || 0 ) GPR [rt] <- (mem31 + 8 * byte) 32 2 || mem31 + 8 * byte...8 * byte Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception 604 CHAPTER 27 CPU INSTRUCTION SET DETAILS LWL 31 26 25 21 20 Load Word Left 16 15 LWL 0 LWL 100010 6 base 5 rt 5 offset 16 Format: LWL rt, offset (base) Description: This instruction can be used in combination with the LWR instruction to load a register with four consecutive bytes from memory, when the bytes cross a word boundary. LWL loads the left portion of the register with the appropriate part of the high-order word; LWR loads the right portion of the register with the appropriate part of the low-order word. The LWL instruction adds its sign-extended 16-bit offset to the contents of general register base to form a virtual address which can specify an arbitrary byte. It reads bytes only from the word in memory which contains the specified starting byte. From one to four bytes will be loaded, depending on the starting byte specified. In 64-bit mode, the loaded word is sign-extended. Conceptually, it starts at the specified byte in memory and loads that byte into the high-order (left-most) byte of the register; then it loads bytes from memory into the register until it reaches the low-order byte of the word in memory. The least-significant (right-most) byte(s) of the register will not be changed. memory address 4 address 0 7 3 6 2 5 1 4 0 register before A B C D $24 LWL $24, 4 ($0) after 4 B C D $24 605 CHAPTER 27 CPU INSTRUCTION SET DETAILS LWL Load Word Left (Continued) LWL The contents of general register rt are internally bypassed within the processor so that no NOP is needed between an immediately preceding load instruction which specifies register rt and a following LWL (or LWR) instruction which also specifies register rt. No address error exceptions due to alignment are possible. Operation: 32 T: vAddr <- ((offset15) 16 || offset15...0) + GPR [base] 3 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor ReverseEndian ) if BigEndianMem = 0 then pAddr <- pAddrPSIZE - 1...2 || 0 endif byte <- vAddr1...0 xor BigEndianCPU word <- vAddr2 xor BigEndianCPU mem <- LoadMemory (uncached, byte, pAddr, vAddr, DATA) temp <- mem32 * word + 8 * byte + 7...32 * word || GPR [rt]23 - 8 * byte...0 GPR [rt] <- temp 64 T: vAddr <- ((offset15) 48 2 2 || offset15...0) + GPR [base] 3 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor ReverseEndian ) if BigEndianMem = 0 then pAddr <- pAddrPSIZE - 1...2 || 0 endif byte <- vAddr1...0 xor BigEndianCPU word <- vAddr2 xor BigEndianCPU mem <- LoadMemory (uncached, 0 || byte, pAddr, vAddr, DATA) temp <- mem32 * word + 8 * byte + 7...32 * word || GPR [rt]23 - 8 * byte...0 GPR [rt] <- (temp31) 32 2 2 || temp 606 CHAPTER 27 CPU INSTRUCTION SET DETAILS LWL Load Word Left (Continued) LWL Given a doubleword in a register and a doubleword in memory, the operation of LWL is as follows: LWL Register Memory A I B J C K D L E M F N G O H P vAddr2..0 BigEndianCPU = 0 destination type offset (LEM) 0 1 2 3 4 5 6 7 S SSSP FGH S SSSOPGH S SSSNOPH S S S SMNOP S SSS L FGH S SSSK LGH SSSSJKLH SSSS I JKL 0 1 2 3 0 1 2 3 0 0 0 0 4 4 4 4 LEM Type Offset S Little-endian memory (BigEndianMem = 0) AccessType (see Table 3-2) sent to memory pAddr2...0 sent to memory sign-extend of destination31 Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception 607 CHAPTER 27 CPU INSTRUCTION SET DETAILS LWR 31 26 25 21 20 Load Word Right 16 15 LWR 0 LWR 100110 6 base 5 rt 5 offset 16 Format: LWR rt, offset (base) Description: This instruction can be used in combination with the LWL instruction to load a register with four consecutive bytes from memory, when the bytes cross a word boundary. LWR loads the right portion of the register with the appropriate part of the low-order word; LWL loads the left portion of the register with the appropriate part of the high-order word. The LWR instruction adds its sign-extended 16-bit offset to the contents of general register base to form a virtual address which can specify an arbitrary byte. It reads bytes only from the word in memory which contains the specified starting byte. From one to four bytes will be loaded, depending on the starting byte specified. In 64-bit mode, the loaded word is sign-extended. Conceptually, it starts at the specified byte in memory and loads that byte into the low-order (right-most) byte of the register; then it loads bytes from memory into the register until it reaches the high-order byte of the word in memory. The most significant (left-most) byte(s) of the register will not be changed. memory address 4 address 0 7 3 6 2 5 1 4 0 register before A B C D $24 LWR $24, 1 ($0) after A 3 2 1 $24 608 CHAPTER 27 CPU INSTRUCTION SET DETAILS LWR Load Word Right (Continued) LWR The contents of general register rt are internally bypassed within the processor so that no NOP is needed between an immediately preceding load instruction which specifies register rt and a following LWR (or LWL) instruction which also specifies register rt. No address error exceptions due to alignment are possible. Operation: 32 T: vAddr <- ((offset15) 16 || offset15...0) + GPR [base] 3 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor ReverseEndian ) if BigEndianMem = 1 then pAddr <- pAddrPSIZE - 1...3 || 0 endif byte <- vAddr1...0 xor BigEndianCPU word <- vAddr2 xor BigEndianCPU mem <- LoadMemory (uncached, 0 || byte, pAddr, vAddr, DATA) temp <- GPR [rt]31...32 - 8 * byte || mem31 + 32 * word...32 * word + 8 * byte GPR [rt] <- temp 64 T: vAddr <- ((offset15) 48 2 3 || offset15...0) + GPR [base] 3 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor ReverseEndian ) if BigEndianMem = 1 then pAddr <- pAddrPSIZE - 1...3 || 0 endif byte <- vAddr1...0 xor BigEndianCPU word <- vAddr2 xor BigEndianCPU mem <- LoadMemory (uncached, WORD-byte, pAddr, vAddr, DATA) temp <- GPR [rt]31...32 - 8 * byte || mem31 + 32 * word...32 * word + 8 * byte GPR [rt] <- (temp31) 32 2 3 || temp 609 CHAPTER 27 CPU INSTRUCTION SET DETAILS LWR Load Word Right (Continued) LWR Given a word in a register and a word in memory, the operation of LWR is as follows: LWR Register Memory A I B J C K D L E M F N G O H P vAddr2..0 BigEndianCPU = 0 destination type offset (LEM) 0 1 2 3 4 5 6 7 S S S SMNOP S S S S EMNO S S S S E FMN S S S S E F GM SSSS I JKL SSSSE I JK SSSSEF I J SSSSEFG I 3 2 1 0 3 2 1 0 0 1 2 3 4 5 6 7 LEM Type Offset S Little-endian memory (BigEndianMem = 0) AccessType (see Table 3-2) sent to memory pAddr2...0 sent to memory sign-extend of destination31 Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception 610 CHAPTER 27 CPU INSTRUCTION SET DETAILS LWU 31 26 25 Load Word Unsigned 21 20 16 15 LWU 0 LWU 101111 6 base 5 rt 5 offset 16 Format: LWU rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the word at the memory location specified by the effective address are loaded into general register rt. The loaded word is zero-extended. If either of the two least-significant bits of the effective address is non-zero, an address error exception occurs. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 32 T: vAddr <- ((offset15) 16 || offset15...0) + GPR [base] 2 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian || 0 )) mem <- LoadMemory (uncached, WORD, pAddr, vAddr, DATA) byte <- vAddr2...0 xor (BigEndianCPU || 0 ) GPR [rt] <- 0 64 T: 32 2 || mem31 + 8 * byte...8 * byte 48 vAddr <- ((offset15) || offset15...0) + GPR [base] 2 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian || 0 )) mem <- LoadMemory (uncached, WORD, pAddr, vAddr, DATA) byte <- vAddr2...0 xor (BigEndianCPU || 0 ) GPR [rt] <- 0 32 2 || mem31 + 8 * byte...8 * byte Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 611 CHAPTER 27 CPU INSTRUCTION SET DETAILS MADD16 31 26 25 Multiply and Add 16-bit integer 21 20 16 15 65 MADD16 0 SPECIAL 000000 6 rs 5 rt 5 00 0 0000 10 0000 DMADD16 101000 6 Format: MADD16 rs, rt Description: The contents of general registers rs and rt are multiplied, treating both operands as 16-bit 2's complement values. The operand[62:15] must be valid 15-bit, sign-extended values. If not, the results is unpredictable. This multiplied result and the 64-bit data joined special register HI to LO are added to form the result. No integer overflow exception occurs under any circumstances. When the operation completes, the low-order word of the double result is loaded into special register LO, and the high-order word of the double result is loaded into special register HI. The following Table are hazard cycles between MADD16 and other instructions. Instruction sequence MULT/MULTU -> MADD16 DMULT/DMULTU -> MADD16 DIV/DIVU -> MADD16 DDIV/DDIVU -> MADD16 MFHI/MFLO -> MADD16 DMADD16 -> MADD16 MADD16 -> MADD16 No. of cycles 1 Cycle 4 Cycles 36 Cycles 68 Cycles 2 Cycles 0 Cycles 0 Cycles Operation: 32, 64 T: temp1<- GPR [rs] * GPR [rt] temp2<- temp1 + (HI31...0 || LO31...0) LO HI <- (temp131) <- (temp263) 32 32 || temp231...0 || temp263...32 Exceptions: None 612 CHAPTER 27 CPU INSTRUCTION SET DETAILS MFC0 31 Move From System Control Coprocessor 26 25 21 20 16 15 11 10 MFC0 0 COP0 010000 6 MF 00000 5 rt 5 rd 5 000 0 0000 11 0000 Format: MFC0 rt, rd Description: The contents of coprocessor register rd of the CP0 are loaded into general register rt. When using a register used by the MFC0 by means of instructions before and after it, refer to Chapter 28 and place the instructions in the appropriate location. Operation: 32 T: data <- CPR [0, rd] T+1: GPR [rt] <- data 64 T: data <- CPR [0, rd] 32 T+1: GPR [rt] <- (data31) || data31...0 Exceptions: Coprocessor unusable exception (user and supervisor mode if CP0 not enabled) 613 CHAPTER 27 CPU INSTRUCTION SET DETAILS MFHI 31 26 25 Move From HI 16 15 11 10 65 MFHI 0 SPECIAL 000000 6 00 0 0000 10 0000 rd 5 0 00000 5 MFHI 010000 6 Format: MFHI rd Description: The contents of special register HI are loaded into general register rd. To ensure proper operation in the event of interruptions, the two instructions which follow a MFHI instruction may not be any of the instructions which modify the HI register: MULT, MULTU, DIV, DIVU, MTHI, DMULT, DMULTU, DDIV, DDIVU. Operation: 32, 64 T: GPR [rd] <- HI Exceptions: None 614 CHAPTER 27 CPU INSTRUCTION SET DETAILS MFLO 31 26 25 Move From LO 16 15 11 10 65 MFLO 0 SPECIAL 000000 6 00 0 0000 10 0000 rd 5 0 00000 5 MFLO 010010 6 Format: MFLO rd Description: The contents of special register LO are loaded into general register rd. To ensure proper operation in the event of interruptions, the two instructions which follow a MFLO instruction may not be any of the instructions which modify the LO register: MULT, MULTU, DIV, DIVU, MTLO, DMULT, DMULTU, DDIV, DDIVU. Operation: 32, 64 T: GPR [rd] <- LO Exceptions: None 615 CHAPTER 27 CPU INSTRUCTION SET DETAILS MTC0 31 26 25 Move To Coprocessor0 21 20 16 15 11 10 MTC0 0 COP0 010000 6 MT 00100 5 rt 5 rd 5 000 0 0000 11 0000 Format: MTC0 rt, rd Description: The contents of general register rt are loaded into coprocessor register rd of coprocessor 0. Because the state of the virtual address translation system may be altered by this instruction, the operation of load instructions, store instructions, and TLB operations immediately prior to and after this instruction are undefined. When using a register used by the MTC0 by means of instructions before and after it, refer to Chapter 28 and place the instructions in the appropriate location. Operation: 32, 64 T: data <- GPR [rt] T+1: CPR [0, rd] <- data Exceptions: Coprocessor unusable exception (user and supervisor mode if CP0 not enabled) 616 CHAPTER 27 CPU INSTRUCTION SET DETAILS MTHI 31 26 25 21 20 Move To HI 65 MTHI 0 SPECIAL 000000 6 rs 5 0 000 0000 0000 0000 15 MTHI 010001 6 Format: MTHI rs Description: The contents of general register rs are loaded into special register HI. If a MTHI operation is executed following a MULT, MULTU, DIV, or DIVU instruction, but before any MFLO, MFHI, MTLO, or MTHI instructions, the contents of special register HI are undefined. Operation: 32, 64 T-2: HI <- undefined T-1: HI <- undefined T: HI <- GPR [rs] Exceptions: None 617 CHAPTER 27 CPU INSTRUCTION SET DETAILS MTLO 31 26 25 21 20 Move To LO 65 MTLO 0 SPECIAL 000000 6 rs 5 0 000 0000 0000 0000 15 MTLO 010011 6 Format: MTLO rs Description: The contents of general register rs are loaded into special register LO. If an MTLO operation is executed following a MULT, MULTU, DIV, or DIVU instruction, but before any MFLO, MFHI, MTLO, or MTHI instructions, the contents of special register LO are undefined. Operation: 32, 64 T-2: LO <- undefined T-1: LO <- undefined T: LO <- GPR [rs] Exceptions: None 618 CHAPTER 27 CPU INSTRUCTION SET DETAILS MULT 31 26 25 21 20 Multiply 16 15 65 MULT 0 SPECIAL 000000 6 rs 5 rt 5 00 0 0000 10 0000 MULT 011000 6 Format: MULT rs, rt Description: The contents of general registers rs and rt are multiplied, treating both operands as 32-bit 2's complement values. No integer overflow exception occurs under any circumstances. In 64-bit mode, the operands must be valid 32bit, sign-extended values. When the operation completes, the low-order word of the double result is loaded into special register LO, and the high-order word of the double result is loaded into special register HI. If either of the two preceding instructions is MFHI or MFLO, the results of these instructions are undefined. Correct operation requires separating reads of HI or LO from writes by a minimum of two other instructions. Operation: 32 T-2: T-1: T: LO HI LO HI t LO HI 64 T-2: T-1: T: LO HI LO HI t LO HI <- undefined <- undefined <- undefined <- undefined <- GPR [rs] * GPR [rt] <- t31...0 <- t63...32 <- undefined <- undefined <- undefined <- undefined <- GPR [rs]31...0 * GPR [rt]31...0 <- (t31) <- (t63) 32 32 || t31...0 || t63...32 Exceptions: None 619 CHAPTER 27 CPU INSTRUCTION SET DETAILS MULTU 31 26 25 21 20 Multiply Unsigned 16 15 65 MULTU 0 SPECIAL 000000 6 rs 5 rt 5 00 0 0000 10 0000 MULTU 011001 6 Format: MULTU rs, rt Description: The contents of general register rs and the contents of general register rt are multiplied, treating both operands as unsigned values. No overflow exception occurs under any circumstances. In 64-bit mode, the operands must be valid 32-bit, sign-extended values. When the operation completes, the low-order word of the double result is loaded into special register LO, and the high-order word of the double result is loaded into special register HI. If either of the two preceding instructions is MFHI or MFLO, the results of these instructions are undefined. Correct operation requires separating reads of HI or LO from writes by a minimum of two instructions. Operation: 32 T-2: T-1: T: LO HI LO HI t LO HI 64 T-2: T-1: T: LO HI LO HI t LO HI <- undefined <- undefined <- undefined <- undefined <- (0 || GPR [rs]) * (0 || GPR [rt]) <- t31...0 <- t63...32 <- undefined <- undefined <- undefined <- undefined <- (0 || GPR [rs]31...0) * (0 || GPR [rt]31...0) <- (t31) <- (t63) 32 32 || t31...0 || t63...32 Exceptions: None 620 CHAPTER 27 CPU INSTRUCTION SET DETAILS NOR 31 26 25 21 20 Nor 16 15 11 10 65 NOR 0 SPECIAL 000000 6 rs 5 rt 5 rd 5 0 00000 5 NOR 100111 6 Format: NOR rd, rs, rt Description: The contents of general register rs are combined with the contents of general register rt in a bit-wise logical NOR operation. The result is placed into general register rd. Operation: 32, 64 T: GPR [rd] <- GPR [rs] nor GPR [rt] Exceptions: None 621 CHAPTER 27 CPU INSTRUCTION SET DETAILS OR 31 26 25 21 20 Or 16 15 11 10 65 OR 0 SPECIAL 000000 6 rs 5 rt 5 rd 5 0 00000 5 OR 100101 6 Format: OR rd, rs, rt Description: The contents of general register rs are combined with the contents of general register rt in a bit-wise logical OR operation. The result is placed into general register rd. Operation: 32, 64 T: GPR [rd] <- GPR [rs] or GPR [rt] Exceptions: None 622 CHAPTER 27 CPU INSTRUCTION SET DETAILS ORI 31 26 25 21 20 Or Immediate 16 15 ORI 0 ORI 001101 6 rs 5 rt 5 immediate 16 Format: ORI rt, rs, immediate Description: The 16-bit immediate is zero-extended and combined with the contents of general register rs in a bit-wise logical OR operation. The result is placed into general register rt. Operation: 32 64 T: T: GPR [rt] <- GPR [rs]31...16 || (immediate or GPR [rs]15...0) GPR [rt] <- GPR [rs]63...16 || (immediate or GPR [rs]15...0) Exceptions: None 623 CHAPTER 27 CPU INSTRUCTION SET DETAILS SB 31 26 25 21 20 Store Byte 16 15 SB 0 SB 101000 6 base 5 rt 5 offset 16 Format: SB rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The least-significant byte of register rt is stored at the effective address. Operation: 32 T: vAddr <- ((offset15) 16 || offset15...0) + GPR [base] 3 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian )) byte <- vAddr2...0 xor BigEndianCPU data <- GPR [rt]63 - 8 * byte...0 || 0 8 * byte 3 StoreMemory (uncached, BYTE, data, pAddr, vAddr, DATA) 64 T: vAddr <- ((offset15) 48 || offset15...0) + GPR [base] 3 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian )) byte <- vAddr2...0 xor BigEndianCPU data <- GPR [rt]63 - 8 * byte...0 || 0 8 * byte 3 StoreMemory (uncached, BYTE, data, pAddr, vAddr, DATA) Exceptions: TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception 624 CHAPTER 27 CPU INSTRUCTION SET DETAILS SD 31 26 25 21 20 Store Doubleword 16 15 SD 0 SD 111111 6 base 5 rt 5 offset 16 Format: SD rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of general register rt are stored at the memory location specified by the effective address. If either of the three least-significant bits of the effective address are non-zero, an address error exception occurs. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: vAddr <- ((offset15) data <- GPR [rt] StoreMemory (uncached, DOUBLEWORD, data, pAddr, vAddr, DATA) 48 || offset15...0) + GPR [base] (pAddr, uncached) <- AddressTranslation (vAddr, DATA) Exceptions: TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 625 CHAPTER 27 CPU INSTRUCTION SET DETAILS SDL 31 26 25 Store Doubleword Left 21 20 16 15 SDL 0 SDL 101100 6 base 5 rt 5 offset 16 Format: SDL rt, offset (base) Description: This instruction can be used with the SDR instruction to store the contents of a register into eight consecutive bytes of memory, when the bytes cross a doubleword boundary. SDL stores the left portion of the register into the appropriate part of the high-order doubleword of memory; SDR stores the right portion of the register into the appropriate part of the low-order doubleword. The SDL instruction adds its sign-extended 16-bit offset to the contents of general register base to form a virtual address which may specify an arbitrary byte. It alters only the word in memory which contains that byte. From one to four bytes will be stored, depending on the starting byte specified. Conceptually, it starts at the most-significant byte of the register and copies it to the specified byte in memory; then it copies bytes from register to memory until it reaches the low-order byte of the word in memory. No address error exceptions due to alignment are possible. memory address 8 address 0 15 14 13 12 11 10 7 6 5 4 3 2 9 1 8 0 register A B C D E F G H $24 before SDL $24, 8 ($0) address 8 address 0 15 14 13 12 11 10 7 6 5 4 3 2 9 1 A 0 after 626 CHAPTER 27 CPU INSTRUCTION SET DETAILS SDL Store Doubleword Left (Continued) SDL This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: vAddr <- ((offset15) 48 || offset15...0) + GPR [base] 3 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor ReverseEndian ) if BigEndianMem = 0 then pAddr <- pAddrPSIZE - 1...3 || 0 endif byte <- vAddr2...0 xor BigEndianCPU data <- 0 56 - 8 * byte 3 3 || GPR [rt]63...56 - 8 * byte Storememory (uncached, byte, data, pAddr, vAddr, DATA) 627 CHAPTER 27 CPU INSTRUCTION SET DETAILS SDL Store Doubleword Left (Continued) SDL Given a doubleword in a register and a doubleword in memory, the operation of SDL is as follows: SDL Register Memory A I B J C K D L E M F N G O H P vAddr2..0 BigEndianCPU = 0 destination type offset (LEM) 0 1 2 3 4 5 6 7 I J K LMNOA I J K LMNA B I J K LMA BC I J K L ABCD I J KABCDE I J ABCDEF I ABCDEFG A BCDE FGH 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 LEM Type Offset Little-endian memory (BigEndianMem = 0) AccessType (see Table 3-2) sent to memory pAddr2...0 sent to memory Exceptions: TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 628 CHAPTER 27 CPU INSTRUCTION SET DETAILS SDR 31 26 25 Store Doubleword Right 21 20 16 15 SDR 0 SDR 101101 6 base 5 rt 5 offset 16 Format: SDR rt, offset (base) Description: This instruction can be used with the SDL instruction to store the contents of a register into eight consecutive bytes of memory, when the bytes cross a boundary between two doublewords. SDR stores the right portion of the register into the appropriate part of the low-order doubleword; SDL stores the left portion of the register into the appropriate part of the low-order doubleword of memory. The SDR instruction adds its sign-extended 16-bit offset to the contents of general register base to form a virtual address which may specify an arbitrary byte. It alters only the word in memory which contains that byte. From one to eight bytes will be stored, depending on the starting byte specified. Conceptually, it starts at the least-significant (rightmost) byte of the register and copies it to the specified byte in memory; then it copies bytes from register to memory until it reaches the high-order byte of the word in memory. No address error exceptions due to alignment are possible. memory address 8 address 0 15 14 13 12 11 10 7 6 5 4 3 2 9 1 8 0 register A B C D E F G H $24 before SDR $24, 1 ($0) address 8 address 0 15 14 13 12 11 10 B C D E F G 9 H 8 0 after 629 CHAPTER 27 CPU INSTRUCTION SET DETAILS SDR Store Doubleword Right (Continued) SDR This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: vAddr <- ((offset15) 48 || offset15...0) + GPR [base] 3 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor ReverseEndian ) if BigEndianMem = 0 then pAddr <- pAddrPSIZE - 1...3 || 0 endif byte <- vAddr2...0 xor BigEndianCPU data <- GPR [rt]63 - 8 * byte || 0 8 * byte 3 3 StoreMemory (uncached, DOUBLEWORD-byte, data, pAddr, vAddr, DATA) 630 CHAPTER 27 CPU INSTRUCTION SET DETAILS SDR Store Doubleword Right (Continued) SDR Given a doubleword in a register and a doubleword in memory, the operation of SDR is as follows: SDR Register Memory A I B J C K D L E M F N G O H P vAddr2..0 BigEndianCPU = 0 destination type offset (LEM) 0 1 2 3 4 5 6 7 A BCDE FGH BCDE FGHP CDE FGHOP DE FGHNOP E FGHMNOP F GH LMNOP GHK LMNOP H J K LMNOP 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 LEM Type Offset Little-endian memory (BigEndianMem = 0) AccessType (see Table 2-2) sent to memory pAddr2...0 sent to memory Exceptions: TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) 631 CHAPTER 27 CPU INSTRUCTION SET DETAILS SH 31 26 25 21 20 Store Halfword 16 15 SH 0 SH 101001 6 base 5 rt 5 offset 16 Format: SH rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form an unsigned effective address. The least-significant halfword of register rt is stored at the effective address. If the leastsignificant bit of the effective address is non-zero, an address error exception occurs. Operation: 32 T: vAddr <- ((offset15) 16 || offset15...0) + GPR [base] 2 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian || 0)) byte <- vAddr2...0 xor (BigEndianCPU || 0) data <- GPR [rt]63 - 8 * byte...0 || 0 8 * byte 2 StoreMemory (uncached, HALFWORD, data, pAddr, vAddr, DATA) 64 T: vAddr <- ((offset15) 48 || offset15...0) + GPR [base] 2 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian || 0)) byte <- vAddr2...0 xor (BigEndianCPU || 0) data <- GPR [rt]63 - 8 * byte...0 || 0 8 * byte 2 StoreMemory (uncached, HALFWORD, data, pAddr, vAddr, DATA) Exceptions: TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception 632 CHAPTER 27 CPU INSTRUCTION SET DETAILS SLL 31 26 25 21 20 Shift Left Logical 16 15 11 10 65 SLL 0 SPECIAL 000000 6 0 00000 5 rt 5 rd 5 sa 5 SLL 000000 6 Format: SLL rd, rt, sa Description: The contents of general register rt are shifted left by sa bits, inserting zeros into the low-order bits. The result is placed in register rd. In 64-bit mode, the 32-bit result is sign-extended when placed in the destination register. It is sign extended for all shift amounts, including zero; SLL with zero shift amount truncates a 64-bit value to 32 bits and then sign extends this 32-bit value. SLL, unlike nearly all other word operations, does not require an operand to be a properly sign-extended word value to produce a valid sign-extended word result. Operation: 32 64 T: T: GPR [rd] <- GPR [rt]31 - sa...0 || 0 s <- 0 || sa temp <- GPR [rt]31 - s...0 || 0 GPR [rd] <- (temp31) 32 s sa || temp Exceptions: None Remark SLL with a shift amount of zero may be treated as a NOP by some assemblers, at some optimization levels. If using SLL with a zero shift to truncate 64-bit values, check the assembler you are using. 633 CHAPTER 27 CPU INSTRUCTION SET DETAILS SLLV 31 26 25 Shift Left Logical Variable 21 20 16 15 11 10 65 SLLV 0 SPECIAL 000000 6 rs 5 rt 5 rd 5 0 00000 5 SLLV 000100 6 Format: SLLV rd, rt, rs Description: The contents of general register rt are shifted left the number of bits specified by the low-order five bits contained in general register rs, inserting zeros into the low-order bits. The result is placed in register rd. In 64-bit mode, the 32-bit result is sign-extended when placed in the destination register. It is sign extended for all shift amounts, including zero; SLLV with zero shift amount truncates a 64-bit value to 32 bits and then sign extends this 32-bit value. SLLV, unlike nearly all other word operations, does not require an operand to be a properly sign-extended word value to produce a valid sign-extended word result. Operation: 32 T: s <- GPR [rs]4...0 GPR [rd] <- GPR [rt](31 - s)...0 || 0 64 T: s <- 0 || GPR [rs]4...0 temp <- GPR [rt](31 - s)...0 || 0 GPR [rd] <- (temp31) 32 s s || temp Exceptions: None Remark SLLV with a shift amount of zero may be treated as a NOP by some assemblers, at some optimization levels. If using SLLV with a zero shift to truncate 64-bit values, check the assembler you are using. 634 CHAPTER 27 CPU INSTRUCTION SET DETAILS SLT 31 26 25 21 20 Set On Less Than 16 15 11 10 65 SLT 0 SPECIAL 000000 6 rs 5 rt 5 rd 5 0 00000 5 SLT 101010 6 Format: SLT rd, rs, rt Description: The contents of general register rt are subtracted from the contents of general register rs. Considering both quantities as signed integers, if the contents of general register rs are less than the contents of general register rt, the result is set to one; otherwise the result is set to zero. The result is placed into general register rd. No integer overflow exception occurs under any circumstances. The comparison is valid even if the subtraction used during the comparison overflows. Operation: 32 T: if GPR [rs] < GPR [rt] then GPR [rd] <- 0 else GPR [rd] <- 0 endif 64 T: if GPR [rs] < GPR [rt] then GPR [rd] <- 0 else GPR [rd] <- 0 endif 64 63 32 31 || 1 || 1 Exceptions: None 635 CHAPTER 27 CPU INSTRUCTION SET DETAILS SLTI 31 26 25 Set On Less Than Immediate 21 20 16 15 SLTI 0 SLTI 001010 6 rs 5 rt 5 immediate 16 Format: SLTI rt, rs, immediate Description: The 16-bit immediate is sign-extended and subtracted from the contents of general register rs. Considering both quantities as signed integers, if rs is less than the sign-extended immediate, the result is set to one; otherwise the result is set to zero. The result is placed into general register rt. No integer overflow exception occurs under any circumstances. The comparison is valid even if the subtraction used during the comparison overflows. Operation: 32 T: if GPR [rs] < (immediate15) GPR [rt] <- 0 else GPR [rt] <- 0 endif 64 T: if GPR [rs] < (immediate15) GPR [rt] <- 0 else GPR [rt] <- 0 endif 64 63 48 32 31 16 || immediate15...0 then || 1 || immediate15...0 then || 1 Exceptions: None 636 CHAPTER 27 CPU INSTRUCTION SET DETAILS SLTIU 31 26 25 Set On Less Than Immediate Unsigned 21 20 16 15 SLTIU 0 SLTIU 001011 6 rs 5 rt 5 immediate 16 Format: SLTIU rt, rs, immediate Description: The 16-bit immediate is sign-extended and subtracted from the contents of general register rs. Considering both quantities as unsigned integers, if rs is less than the sign-extended immediate, the result is set to one; otherwise the result is set to zero. The result is placed into general register rt. No integer overflow exception occurs under any circumstances. The comparison is valid even if the subtraction used during the comparison overflows. Operation: 32 T: if (0 || GPR [rs]) < (0 || (immediate15) GPR [rt] <- 0 else GPR [rt] <- 0 endif 64 T: if (0 || GPR [rs]) < (0 || (immediate15) GPR [rt] <- 0 else GPR [rt] <- 0 endif 64 63 48 32 31 16 || immediate15...0) then || 1 || immediate15...0) then || 1 Exceptions: None 637 CHAPTER 27 CPU INSTRUCTION SET DETAILS SLTU 31 26 25 Set On Less Than Unsigned 21 20 16 15 11 10 65 SLTU 0 SPECIAL 000000 6 rs 5 rt 5 rd 5 0 00000 5 SLTU 101011 6 Format: SLTU rd, rs, rt Description: The contents of general register rt are subtracted from the contents of general register rs. Considering both quantities as unsigned integers, if the contents of general register rs are less than the contents of general register rt, the result is set to one; otherwise the result is set to zero. The result is placed into general register rd. No integer overflow exception occurs under any circumstances. The comparison is valid even if the subtraction used during the comparison overflows. Operation: 32 T: if (0 || GPR [rs]) < 0 || GPR [rt] then GPR [rd] <- 0 else GPR [rd] <- 0 endif 64 T: if (0 || GPR [rs]) < 0 || GPR [rt] then GPR [rd] <- 0 else GPR [rd] <- 0 endif 64 63 32 31 || 1 || 1 Exceptions: None 638 CHAPTER 27 CPU INSTRUCTION SET DETAILS SRA 31 26 25 Shift Right Arithmetic 21 20 16 15 11 10 65 SRA 0 SPECIAL 000000 6 0 00000 5 rt 5 rd 5 sa 5 SRA 000011 6 Format: SRA rd, rt, sa Description: The contents of general register rt are shifted right by sa bits, sign-extending the high-order bits. The result is placed in register rd. In 64-bit mode, the operand must be a valid sign-extended, 32-bit value. Operation: 32 64 T: T: GPR [rd] <- (GPR [rt]31) || GPR [rt]31...sa s <- 0 || sa temp <- (GPR [rt]31) || GPR [rt]31...s GPR [rd] <- (temp31) 32 s sa || temp Exceptions: None 639 CHAPTER 27 CPU INSTRUCTION SET DETAILS SRAV 31 26 25 Shift Right Arithmetic Variable 21 20 16 15 11 10 65 SRAV 0 SPECIAL 000000 6 rs 5 rt 5 rd 5 0 00000 5 SRAV 000111 6 Format: SRAV rd, rt, rs Description: The contents of general register rt are shifted right by the number of bits specified by the low-order five bits of general register rs, sign-extending the high-order bits. The result is placed in register rd. In 64-bit mode, the operand must be a valid sign-extended, 32-bit value. Operation: 32 T: s <- GPR [rs]4...0 GPR [rd] <- (GPR [rt]31) || GPR [rt]31...s 64 T: s <- GPR [rs]4...0 temp <- (GPR [rt]31) || GPR [rt]31...s GPR [rd] <- (temp31) 32 s s || temp Exceptions: None 640 CHAPTER 27 CPU INSTRUCTION SET DETAILS SRL 31 26 25 21 20 Shift Right Logical 16 15 11 10 65 SRL 0 SPECIAL 000000 6 0 00000 5 rt 5 rd 5 sa 5 SRL 000010 6 Format: SRL rd, rt, sa Description: The contents of general register rt are shifted right by sa bits, inserting zeros into the high-order bits. The result is placed in register rd. In 64-bit mode, the operand must be a valid sign-extended, 32-bit value. Operation: 32 64 T: T: GPR [rd] <- 0 || GPR [rt]31...sa s <- 0 || sa temp <- 0 || GPR [rt]31...s GPR [rd] <- (temp31) 32 s sa || temp Exceptions: None 641 CHAPTER 27 CPU INSTRUCTION SET DETAILS SRLV 31 26 25 Shift Right Logical Variable 21 20 16 15 11 10 65 SRLV 0 SPECIAL 000000 6 rs 5 rt 5 rd 5 0 00000 5 SRLV 000110 6 Format: SRLV rd, rt, rs Description: The contents of general register rt are shifted right by the number of bits specified by the low-order five bits of general register rs, inserting zeros into the high-order bits. The result is placed in register rd. In 64-bit mode, the operand must be a valid sign-extended, 32-bit value. Operation: 32 T: s <- GPR [rs]4...0 GPR [rd] <- 0 || GPR [rt]31...s 64 T: s <- GPR [rs]4...0 temp <- 0 || GPR [rt]31...s GPR [rd] <- (temp31) 32 s s || temp Exceptions: None 642 CHAPTER 27 CPU INSTRUCTION SET DETAILS STANDBY 31 26 25 24 Standby 0 0000 19 STANDBY 65 0 COP0 010000 6 CO 1 000 0000 0000 0000 STANDBY 100001 6 1 Format: STANDBY Description: STANDBY instruction starts mode transition from Fullspeed mode to Standby mode. When the STANDBY instruction finishes the WB stage, the VR4102 wait by the SysAD bus is idle state, after then the internal clocks will shut down, thus freezing the pipeline. The PLL, Timer/Interrupt clocks and the internal bus clocks (TClock and MasterOut) will continue to run. Once the VR4102 is in Standby mode, any interrupt, including the internally generated timer interrupt, NMI, Soft Reset, and Cold Reset will cause the VR4102 to exit Standby mode and to enter Fullspeed mode. Operation: 32, 64 T: T+1: Standby operation () Exceptions: Coprocessor unusable exception Remark Refer to Chapter 15 for details about the operation of the peripheral units at mode transition. 643 CHAPTER 27 CPU INSTRUCTION SET DETAILS SUB 31 26 25 21 20 Subtract 16 15 11 10 65 SUB 0 SPECIAL 000000 6 rs 5 rt 5 rd 5 0 00000 5 SUB 100010 6 Format: SUB rd, rs, rt Description: The contents of general register rt are subtracted from the contents of general register rs to form a result. The result is placed into general register rd. In 64-bit mode, the operands must be valid sign-extended, 32-bit values. The only difference between this instruction and the SUBU instruction is that SUBU never traps on overflow. An integer overflow exception takes place if the carries out of bits 30 and 31 differ (2's complement overflow). The destination register rd is not modified when an integer overflow exception occurs. Operation: 32 64 T: T: GPR [rd] <- GPR [rs] - GPR [rt] temp <- GPR [rs] - GPR [rt] GPR [rd] <- (temp31) 32 || temp31...0 Exceptions: Integer overflow exception 644 CHAPTER 27 CPU INSTRUCTION SET DETAILS SUBU 31 26 25 21 20 Subtract Unsigned 16 15 11 10 65 SUBU 0 SPECIAL 000000 6 rs 5 rt 5 rd 5 0 00000 5 SUBU 100011 6 Format: SUBU rd, rs, rt Description: The contents of general register rt are subtracted from the contents of general register rs to form a result. The result is placed into general register rd. In 64-bit mode, the operands must be valid sign-extended, 32-bit values. The only difference between this instruction and the SUB instruction is that SUBU never traps on overflow. No integer overflow exception occurs under any circumstances. Operation: 32 64 T: T: GPR [rd] <- GPR [rs] - GPR [rt] temp <- GPR [rs] - GPR [rt] GPR [rd] <- (temp31) 32 || temp31...0 Exceptions: None 645 CHAPTER 27 CPU INSTRUCTION SET DETAILS SUSPEND 31 26 25 24 Suspend 0 0000 19 SUSPEND 65 0 COP0 010000 6 CO 1 000 0000 0000 0000 SUSPEND 100010 6 1 Format: SUSPEND Description: SUSPEND instruction starts mode transition from Fullspeed mode to Suspend mode. When the SUSPEND instruction finishes the WB stage, the VR4102 wait by the SysAD bus is idle state, after then the internal clocks including the TClock will shut down, thus freezing the pipeline. The PLL, Timer/Interrupt clocks and MasterOut, will continue to run. Once the VR4102 is in Suspend mode, any interrupt, including the internally generated timer interrupt, NMI, Soft Reset and Cold Reset will cause the VR4102 to exit Suspend mode and to enter Fullspeed mode. Operation: 32, 64 T: T+1: Suspend operation () Exceptions: Coprocessor unusable exception Remark Refer to Chapter 15 for details about the operation of the peripheral units at mode transition. 646 CHAPTER 27 CPU INSTRUCTION SET DETAILS SW 31 26 25 21 20 Store Word 16 15 SW 0 SW 101011 6 base 5 rt 5 offset 16 Format: SW rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of general register rt are stored at the memory location specified by the effective address. If either of the two least-significant bits of the effective address are non-zero, an address error exception occurs. Operation: 32 T: vAddr <- ((offset15) 16 || offset15...0) + GPR [base] 2 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian || 0 )) byte <- vAddr2...0 xor (BigEndianCPU || 0 ) data <- GPR [rt]63 - 8 * byte || 0 8 * byte 2 StoreMemory (uncached, WORD, data, pAddr, vAddr, DATA) 64 T: vAddr <- ((offset15) 48 || offset15...0) + GPR [base] 2 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian || 0 )) byte <- vAddr2...0 xor (BigEndianCPU || 0 ) data <- GPR [rt]63 - 8 * byte || 0 8 * byte 2 StoreMemory (uncached, WORD, data, pAddr, vAddr, DATA) Exceptions: TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception 647 CHAPTER 27 CPU INSTRUCTION SET DETAILS SWL 31 26 25 21 20 Store Word Left 16 15 SWL 0 SWL 101010 6 base 5 rt 5 offset 16 Format: SWL rt, offset (base) Description: This instruction can be used with the SWR instruction to store the contents of a register into four consecutive bytes of memory, when the bytes cross a word boundary. SWL stores the left portion of the register into the appropriate part of the high-order word of memory; SWR stores the right portion of the register into the appropriate part of the low-order word. The SWL instruction adds its sign-extended 16-bit offset to the contents of general register base to form a virtual address which may specify an arbitrary byte. It alters only the word in memory which contains that byte. From one to four bytes will be stored, depending on the starting byte specified. Conceptually, it starts at the most-significant byte of the register and copies it to the specified byte in memory; then it copies bytes from register to memory until it reaches the low-order byte of the word in memory. No address error exceptions due to alignment are possible. memory address 4 address 0 7 3 6 2 5 1 4 0 register before A B C D $24 SWL $24, 4 ($0) address 4 address 0 7 3 6 2 5 1 A 0 after 648 CHAPTER 27 CPU INSTRUCTION SET DETAILS SWL Operation: 32 T: vAddr <- ((offset15) 16 Store Word Left (Continued) SWL || offset15...0) + GPR [base] 3 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor ReverseEndian ) if BigEndianMem = 0 then pAddr <- pAddrPSIZE - 1...2 || 0 endif byte <- vAddr1...0 xor BigEndianCPU data <- 0 else data <- 0 endif StoreMemory (uncached, byte, data, pAddr, vAddr, DATA) 64 T: vAddr <- ((offset15) 48 24 - 8 * byte 32 2 2 if (vAddr2 xor BigEndianCPU) = 0 then || 0 24 - 8 * byte || GPR [rt]31...24 - 8 * byte 32 || GPR [rt]31...24 - 8 * byte || 0 || offset15...0) + GPR [base] 3 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor ReverseEndian ) if BigEndianMem = 0 then pAddr <- pAddrPSIZE - 1...2 || 0 endif byte <- vAddr1...0 xor BigEndianCPU data <- 0 else data <- 0 endif StoreMemory (uncached, byte, data, pAddr, vAddr, DATA) 24 - 8 * byte 32 2 2 if (vAddr2 xor BigEndianCPU) = 0 then || 0 24 - 8 * byte || GPR [rt]31...24 - 8 * byte 32 || GPR [rt]31...24 - 8 * byte || 0 649 CHAPTER 27 CPU INSTRUCTION SET DETAILS SWL Store Word Left (Continued) SWL Given a doubleword in a register and a doubleword in memory, the operation of SWL is as follows: SWL Register Memory A I B J C K D L E M F N G O H P vAddr2..0 BigEndianCPU = 0 destination type offset (LEM) 0 1 2 3 4 5 6 7 I J K LMNOE I J K LMNE F I J K LME FG I J K L E FGH I J K EMNOP I J E FMNOP I E F GMNOP E FGHMNOP 0 1 2 3 0 1 2 3 0 0 0 0 4 4 4 4 LEM Type Offset Little-endian memory (BigEndianMem = 0) AccessType (see Table 3-2) sent to memory pAddr2...0 sent to memory Exceptions: TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception 650 CHAPTER 27 CPU INSTRUCTION SET DETAILS SWR 31 26 25 21 20 Store Word Right 16 15 SWR 0 SWR 101110 6 base 5 rt 5 offset 16 Format: SWR rt, offset (base) Description: This instruction can be used with the SWL instruction to store the contents of a register into four consecutive bytes of memory, when the bytes cross a boundary between two words. SWR stores the right portion of the register into the appropriate part of the low-order word; SWL stores the left portion of the register into the appropriate part of the low-order word of memory. The SWR instruction adds its sign-extended 16-bit offset to the contents of general register base to form a virtual address which may specify an arbitrary byte. It alters only the word in memory which contains that byte. From one to four bytes will be stored, depending on the starting byte specified. Conceptually, it starts at the least-significant (rightmost) byte of the register and copies it to the specified byte in memory; then copies bytes from register to memory until it reaches the high-order byte of the word in memory. No address error exceptions due to alignment are possible. memory address 4 address 0 7 3 6 2 5 1 4 0 register before A B C D $24 SWR $24, 1 ($0) address 4 address 0 7 B 6 C 5 D 4 0 after 651 CHAPTER 27 CPU INSTRUCTION SET DETAILS SWR Operation: 32 T: vAddr <- ((offset15) 16 Store Word Right (Continued) SWR || offset15...0) + GPR [base] 3 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor ReverseEndian ) if BigEndianMem = 1 then pAddr <- pAddrPSIZE - 1...2 || 0 endif byte <- vAddr1...0 xor BigEndianCPU data <- 0 else data <- GPR [rt]31 - 8 * byte || 0 endif StoreMemory (uncached, WORD-byte, data, pAddr, vAddr, DATA) 64 T: vAddr <- ((offset15) 48 8 * byte 32 2 2 if (vAddr2 xor BigEndianCPU) = 0 then || GPR [rt]31 - 8 * byte...0 || 0 8 * byte || 0 32 || offset15...0) + GPR [base] 3 (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor ReverseEndian ) if BigEndianMem = 1 then pAddr <- pAddrPSIZE - 1...2 || 0 endif byte <- vAddr1...0 xor BigEndianCPU data <- 0 else data <- GPR [rt]31 - 8 * byte || 0 endif StoreMemory (uncached, WORD-byte, data, pAddr, vAddr, DATA) 8 * byte 32 2 2 if (vAddr2 xor BigEndianCPU) = 0 then || GPR [rt]31 - 8 * byte...0 || 0 8 * byte || 0 32 652 CHAPTER 27 CPU INSTRUCTION SET DETAILS SWR Store Word Right (Continued) SWR Given a doubleword in a register and a doubleword in memory, the operation of SWR is as follows: SWR Register Memory A I B J C K D L E M F N G O H P vAddr2..0 BigEndianCPU = 0 destination type offset (LEM) 0 1 2 3 4 5 6 7 I J K L E FGH I J K L FGHP I J K LGHOP I J K L HNOP E FGHMNOP F GH LMNOP GHK LMNOP H J K LMNOP 3 2 1 0 3 2 1 0 0 1 2 3 4 5 6 7 LEM Type Offset Little-endian memory (BigEndianMem = 0) AccessType (see Table 3-2) sent to memory pAddr2...0 sent to memory Exceptions: TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception 653 CHAPTER 27 CPU INSTRUCTION SET DETAILS SYNC 31 26 25 Synchronize 65 SYNC 0 SPECIAL 000000 6 0000 0000 0 0000 20 0000 0000 SYNC 001111 6 Format: SYNC Description: The SYNC instruction is executed as a NOP on the VR4102. This operation maintains compatibility with code compiled for the VR4000 and VR4400. Operation: 32, 64 T: SyncOperation ( ) Exceptions: None 654 CHAPTER 27 CPU INSTRUCTION SET DETAILS SYSCALL 31 26 25 System Call SYSCALL 65 0 SPECIAL 000000 6 Code 20 SYSCALL 001100 6 Format: SYSCALL Description: A system call exception occurs, immediately and unconditionally transferring control to the exception handler. The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. Operation: 32, 64 T: SystemCallException Exceptions: System Call exception 655 CHAPTER 27 CPU INSTRUCTION SET DETAILS TEQ 31 26 25 21 20 Trap If Equal 16 15 65 TEQ 0 SPECIAL 000000 6 rs 5 rt 5 code 10 TEQ 110100 6 Format: TEQ rs, rt Description: The contents of general register rt are compared to general register rs. If the contents of general register rs are equal to the contents of general register rt, a trap exception occurs. The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. Operation: 32, 64 T: if GPR [rs] = GPR [rt] then TrapException endif Exceptions: Trap exception 656 CHAPTER 27 CPU INSTRUCTION SET DETAILS TEQI 31 26 25 Trap If Equal Immediate 21 20 16 15 TEQI 0 REGIMM 000001 6 rs 5 TEQI 01100 5 immediate 16 Format: TEQI rs, immediate Description: The 16-bit immediate is sign-extended and compared to the contents of general register rs. If the contents of general register rs are equal to the sign-extended immediate, a trap exception occurs. Operation: 32 T: if GPR [rs] = (immediate15) TrapException endif 64 T: if GPR [rs] = (immediate15) TrapException endif 48 16 || immediate15...0 then || immediate15...0 then Exceptions: Trap exception 657 CHAPTER 27 CPU INSTRUCTION SET DETAILS TGE 31 26 25 Trap If Greater Than Or Equal 21 20 16 15 65 TGE 0 SPECIAL 000000 6 rs 5 rt 5 code 10 TGE 110000 6 Format: TGE rs, rt Description: The contents of general register rt are compared to the contents of general register rs. Considering both quantities as signed integers, if the contents of general register rs are greater than or equal to the contents of general register rt, a trap exception occurs. The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. Operation: 32, 64 T: if GPR [rs] > GPR [rt] then TrapException endif Exceptions: Trap exception 658 CHAPTER 27 CPU INSTRUCTION SET DETAILS TGEI 31 Trap If Greater Than Or Equal Immediate 26 25 21 20 16 15 TGEI 0 REGIMM 000001 6 rs 5 TGEI 01000 5 immediate 16 Format: TGEI rs, immediate Description: The 16-bit immediate is sign-extended and compared to the contents of general register rs. Considering both quantities as signed integers, if the contents of general register rs are greater than or equal to the sign-extended immediate, a trap exception occurs. Operation: 32 T: if GPR [rs] > (immediate15) TrapException endif 64 T: if GPR [rs] > (immediate15) TrapException endif 48 16 || immediate15...0 then || immediate15...0 then Exceptions: Trap exception 659 CHAPTER 27 CPU INSTRUCTION SET DETAILS TGEIU 31 Trap If Greater Than Or Equal Immediate Unsigned 26 25 21 20 16 15 TGEIU 0 REGIMM 000001 6 rs 5 TGEIU 01001 5 immediate 16 Format: TGEIU rs, immediate Description: The 16-bit immediate is sign-extended and compared to the contents of general register rs. Considering both quantities as unsigned integers, if the contents of general register rs are greater than or equal to the signextended immediate, a trap exception occurs. Operation: 32 T: if (0 || GPR [rs]) > (0 || (immediate15) TrapException endif 64 T: if (0 || GPR [rs]) > (0 || (immediate15) TrapException endif 48 16 || immediate15...0) then || immediate15...0) then Exceptions: Trap exception 660 CHAPTER 27 CPU INSTRUCTION SET DETAILS TGEU 31 26 25 Trap If Greater Than Or Equal Unsigned 21 20 16 15 65 TGEU 0 SPECIAL 000000 6 rs 5 rt 5 code 10 TGEU 110001 6 Format: TGEU rs, rt Description: The contents of general register rt are compared to the contents of general register rs. Considering both quantities as unsigned integers, if the contents of general register rs are greater than or equal to the contents of general register rt, a trap exception occurs. The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. Operation: 32, 64 T: if (0 || GPR [rs]) > (0 || GPR [rt]) then TrapException endif Exceptions: Trap exception 661 CHAPTER 27 CPU INSTRUCTION SET DETAILS TLBP 31 26 25 24 Probe TLB For Matching Entry 65 CO 1 TLBP 0 COP0 010000 6 000 0000 0 0000 19 0000 0000 TLBP 001000 6 1 Format: TLBP Description: The Index register is loaded with the address of the TLB entry whose contents match the contents of the EntryHi register. If no TLB entry matches, the high-order bit of the Index register is set. The architecture does not specify the operation of memory references associated with the instruction immediately after a TLBP instruction, nor is the operation specified if more than one TLB entry matches. Operation: 32 T: Index <- 1 || 0 25 || Undefined 6 for i in 0...TLBEntries - 1 if (TLB [i]95...77 = EntryHi31...13) and (TLB [i]76 or (TLB [i]71...64 = EntryHi7...0)) then Index <- 0 endif endfor 64 T: Index <- 1 || 0 25 26 || i5...0 || Undefined 6 for i in 0...TLBEntries - 1 if (TLB [i]167...141 and not (0 15 15 || TLB [i]216...205)) || TLB [i]216...205)) and = (EntryHi39...13) and not (0 Index <- 0 endif endfor 26 (TLB [i]140 or (TLB [i]135...128 = EntryHi7...0)) then || i5...0 Exceptions: Coprocessor unusable exception 662 CHAPTER 27 CPU INSTRUCTION SET DETAILS TLBR 31 26 25 24 Read Indexed TLB Entry 65 CO 1 TLBR 0 COP0 010000 6 000 0000 0 0000 19 0000 0000 TLBR 000001 6 1 Format: TLBR Description: The G bit (which controls ASID matching) read from the TLB is written into both of the EntryLo0 and EntryLo1 registers. The EntryHi and EntryLo registers are loaded with the contents of the TLB entry pointed at by the contents of the TLB Index register. The operation is invalid (and the results are unspecified) if the contents of the TLB Index register are greater than the number of TLB entries in the processor. Operation: 32 T: PageMask <- TLB [Index5...0]127...96 EntryHi <- TLB [Index5...0]95...64 and not TLB [Index5...0]127...96 EntryLo1 <- TLB [Index5...0]63...33 || TLB [Index5...0]76 EntryLo0 <- TLB [Index5...0]31...1 || TLB [Index5...0]76 64 T: PageMask <- TLB [Index5...0]255...192 EntryHi <- TLB [Index5...0]191...128 and not TLB [Index5...0]255...192 EntryLo1 <- TLB [Index5...0]127...65 || TLB [Index5...0]140 EntryLo0 <- TLB [Index5...0]63...1 || TLB [Index5...0]140 Exceptions: Coprocessor unusable exception 663 CHAPTER 27 CPU INSTRUCTION SET DETAILS TLBWI 31 26 25 24 Write Indexed TLB Entry 65 CO 1 TLBWI 0 COP0 010000 6 000 0000 0 0000 19 0000 0000 TLBWI 000010 6 1 Format: TLBWI Description: The TLB entry pointed at by the contents of the TLB Index register is loaded with the contents of the EntryHi and EntryLo registers. The G bit of the TLB is written with the logical AND of the G bits in the EntryLo0 and EntryLo1 registers. The operation is invalid (and the results are unspecified) if the contents of the TLB Index register are greater than the number of TLB entries in the processor. Operation: 32, 64 T: TLB [Index5...0] Coprocessor unusable exception 664 CHAPTER 27 CPU INSTRUCTION SET DETAILS TLBWR 31 26 25 24 Write Random TLB Entry 65 CO 1 TLBWR 0 COP0 010000 6 000 0000 0 0000 19 0000 0000 TLBWR 000110 6 1 Format: TLBWR Description: The TLB entry pointed at by the contents of the TLB Random register is loaded with the contents of the EntryHi and EntryLo registers. The G bit of the TLB is written with the logical AND of the G bits in the EntryLo0 and EntryLo1 registers. Operation: 32, 64 T: TLB [Random5...0] Coprocessor unusable exception 665 CHAPTER 27 CPU INSTRUCTION SET DETAILS TLT 31 26 25 21 20 Trap If Less Than 16 15 65 TLT 0 SPECIAL 000000 6 rs 5 rt 5 code 10 TLT 110010 6 Format: TLT rs, rt Description: The contents of general register rt are compared to general register rs. Considering both quantities as signed integers, if the contents of general register rs are less than the contents of general register rt, a trap exception occurs. The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. Operation: 32, 64 T: if GPR [rs] < GPR [rt] then TrapException endif Exceptions: Trap exception 666 CHAPTER 27 CPU INSTRUCTION SET DETAILS TLTI 31 26 25 Trap If Less Than Immediate 21 20 16 15 TLTI 0 REGIMM 000001 6 rs 5 TLTI 01010 5 immediate 16 Format: TLTI rs, immediate Description: The 16-bit immediate is sign-extended and compared to the contents of general register rs. Considering both quantities as signed integers, if the contents of general register rs are less than the sign-extended immediate, a trap exception occurs. Operation: 32 T: if GPR [rs] < (immediate15) TrapException endif 64 T: if GPR [rs] < (immediate15) TrapException endif 48 16 || immediate15...0 then || immediate15...0 then Exceptions: Trap exception 667 CHAPTER 27 CPU INSTRUCTION SET DETAILS TLTIU 31 26 25 Trap If Less Than Immediate Unsigned 21 20 16 15 TLTIU 0 REGIMM 000001 6 rs 5 TLTIU 01011 5 immediate 16 Format: TLTIU rs, immediate Description: The 16-bit immediate is sign-extended and compared to the contents of general register rs. Considering both quantities as unsigned integers, if the contents of general register rs are less than the sign-extended immediate, a trap exception occurs. Operation: 32 T: if (0 || GPR [rs]) < (0 || (immediate15) TrapException endif 64 T: if (0 || GPR [rs]) < (0 || (immediate15) TrapException endif 48 16 || immediate15...0) then || immediate15...0) then Exceptions: Trap exception 668 CHAPTER 27 CPU INSTRUCTION SET DETAILS TLTU 31 26 25 Trap If Less Than Unsigned 21 20 16 15 65 TLTU 0 SPECIAL 000000 6 rs 5 rt 5 code 10 TLTU 110011 6 Format: TLTU rs, rt Description: The contents of general register rt are compared to general register rs. Considering both quantities as unsigned integers, if the contents of general register rs are less than the contents of general register rt, a trap exception occurs. The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. Operation: 32, 64 T: if (0 || GPR [rs]) < (0 || GPR [rt]) then TrapException endif Exceptions: Trap exception 669 CHAPTER 27 CPU INSTRUCTION SET DETAILS TNE 31 26 25 21 20 Trap If Not Equal 16 15 65 TNE 0 SPECIAL 000000 6 rs 5 rt 5 code 10 TNE 110110 6 Format: TNE rs, rt Description: The contents of general register rt are compared to general register rs. If the contents of general register rs are not equal to the contents of general register rt, a trap exception occurs. The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. Operation: 32, 64 T: if GPR [rs] z GPR [rt] then TrapException endif Exceptions: Trap exception 670 CHAPTER 27 CPU INSTRUCTION SET DETAILS TNEI 31 26 25 Trap If Not Equal Immediate 21 20 16 15 TNEI 0 REGIMM 000001 6 rs 5 TNEI 01110 5 immediate 16 Format: TNEI rs, immediate Description: The 16-bit immediate is sign-extended and compared to the contents of general register rs. If the contents of general register rs are not equal to the sign-extended immediate, a trap exception occurs. Operation: 32 T: if GPR [rs] z (immediate15) TrapException endif 64 T: if GPR [rs] z (immediate15) TrapException endif 48 16 || immediate15...0 then || immediate15...0 then Exceptions: Trap exception 671 CHAPTER 27 CPU INSTRUCTION SET DETAILS XOR 31 26 25 21 20 Exclusive Or 16 15 11 10 65 XOR 0 SPECIAL 000000 6 rs 5 rt 5 rd 5 0 00000 5 XOR 100110 6 Format: XOR rd, rs, rt Description: The contents of general register rs are combined with the contents of general register rt in a bit-wise logical exclusive OR operation. The result is placed into general register rd. Operation: 32, 64 T: GPR [rd] <- GPR [rs] xor GPR [rt] Exceptions: None 672 CHAPTER 27 CPU INSTRUCTION SET DETAILS XORI 31 26 25 Exclusive OR Immediate 21 20 16 15 XORI 0 XORI 001110 6 rs 5 rt 5 immediate 16 Format: XORI rt, rs, immediate Description: The 16-bit immediate is zero-extended and combined with the contents of general register rs in a bit-wise logical exclusive OR operation. The result is placed into general register rt. Operation: 32 64 T: T: GPR [rt] <- GPR [rs] xor (0 GPR [rt] <- GPR [rs] xor (0 16 || immediate) || immediate) 48 Exceptions: None 673 CHAPTER 27 CPU INSTRUCTION SET DETAILS 27.6 CPU INSTRUCTION OPCODE BIT ENCODING The remainder of this chapter presents the opcode bit encoding for the CPU instruction set (ISA and extensions), as implemented by the VR4102. Figure 27-2 lists the VR4102 Opcode Bit Encoding. Figure 27-1. VR4102 Opcode Bit Encoding (1/2) 28...26 0 SPECIAL ADDI COP0 DADDIH LB SB * * 2...0 0 SLL JR MFHI MULT ADD MADD16 TGE DSLLH 18...16 0 BLTZ TGEI BLTZAL * Opcode 1 REGIMM ADDIU S DADDIUH LH SH S S 2 J SLTI S LDLH LWL SWL S S 3 JAL SLTIU * LDRH LW SW * * 4 BEQ ANDI BEQL * LBU SDLH * * 5 BNE ORI BNEL * LHU SDRH S S 6 BLEZ XORI BLEZL * LWR SWR S S 7 BGTZ LUI BGTZL * LWUH CACHEG LDH SDH 31...29 0 1 2 3 4 5 6 7 SPECIAL function 1 * JALR MTHI MULTU ADDU DMADD16 5...3 0 1 2 3 4 5 6 7 2 SRL * MFLO DIV SUB SLT TLT DSRLH 3 SRA * MTLO DIVU SUBU SLTU TLTU DSRAH 4 SLLV SYSCALL DSLLVH DMULTH AND DADDH TEQ DSLL32H 5 * BREAK * DMULTUH OR DADDUH * * 6 SRLV * DSRLVH DDIVH XOR DSUBH TNE DSRL32H 7 SRAV SYNC DSRAVH DDIVUH NOR DSUBUH * DSRA32H TGEU * REGIMM rt 1 BGEZ TGEIU BGEZAL * 2 BLTZL TLTI 3 BGEZL TLTIU 4 * TEQI * * 5 * * * * 6 * TNEI * * 7 * * * * 20...19 0 1 2 3 BLTZALL BGEZALL * * 674 CHAPTER 27 CPU INSTRUCTION SET DETAILS Figure 27-1. VR4102 Opcode Bit Encoding (2/2) 23...21 0 MF BC COP0 rs 1 DMFH J 2 J J 3 J J CO 4 MT J 5 DMTH J 6 J J 7 J J 25, 24 0 1 2 3 20...19 0 1 2 3 18...16 0 BCF J J J 2...0 0 I TLBP [ ERET F I I I I COP0 rt 1 BCT J J J 2 BCFL J J J 3 BCTL J J J 4 J J J J 5 J J J J 6 J J J J 7 J J J J CP0 Function 1 TLBR I I I STANDB I I I 2 TLBWI I I I SUSPEND 5...3 0 1 2 3 4 5 6 7 3 I I I I HIBERNATE 4 I I I I I I I I 5 I I I I I I I I 6 TLBWR I I I I I I I 7 I I I I I I I I I I I I I I Key: * J G I [ F Operation codes marked with an asterisk cause reserved instruction exceptions in all current implementations and are reserved for future versions of the architecture. Operation codes marked with a gamma cause a reserved instruction exception. They are reserved for future versions of the architecture. Operation codes marked with a delta are valid only for VR4102 processors with CP0 enabled, and cause a reserved instruction exception on other processors. Operation codes marked with a phi are invalid but do not cause reserved instruction exceptions in VR4102 implementations. Operation codes marked with a xi cause a reserved instruction exception on VR4102 processor. Operation codes marked with a chi are valid on R4x00 and VR4102 only. Operation codes marked with epsilon are valid when the processor operating as a 64-bit processor. These instructions will cause a reserved instruction exception if 64-bit operation is not enabled. Operation codes marked with a pi are invalid and cause coprocessor unusable exception. H S 675 [MEMO] 676 CHAPTER 28 VR4102 COPROCESSOR 0 HAZARDS The VR4100 CPU core avoids contention of its internal resources by causing a pipeline interlock in such cases as when the contents of the destination register of an instruction are used as a source in the succeeding instruction. Therefore, instructions such as NOP must not be inserted between instructions. However, interlocks do not occur on the operations related to the CP0 registers and the TLB. Therefore, contention of internal resources should be considered when composing a program which manipulates the CP0 registers or the TLB. The CP0 hazards define the number of NOP instructions which is required to avoid contention of internal resources, or the number of instructions unrelated to contention. This chapter describes the CP0 hazards of the VR4100 CPU core. The CP0 hazards of the VR4100 CPU core are equally or less stringent than those of the VR4000; Table 28-1 lists the Coprocessor 0 hazards of the VR4100 CPU core. Code which complies with these hazards will run without modification on the VR4000. The contents of the CP0 registers or the bits in the "Source" column of this table can be used as a source after they are fixed. The contents of the CP0 registers or the bits in the "Destination" column of this table can be available as a destination after they are stored. Based on this table, the number of NOP instructions required between instructions related to the TLB is computed by the following formula, and so is the number of instructions unrelated to contention: (Destination Hazard number of A) - [(Source Hazard number of B) + 1] As an example, to compute the number of instructions required between an MTC0 and a subsequent MFC0 instruction, this is: (5) - (3 + 1) = 1 instruction The CP0 hazards do not generate interlocks of pipeline. Therefore, the required number of instruction must be controlled by program. 677 CHAPTER 28 VR4102 COPROCESSOR 0 HAZARDS Table 28-1. VR4102 Coprocessor 0 Hazards Instruction or Event Source CP0 Data Used, Stage Used MTC0 MFC0 TLBR TLBWI TLBWR TLBP ERET CPR [rd] Index, TLB Index or Random, PageMask, EntryHi, EntryLo0, EntryLo1 PageMask, EntryHi EPC or ErrorEPC, TLB Status CACHE Index Load Tag CACHE Index Store Tag CACHE Hit ops. Load/Store TagLo, TagHi, PErr cache line EntryHi [ASID], Status [KSU, EXL, ERL, RE], Config [K0C], TLB Config [AD, EP] WatchHi, WatchLo Load/Store exception Instruction fetch exception Instruction fetch EntryHi [ASID], Status [KSU, EXL, ERL, RE], Config [K0C] TLB Coproc. usable test Interrupt signals sampled TLB shutdown Status [CU, KSU, EXL, ERL] Cause [IP], Status [IM, IE, EXL, ERL] 2 3 3 3 cache line 5 3 2 2 PageMask, EntryHi, EntryLo0, EntryLo1 TLB 5 5 No. of cycles Destination CP0 Data Written, Stage Available CPR [rd] 5 No. of cycles 2 2 2 Index Status [EXL, ERL] 6 4 TagLo, TagHi, PErr 5 3 3 EPC, Status, Cause, 5 BadVAddr, Context, XContext EPC, Status Cause, BadVAddr, Context, XContext 4 5 2 2 2 Status [TS] 2 (Inst.), 4 (Data) 678 CHAPTER 28 VR4102 COPROCESSOR 0 HAZARDS Cautions 1. If the setting of the K0 bit in the Config register is changed to uncached mode by MTC0, the accessed memory area is switched to the uncached one at the instruction fetch of the third instruction after MTC0. 2. A stall of several instructions occurs if a jump or branch instruction is executed immediately after the setting of the ITS bit in the Status register. Remarks 1. The instruction following MTC0 must not be MFC0. 2. The five instructions following MTC0 to Status register that changes KSU and sets EXL and ERL may be executed in the new mode, and not kernel mode. This can be avoided by setting EXL first, leaving KSU set to kernel, and later changing KSU. 3. There must be two non-load, non-CACHE instructions between a store and a CACHE instruction directed to the same primary cache line as the store. The status during execution of the following instruction for which CP0 hazards must be considered is described below. (1) MTC0 Destination: The completion of writing to a destination register (CP0) of MTC0. (2) MFC0 Source: The confirmation of a source register (CP0) of MFC0. (3) TLBR Source: The confirmation of the status of TLB and the Index register before the execution of TLBR. Destination: The completion of writing to a destination register (CP0) of TLBR. (4) TLBWI, TLBWR Source: The confirmation of a source register of these instructions and registers used to specify a TLB entry. Destination: The completion of writing to TLB by these instructions. (5) TLBP Source: The confirmation of the PageMask register and the EntryHi register before the execution of TLBP. Destination: The completion of writing the result of execution of TLBP to the Index register. (6) ERET Source: The confirmation of registers containing information necessary for executing ERET. Destination: The completion of the processor state transition by the execution of ERET. (7) CACHE Index Load Tag Destination: The completion of writing the results of execution of this instruction to the related registers. 679 CHAPTER 28 VR4102 COPROCESSOR 0 HAZARDS (8) CACHE Index Store Tag Source: The confirmation of registers containing information necessary for executing this instruction. (9) Coprocessor Usable Test Source: The confirmation of modes set by the bits of the CP0 registers in the "Source" column. When accessing the CP0 registers in User mode after the content of the CU0 bit of the Status register is modified, or when executing an instruction such as TLB instructions, CACHE instructions, or branch instructions which use the resource of the CP0. 2. When accessing the CP0 registers in the operating mode set in the Status register after the KSU, EXL, and ERL bits of the Status register are modified. Examples 1. (10) Instruction Fetch Source: The confirmation of the operating mode and TLB necessary for instruction fetch. When changing the operating mode from User to Kernel and fetching instructions after the KSU, EXL, and ERL bits of the Status register are modified. 2. When fetching instructions using the modified TLB entry after TLB modification. Examples 1. (11) Instruction Fetch Exception Destination: The completion of writing to registers containing information related to the exception when an exception occurs on instruction fetch. (12) Interrupts Source: The confirmation of registers judging the condition of occurrence of interrupt when an interrupt factor is detected. (13) Loads/Sores Source: The confirmation of the operating mode related to the address generation of Load/Store instructions, TLB entries, the cache mode set in the K0 bit of the Config register, and the registers setting the condition of occurrence of a Watch exception. Example When Loads/Stores are executed in the kernel field after changing the mode from User to Kernel. (14) Load/Store Exception Destination: The completion of writing to registers containing information related to the exception when an exception occurs on load or store operation. (15) TLB Shutdown Destination: The completion of writing to the TS bit of the Status register when a TLB shutdown occurs. 680 CHAPTER 28 VR4102 COPROCESSOR 0 HAZARDS Table 28-2 indicates examples of calculation. Table 28-2. Calculation Example of CP0 Hazard and the Number of Instructions Inserted Destination Source Contending internal resource TLB Entry TLB Entry TLB Entry Status [CU] EntryHi EntryLo0 Index EntryHi EPC Status Status [IE] Number of instructions inserted 2 1 2 2 1 2 2 2 2 2 2 Formula TLBWR/TLBWI TLBWR/TLBWI TLBWR/TLBWI MTC0, Status [CU] TLBR MTC0 EntryLo0 TLBP MTC0 EntryHi MTC0 EPC MTC0 Status MTC0 Status [IE] Note TLBP Load or Store using newly modified TLB Instruction fetch using newly modified TLB Coprocessor instruction which requires the setting of CU MFC0 EntryHi TLBWR/TLBWI MFC0 Index TLBP ERET ERET Instruction which causes an interrupt 5 - (2 + 1) 5 - (3 + 1) 5 - (2 + 1) 5 - (2 + 1) 5 - (3 + 1) 5 - (2 + 1) 6 - (3 + 1) 5 - (2 + 1) 5 - (2 + 1) 5 - (2 + 1) 5 - (2 + 1) Note The number of hazards is undefined if the instruction execution sequence is changed by exceptions. In such a case, the minimum number of hazards until the IE bit value is confirmed may be the same as the maximum number of hazards until an interrupt request occurs which is pending and enabled. 681 [MEMO] 682 CHAPTER 29 PLL PASSIVE COMPONENTS The Phase Locked Loop circuit requires several passive components for proper operation, which are connected to VDDP and GNDP as illustrated in Figure 29-1. Figure 29-1. Example of Connection of PLL Passive Components VDD R VDDP VR4102 GNDP C1 C3 C2 R GND Remarks1. C1, C2, C3 capacitors and R resistors are mounted on the printed circuit board. 2. Since the value for the components depends upon the application system, the optimum values for each system should be decided after repeated experimentation. It is essential to isolate the analog power and ground for the PLL circuit (VDDP/GNDP) from the regular power and ground (VDD/GND). Initial evaluations have yielded good results with the following values: R=5: C1 = 1 nF C2 = 2 nF C3 = 10 PF Since the optimum values for the filter components depend upon the application and the system noise environment, these values should be considered as starting points for further experimentation within your specific application. In addition, the chokes (inductors: L) can be considered for use as an alternative to the resistors (R) for use in filtering the power supply. 683 [MEMO] 684 APPENDIX A DIFFERENCES BETWEEN VR4102 AND VR4101 A.1 SUMMARY OF DIFFERENCES Item Cache size ISA interface Bus sizing Bus hold I/O space Memory space LCD memory space VR4102 Instruction: 4 Kbytes, data: 1 Kbyte 16-/8-bit dynamic bus sizing Available 64 Mbytes 64 Mbytes VR4101 Instruction: 2 Kbytes, data: 1 Kbyte Select 16-/8-bit bus with address spaces Not available 4 Mbytes 4 Mbytes Switches between LCD mode and high-speed Supports only LCD mode memory mode Memory controller Max. DRAM capacity 32 Mbytes (EDO type) Max. ROM capacity DRAM type ROM type 32 Mbytes 16 Mbits, 64 Mbits 32 Mbits, 64 Mbits 4 factors Connected to AIU and FIR Uses a DMA space for each page 8 Mbytes 16 Mbytes 16 Mbits 16 Mbits, 32 Mbits 3 factors Connected to AIU, PIU, KIU, and SIU Uses a DMA space linearly 3 channels: 24 bits x 1 (32.768 kHz) 48 bits x 1 (32.768 kHz) 31 bits x 1 (for performance test, TClock) Supports up to 64 keys Supports PWM/Buzz output Power-on factor DMA controller Timer, counter 4 channels: 24 bits x 2 (32.768 kHz) 48 bits x 1 (32.768 kHz) 25 bits x 1 (for performance test, TClock) Keyboard interface Audio interface Supports 64/80/96 keys Supports PCM input/output On-chip D/A converter Touch panel interface On-chip 10-bit A/D converter On-chip touch panel controller External 10/12-bit A/D converter External touch panel controller NEC original x 2 (Max. data rate: 115.2 kbps) Serial interface NS16650 compatible x 1 (Max. data rate: 1.152 Mbps) NEC original x 1 (Max. data rate: 115.2 kbps Max.) Ports for LED lighting MODEM interface Available Not available On-chip interface supporting software MODEM Not available (equivalent to PCT288I) IrDA interface General-purpose I/O ports Clock input FIR (Max. data rate: 4 Mbps) 49 Max. (including alternate-function pins) 32.768 kHz (input to CG), 18.432 MHz (input to CG), 48 MHz (directly connected to on-chip IrDA interface) SIR (Max. data rate: 115.2 kbps) 12 Max. 32.768 kHz (input to CG) Package 216 pin LQFP, 224-pin FBGA 160 pin LQFP 685 APPENDIX A DIFFERENCES BETWEEN VR4102 AND VR4101 A.2 DETAILS OF DIFFERENCES A.2.1 CPU Core (1) Cache Size The instruction cache of the VR4102 is 4K bytes in size, on the other hand, that of the VR4101 is 2K bytes. The size of the data cache of the VR4102 is 1K bytes which is the same as that of the VR4101. To specify cache data address used for CACHE instruction, the VR4102 uses bit 31..12 of the TagLo register, in contrast to the VR4101 which uses bit 31..11. For data cache, both the VR4102 and the VR4101 use bit 13..10 of the TagLo register. (2) Settings of the Config Register Bit 12 of the Config register (CS) indicates cache size mode, bit 11..9 (IC) indicates instruction cache size, and bit 8..5 (DC) indicates data cache size. In the VR4102, CS is set to 1 (cache of small capacity), IC to 010 (4K bytes), and DC to 000 (1K bytes). In the VR4101, bit 12..5 of the Config register are not defined and fix to 0 as a reserved field. Bit 27..24 of the Config register (EP) indicates transfer data pattern in the cache writeback. This field must be set to 0000 (DD) in the VR4102, on the other hand, it must be set to 0011 (DxDx) in the VR4101. A.2.2 Address Mapping (1) Memory Area In the VR4102, 16M and 64M bits are selectable for DRAM space size, though only a 16M-bit DRAM can be connected to the VR4101. Similarly, 32M and 64M bits are selectable for ROM space size in the VR4102, though only a 32M-bit ROM can be connected to the VR4101. (2) LCD Space The LCD space is mapped to 16M-byte area of 0x0A00 0000 through 0x0AFF FFFF in both the VR4102 and the VR4101. However, the VR4102 can also use this area as the high speed memory space, and the switching is set in one of the BCU registers. (3) ISA Spaces The ISA memory and I/O spaces have a size of 64M bytes respectively in the VR4102. Those in the VR4101 have 4M bytes in total (2M bytes for 8-bit bus, 2M bytes for 16-bit bus). In addition, the VR4102 supports 16/8-bit dynamic sizing for the ISA bus. (4) Internal I/O Space The internal I/O space is expanded to 32M bytes in the VR4102 compared to that of the VR4101 which has a size of 16M bytes. 686 APPENDIX A DIFFERENCES BETWEEN VR4102 AND VR4101 A.2.3 BCU (1) Setting of BCU Transaction In the VR4101, the intervals of bus transactions and the number of repetitions in the enabled BCU transaction intervals can be selectable. This function is deleted in the VR4102. (2) Memory Access Control 16 and 32 bits are selectable as the data bus width with DBUS32 pin at reset in the VR4102 except for ISA memory area, on the other hand, the bus width is fixed to 16 bits in the VR4101. Though both the VR4102 and the VR4101 can select three memory types which are DRAM, masked ROM, and Flash memory, their memory sizes and mapping method are different as summarized below. Memory type DRAM Masked ROM VR4102 16M-bit/64M-bit EDO x 16 bits (access time: 60 ns) 32M-bit/64M-bit ordinary or page type x 16 bits 16-bit bus mode: selected as banks0/1 or 2/3 32-bit bus mode: selected as bank0 or 1 Flash memory 16-bit bus mode: selected as banks0/1 or 2/3 32-bit bus mode: selected as bank0 or 1 (3) LCD Space The LCD space is used only for LCD access in the VR4101, while it can be used for either LCD access or highspeed memory access in the VR4102. Which of LCD or high-speed memory the LCD space is used for is selected in BCUCNT1REG register. When high-speed memory is selected, LCDCS# pin becomes active. The access time for LCD is selectable among 2, 4, 6, and 8 TClock cycles in both the VR4102 and the VR4101. For high-speed memory in the VR4102, the access time is selectable among 1, 2, 3, 4, 5, 6, 7, and 8 TClock cycles. These selections of access time are set in BCUSPEEDREG register. When transferring LCD data, inverting the data values or not is selectable in the VR4102 and is set in BCUCNT2REG register. On the other hand, the VR4101 always inverts the values at LCD data transfer. (4) ISA Space In the VR4102, the bus size is dynamically controlled at every bus cycle with IOCS# and MEMCS# pins. In the VR4101, the bus size is fixed to 8 or 16 bits and is distinguished by the accessed address space. (5) Others The VR4102 has bus hold function and can make ISA, LCD, and memory interfaces into bus hold state. The VR4101 has no bus hold function, and therefore the CPU is always master state. Bit 11..8 and bit 3..0 of PREVIDREG register indicate the revision number of the on-chip peripheral units in both the VR4102 and the VR4101. In addition, bit 15..12 indicates the processor revision number in the VR4102, though it is fixed to 0 in the VR4101. The remaining bits, bit 7..4, are fixed to 0 in both processors. To use the whole ROM space can be selected VR4101 16M-bit EDO x 16 bits (access time: 60 ns) 32M-bit ordinary or page type x 16 bits The whole ROM space is selected 687 APPENDIX A DIFFERENCES BETWEEN VR4102 AND VR4101 A.2.4 DMA (1) Sources of DMA The VR4102 uses DMA transfer for AIU reception, AIU transmission, and FIR transmission/reception (in priority order). On the other hand, the VR4101 uses DMA transfer for AIU, PIU, SIU reception, SIU transmission, and KIU (in priority order). (2) DMA Operation The VR4102 reloads the DMA base address every time the DMA transfer reaches page boundary. The VR4101 uses DMA address space linearly which starts at DMA base address. For more details about DMA address manipulation, see Chapter 11. A.2.5 ICU (1) Sources of Interrupts Compared with the VR4101, five interrupt sources, HSP, LED, FIR, RTC Long timer 2, and TClock counter, are newly added in the VR4102 ICU. Three more software interrupts which are caused by setting the SOFTINTREG register are also added. The number of interrupt factors are changed in eight interrupt sources which are SIU, DSIU, GIU, KIU, AIU, PIU, KIU in Suspend mode, and PIU in Suspend mode. (2) Notification to the CPU Core In the VR4102, NMI and Int[3..0] signals are used to notify interrupt requests to the CPU core, in contrast to the VR4101 which uses NMI and Int[1..0] signals. A.2.6 PMU (1) Power-On Function Compared with the VR4101, GPIO[3..0] and GPIO[12..9] inputs are added in the VR4102 as a CPU activation factor. Especially, GPIO[3] can be used without any settings immediately after RTCRST. (2) BATTLOCK and CARDLOCK Notifications No dedicated pins for BATTLOCK and CARDLOCK functions are assigned in the VR4102. assigned to either of GPIO[12..9] pins and they are manipulated as two of GIU interrupts. A.2.7 RTC (1) RTC Long Timers The VR4102 has two RTC Long timers, on the other hand the VR4101 has only one. (2) TClock Counter TClock counter of the VR4102 is 25-bit long which is 6 bits shorter than that of the VR4101. TClock counter of the VR4102 is added as one of the interrupt factors, and an interrupt request occurs when its value becomes 1. In the VR4101, no interrupt request is caused by TClock counter. They must be 688 APPENDIX A DIFFERENCES BETWEEN VR4102 AND VR4101 A.2.8 GIU (1) GPIO Pins The VR4102 has 49 general-purpose I/O pins and 33 of them have alternate functions, while the VR4101 has 12 general I/O pins and none of them have alternate functions. GPIO[15] pin of the VR4102 is assigned as DCD# input which has dedicated pin in the VR4101. In both the VR4102 and the VR4101, GIU controls DCD# input as well as GPIO pins. GPIO pins are also used as interrupt request inputs except for GPIO[49..32] of the VR4102, and in which power modes an interrupt request is enabled is different from each GPIO pin. The functions of GPIO pins are as summarized below. Pins I/O Interrupt input Enabled power mode VR4102 GPIO[49] GPIO[48] GPIO[47..44] GPIO[43..32] GPIO[31..16] GPIO[15] GPIO[14] GPIO[13] GPIO[12] GPIO[11] GPIO[10..9] GPIO[8..4] GPIO[3..0] O I/O I/O O I/O I I/O I/O I/O I/O I/O I/O I/O N/A N/A N/A N/A A A A A A A A A A Standby Standby Standby Standby Standby Hibernate Suspend Suspend Suspend Suspend Suspend Standby Hibernate Standby Suspend Standby Standby VR4101 Hibernate Alternative functions in VR4102 DBUS32 DSIU pins KSCAN[11..0] DATA[31..16] DCD# 2 1 Notes Notes 1. This pin is assigned as DCD# input in the VR4102. 2. This pin does not exist in the VR4101. DCD input is internally connected to the corresponding register bits for GPIO[13] in GIU and the VR4101 manipulates those bits as input only. (2) Interrupt Input Control In both the VR4102 and the VR4101, either edge, high level, or low level of the input signal is selectable as an interrupt input trigger. In the VR4102, whether interrupt requests are held in GIU or not is selectable, while they are not held in the VR4101. 689 APPENDIX A DIFFERENCES BETWEEN VR4102 AND VR4101 A.2.9 PIU PIU of the VR4102 is greatly changed from that of the VR4101 as summarized below. Item A/D converter Data transfer Data buffers VR4102 On-chip (10 bits) Transfer to buffer in PIU Four buffers (two pages each) for coordinate data only Four buffers for A/D scan Scan types Coordinate data scan Command scan A/D scan A/D port scan activation states Panel applied voltage stabilization standby time counter Panel applied voltage during low- All four touch panel pins are at low voltage mode Panel state during disable state level Touch detection state (Interrupts do not occur when CPU is in Hibernate mode.) Handling of valid data when data loss occurs Data interrupt Three types of special-purpose interrupts (two coordinate data interrupts, A/D scan interrupt, and command scan interrupt) PIUDataRdyIntr No Yes Two types of page boundary interrupts Valid data is always retained Valid data is overwritten All four touch panel pins are at Hi-Z All four touch panel pins are at Hi-Z Standby, WaitPen Touch, Interval 6 bits Coordinate data scan Command scan Main battery scan Sub battery scan Standby 4 bits DMA transfer One buffer VR4101 External (10/12 bits) 690 APPENDIX A DIFFERENCES BETWEEN VR4102 AND VR4101 A.2.10 AIU (1) Audio Output Mode The PCM output is employed in the VR4102 as an audio output mode. In the VR4101, Buzzer or PWM output is selectable. (2) Audio Input Mode The VR4102 has an analog audio input which is connected to the on-chip A/D converter. The VR4101 does not support any audio inputs. (3) Audio Data Transfer The VR4102 uses DMA transfer to prepare PCM data in the output operation and to store sampled data in the input operation. In the VR4101, output frequency and period for the Buzz mode are set in the AIU registers, or output high level and low level width for the PWM mode are prepared with DMA transfer. (4) Volume Control Volume of the audio outputs is controlled by an external circuit or by shifting data input to D/A converter in the VR4102. In the VR4101, four steps of audio output volume can be set in the AIUMUTEREG register and are controlled by an external circuit based on the settings in the register. A.2.11 KIU (1) Number of Keys Supported In the VR4102, the number of scan lines used is selectable among 8, 10, and 12 by setting the SCANLINE register, which determines the number of keys enabled to either of 64, 80, or 96. The VR4102 can detect when any of enabled keys are pressed using selected scan lines and 8 detection lines. The VR4101 can detect when any of 64 keys are pressed using 8 scan lines and 8 detection lines. When the VR4102 uses only 8 or 10 scan lines, the unused scan lines can be used as general-purpose output ports. When the KIU is disabled in the VR4102, all the scan lines (KSCAN[11..0] pins) can be used as generalpurpose outputs (GPIO[43..32]). (2) LCD Brightness Control The VR4101 has LCD brightness control pins which are alternately used as KCSAN[1..0] pins and indicate the contents of EVVOLREG register to specify brightness. The VR4102 has no pins for LCD brightness control. (3) KIU Data Transfer The VR4102 transfers KIU data by reading data buffers when an interrupt occurs, while the VR4101 transfers with DMA. 691 APPENDIX A DIFFERENCES BETWEEN VR4102 AND VR4101 A.2.12 DSIU (1) Hardware Flow Control The VR4102 has two pins for hardware flow control, DCTS# and DRTS#, while the VR4101 has no pins for it. (2) Supported Interrupts The VR4102 DSIU supports receive error interrupt, receive completion interrupt, transmit completion interrupt, and CTS interrupt. The VR4101 DSIU supports receive error interrupt, receive completion interrupt, and transmit completion interrupt. (3) Alternative Functions of DSIU Pins The VR4102 DSIU pins can be used as general-purpose output port, GPIO[47..44], when DSIU is disabled. Those of the VR4101 have no alternative functions. A.2.13 SIU The VR4102 SIU is newly designed and is functionally compatible with NS16550 in contrast to that of the VR4101 which is originally designed by NEC. Their differences are as summarized below. Item Architecture Maximum data rate IR communication Data transfer Character length Stop bit length Parity check Framing error Break transmission Break detection Receive overrun error Flow control pins Transmit data flow 1.15 Mbps Available Read out of FIFO buffers by software 5, 6, 7, or 8 bits 1, 1.5 (for 5 bits), or 2 (for 6, 7, or 8 bits) Checked/generated is selectable Automatically detected Available Automatically detected Automatically detected RTS#, CTS#, DTR#, DSR#, DCD# 16450 mode: from SIUTH register to transmit shift register FIFO mode: from FIFO (16 bytes) to transmit shift register Receive data flow 16450 mode: from receive shift register to SIURB register FIFO mode: from receive shift register to FIFO (16 bytes) From SIURXDATREG to DMA (2K bytes) VR4102 Functionally compatible with NS16550 NEC original 115 kbps Available DMA 7 or 8 bits 1 or 2 Checked/not generated (substituted by software) Automatically detected Available Automatically detected Occurs receive data lost interrupt RTS#, CTS#, DTR#, DSR#, DCD From DMA (2K bytes) to SIUTXDATREG VR4102 692 APPENDIX A DIFFERENCES BETWEEN VR4102 AND VR4101 A.2.14 Newly Added Units The VR4102 has three newly designed peripheral units as described below which the VR4101 does not have. (1) LED This unit is used to control lighting of an LED. This unit features as below: * * * High level width (up to 2 seconds), low level width (up to 8 seconds), and the number of blink can be set Supports stop interrupt request Enabled during Standby, Suspend, and Hibernate modes (2) HSP This unit is used to realize a software MODEM with externally connected CODEC and DAA blocks. The HSP unit of the VR4102 is compatible with PCT288I produced by PCTel. The assigned functions of software and each block are as below. Software: protocol calculation, CODEC control, error correction, and OS interface HSP unit: serial/parallel conversion of 16-bit data, control of status pins, and FIFO buffer management CODEC: D/A, A/D conversion and operation clock supply based on MCLK of HSP unit DAA: interface for CODEC data and telephone circuits (3) FIR This unit is used for IrDA communication in high-speed data transfer. Supported transfer rates includes 0.576M, 1.152M, and 4M bps. 693 [MEMO] 694 APPENDIX B INDEX A A/D converter ... 381, 383, 422 A/D port scan ... 404 Access data size ... 247 Address error exception ... 180 Address translation ... 119, 120 Addressing ... 47 AIU ... 31, 409 AIU registers ... 39, 409 AIUIAHREG ... 275 AIUIALREG ... 275 AIUIBAHREG ... 273 AIUIBALREG ... 273 AIUINTREG ... 298 AIUOAHREG ... 278 AIUOALREG ... 278 AIUOBAHREG ... 276 AIUOBALREG ... 276 ASIM00REG ... 438 ASIM01REG ... 439 ASIS0REG ... 444 Audio Interface Unit (AIU) ... 31, 409 C Cache ... 51 Cache data integrity ... 220 Cache error check ... 212 Cache error exception ... 184 Cache error register ... 171 CACHE instruction ... 219, 220 Cache line ... 214, 218 Cache memory ... 213 Cache operations ... 217 Cache organization ... 214 Cache state transition ... 219 Cache states ... 218 Cause register ... 165 CLKSPEEDREG ... 245 Clock generator ... 43 Clock interface ... 53 Clock Mask Unit (CMU) ... 31, 289 Clock oscillator ... 54 CMU ... 31, 289 CMU register ... 34, 289 CMUCLKMSK ... 290 Code compatibility ... 115 Cold reset ... 207 Cold reset exception ... 177 Compare register ... 162 Computational instructions ... 86 Config register ... 150 Connection of address pins ... 246 Context register ... 160 Coordinate detection ... 382 Coprocessor 0 (CP0) ... 44, 49, 141 Coprocessor Unusable exception ... 187 Count register ... 161 CP0 ... 44, 49, 141 CP0 hazards ... 677 CP0 registers ... 49, 50, 141, 146 CPU ... 43 CPU bus interface ... 43 CPU core ... 43 CPU Instruction ... 46, 81, 525 CPU Instruction Set ... 46, 81, 525 CPU registers ... 45 CRCSR ... 508 Crystal oscillation ... 54 B BadVAddr register ... 161 Baud rates and divisors ... 466 BCU ... 31, 235 BCU registers ... 33, 235 BCUCNTREG 1 ... 236 BCUCNTREG 2 ... 238 BCUERRSTREG ... 241 BCURFCNTREG ... 242 BCURFCOUNTREG ... 244 BCUSPEEDREG ... 239 BEV ... 211 Bootstrap exception vector (BEV) ... 211 BPRM0REG ... 446 Branch address ... 93 Branch delay ... 102 Branch instruction ... 92, 528 Breakpoint exception ... 186 Bus Control Unit (BCU) ... 31, 235 Bus error exception ... 185 Bus hold ... 268 Bus interface ... 43 Bus mode ... 247 Bypassing ... 115 695 APPENDIX B INDEX D D/A converter ... 421 Data cache ... 44, 215 Data cache addressing ... 216 Data formats ... 47, 448 Data loss ... 405 DCU ... 31, 281 DCU registers ... 34, 281 Deadman's SW shutdown ... 320 Deadman's Switch ... 202 Deadman's Switch Unit (DSU) ... 31, 355 Debug Serial Interface Unit (DSIU) ... 32, 435 Defining access types ... 82 Direct Memory Access (DMA) ... 271, 421, 422, 513, 522 Direct Memory Access Address Unit (DMAAU) ... 31, 271 Direct Memory Access Control Unit (DCU) ... 31, 281 DMA priority levels ... 281 DMAAU ... 31, 271 DMAAU registers ... 33, 272 DMACR ... 512 DMAER ... 513 DMAIDLEREG ... 283 DMAMSKREG ... 285 DMAREQREG ... 286 DMARSTREG ... 282 DMASENREG ... 284 DPCNTR ... 501 DPINTR ... 500 DRAM ... 140 DRAM access ... 264 DRAM space ... 140 DSIU ... 32, 435 DSIU registers ... 40, 435 DSIUINTREG ... 301 DSIURESETREG ... 447 DSU ... 31, 355 DSU registers ... 37, 355 DSUCLRREG ... 358 DSUCNTREG ... 356 DSUSETREG ... 357 DSUTIMREG ... 359 DVALIDREG ... 418 EntryHi register ... 147 EntryLo register ... 147 EPC register ... 167 ErrorEPC register ... 171 ETIMEHREG ... 338 ETIMELREG ... 337 ETIMEMREG ... 337 Exception ... 109, 173 Exception conditions ... 112 Exception processing ... 157, 191 Exception processing registers ... 159 Exception Program Counter (EPC) register ... 167 Exception vector locations ... 173 External clock ... 54 F Fast IrDA Interface Unit (FIR) ... 32, 497 FIFO interrupt modes ... 470 FIFO polling mode ... 471 FIR ... 32, 497 FIR registers ... 42, 497 FIRAHREG ... 280 FIRALREG ... 280 FIRBAHREG ... 279 FIRBALREG ... 279 FIRCR ... 509 FIRINTREG ... 313 Flash memory ... 247 Flash memory interface ... 249 FRSTR ... 499 FSR ... 505 Fullspeed mode ... 210, 326 G General Purpose I/O Unit (GIU) ... 31, 361 GIU ... 31, 361 GIU registers ... 37, 362 GIUINTALSELH ... 374 GIUINTALSELL ... 373 GIUINTENH ... 370 GIUINTENL ... 369 GIUINTHREG ... 312 GIUINTHTSELH ... 376 GIUINTHTSELL ... 375 GIUINTLREG ... 300 GIUINTSTATH ... 368 GIUINTSTATL ... 367 GIUINTTYPH ... 372 GIUINTTYPL ... 371 GIUIOSELH ... 364 GIUIOSELL ... 363 E ECMPHREG ... 340 ECMPLREG ... 339 ECMPMREG ... 339 Elapsed Timer ... 335 Endianness ... 47, 48 696 APPENDIX B INDEX GIUPIODH ... 366 GIUPIODL ... 365 GIUPODATH ... 380 GIUPODATL ... 378 Interrupt exception ... 190 Interrupt request signal ... 232 INTR0REG ... 445 INTREG ... 420 IRSR1 ... 507 H HALTimer shutdown ... 204, 320 Hardware interrupts ... 232 Hibernate mode ... 211, 327 Hierarchy of memory ... 213 HSP ... 32, 481 HSP registers ... 41, 483 HSPCNTL ... 486 HSPDATA[15..0] ... 485 HSPERRCNT ... 493 HSPEXTIN ... 492 HSPEXTOUT ... 487 HSPFFSZ ... 489 HSPID ... 492 HSPID[7:0] ... 493 HSPINDEX[15..0] ... 485 HSPINIT ... 484 HSPMCLKD ... 488 HSPPCS[7:0] ... 493 HSPPCTEL[7:0] ... 493 HSPRxData ... 490 HSPSTS ... 491 HSPTOC ... 488 HSPTxData ... 485 J Joint TLB ... 52 JTLB ... 52 Jump instruction ... 92, 528 K Kernel expanded addressing mode ... 211 Kernel mode ... 127 Kernel mode address space ... 128 Keyboard Interface Unit (KIU) ... 32, 423 KIU ... 32, 423 KIU registers ... 40, 423 KIU sequencer ... 427, 428 KIUDAT0 ... 424 KIUDAT1 ... 424 KIUDAT2 ... 424 KIUDAT3 ... 424 KIUDAT4 ... 424 KIUDAT5 ... 424 KIUGPEN ... 433 KIUINT ... 431 KIUINTREG ... 299 KIURST ... 432 KIUSCANREP ... 425 KIUSCANS ... 427 KIUWKI ... 430 KIUWKS ... 429 I I/O registers ... 33 ICU ... 31, 291 ICU registers ... 35, 294 IE bit ... 212 IFR ... 517 Illegal access ... 251 IMR ... 504 Index register ... 146 Initialization interface ... 199 Instruction cache ... 43, 214 Instruction cache addressing ... 216 Instruction formats ... 46, 81 Instruction pipeline ... 53 Integer overflow exception ... 189 Interlock ... 109 Internal I/O space ... 139 Interrupt ... 231 Interrupt control ... 293 Interrupt Control Unit (ICU) ... 31, 291 Interrupt enable (IE) ... 212 L LCD ... 140 LCD control interface ... 250 LCD interface ... 263 LCD space ... 140 LED ... 32, 453 LED Control Unit (LED) ... 32, 453 LED registers ... 41, 453 LEDASTCREG ... 457 LEDCNTREG ... 456 LEDHTSREG ... 454 LEDINTREG ... 458 LEDLTSREG ... 455 Load delay ... 102 Load delay slot ... 82 Load instruction ... 82, 527 Load Linked Address (LLAddr) register ... 151 697 APPENDIX B INDEX Local loopback ... 473 M MAIUINTREG ... 305 MasterOut ... 53 MCNTREG ... 416 MCNVRREG ... 417 MDMADATREG ... 410 MDSIUINTREG ... 308 Memory management system (MMU) ... 52, 117 MFIRINTREG ... 316 MGIUINTHREG ... 315 MGIUINTLREG ... 307 MIDATREG ... 415 MIRCR ... 511 MKIUINTREG ... 306 MODEM Interface Unit (HSP) ... 32, 481 MODEMREG ... 437 MPIUINTREG ... 304 MRXF ... 522 MSYSINT1REG ... 302 MSYSINT2REG ... 314 N NMI exception ... 179 NMIREG ... 309 Non-maskable Interrupt (NMI) ... 231 O Opcode bit encoding ... 674 Operating modes ... 121 Operation when unbranched ... 93 Ordinary Interrupts ... 231 Ordinary ROM ... 248 P PageMask register ... 143, 147 PageROM ... 248 Parity error prohibit ... 212 Parity error register ... 170 PClock ... 53 Phase lock loop (PLL) ... 43 Physical address ... 135 Pin configuration ... 57 Pin functions ... 57, 62 Pipeline ... 99 PIU ... 32, 381 PIU registers ... 38, 386 PIUAB0REG ... 400 PIUAB1REG ... 400 PIUAB2REG ... 400 PIUAB3REG ... 400 PIUAMSKREG ... 397 PIUASCNREG ...395 PIUCIVLREG ... 398 PIUCMDREG ... 393 PIUCNTREG ... 387 PIUINTREG (ICU) ... 297 PIUINTREG (PIU) ... 390 PIUPB00REG ... 399 PIUPB01REG ... 399 PIUPB02REG ... 399 PIUPB03REG ... 399 PIUPB04REG ... 399 PIUPB10REG ... 399 PIUPB11REG ... 399 PIUPB12REG ... 399 PIUPB13REG ... 399 PIUPB14REG ... 399 PIUSIVLREG ... 391 PIUSTBLREG ... 392 PLL ... 43 PLL passive components ... 683 PMU ... 31, 319 PMU registers ... 35, 327 PMUCNT2REG ... 333 PMUCNTREG ... 330 PMUINT2REG ... 332 PMUINTREG ... 328 PORTREG ... 436 Power Management Unit (PMU) ... 31, 319 Power mode ... 210, 325 Power mode state transition ... 325 Power-on control ... 321 Power-on sequence ... 205 Precision of exceptions ... 158 Priority of exceptions ... 176 Privilege mode ... 211 Processor Revision Identifier (PRId) register ... 149 R Random register ... 146 RDR ... 503 Real-time Clock Unit (RTC) ... 31, 335 Refresh ... 267 Reserved Instruction exception ... 188 Reset control ... 319 Reset function ... 199 Reverse endian ... 211 REVIDREG ... 243 ROM ... 137 ROM access ... 252 698 APPENDIX B INDEX ROM interface ... 248 ROM space ... 137 RSTSW ... 201, 319 RTC ... 31, 335 RTC registers ... 36, 336 RTC reset ... 199, 319 RTCINTREG ... 353 RTCL1CNTHREG ... 344 RTCL1CNTLREG ... 343 RTCL1HREG ... 342 RTCL1LREG ... 341 RTCL2CNTHREG ... 348 RTCL2CNTLREG ... 347 RTCL2HREG ... 346 RTCL2LREG ... 345 RTCLong timer ... 335 RXB0LREG ... 441 RXB0RREG ... 440 RXFL ... 523 RXIR ... 515 RXSTS ... 519 Software interrupts ... 232 Software shutdown ... 203, 320 Special instructions ... 96 Stall conditions ... 113 Standby mode ... 210, 326 Status after reset ... 164 Status register ... 162 Store delay slot ... 82 Store instruction ... 82, 527 Supervisor expanded addressing mode ... 211 Supervisor mode ... 124 Supervisor mode address space ... 125 Suspend mode ... 210, 326 SYSINT1REG ... 295 SYSINT2REG ... 311 System Call exception ... 186 System Control Coprocessor (CP0) ... 44, 49, 141 System Control Coprocessor (CP0) instructions ... 97, 528 T TagHi register ... 152 TagLo register ... 152 TCLKCNTHREG ... 352 TCLKCNTLREG ... 351 TCLKHREG ... 350 TCLKLREG ... 349 TClock ... 53 Tclock Counter ... 335 TDR ... 502 TDREG ... 287 Timer interrupt ... 232 TLB ... 52, 117 TLB entry ... 142 TLB exceptions ... 181 TLB instructions ... 155 TLB Invalid exception ... 182 TLB Misses ... 155 TLB Modified exception ... 183 TLB Refill exception ... 181 Touch panel ... 381 Touch Panel Interface Unit (PIU) ... 32, 381 Touch/release detection ... 404 Translation Lookaside Buffer (TLB) ... 52, 117 Trap exception ... 188 TXFL ... 521 TXIR ... 514 TXS0LREG ... 443 TXS0RREG ... 442 S Scan sequencer ... 383, 425 SCANLINE ... 434 SCNTREG ... 413 SCNVRREG ... 414 SDMADATREG ... 411 SEQREG ... 419 Serial Interface Unit (SIU) ... 32, 461 Shutdown control ... 320 SIU ... 32, 461 SIU registers ... 41, 461 SIUDLL ... 463 SIUDLM ... 465 SIUFC ... 469 SIUIE ... 464 SIUIID ... 467 SIUIRSEL ... 478 SIULC ... 472 SIULS ... 474 SIUMC ... 473 SIUMS ... 476 SIURB ... 462 SIUSC ... 477 SIUTH ... 462 Slip conditions ... 114 SODATREG ... 412 Soft reset ... 208 Soft reset exception ... 178 SOFTINTREG ... 370 699 APPENDIX B INDEX U User expanded addressing mode ... 211 User mode ... 121 User mode address space ... 122 V Virtual address ... 117 Virtual-to-physical address translation ... 118 W Watch exception ... 189 WatchHi register ... 168 WatchLo register ... 168 Wired register ... 148 X XContext register ... 169 XTLB Refill exception ... 181 700 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